Paparazzi UAS  v5.17_devel-24-g2ae834f
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i2c_arch.c
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22 
29 #include "mcu_periph/i2c.h"
30 
31 #include BOARD_CONFIG
32 
33 #include <libopencm3/stm32/rcc.h>
34 #include <libopencm3/stm32/gpio.h>
35 #include <libopencm3/cm3/nvic.h>
36 #include <libopencm3/cm3/scb.h>
37 
38 #include "mcu_periph/gpio.h"
39 
40 
41 static bool i2c_stm32_idle(struct i2c_periph *periph) __attribute__((unused));
42 static bool i2c_stm32_submit(struct i2c_periph *periph, struct i2c_transaction *t) __attribute__((unused));
43 static void i2c_stm32_setbitrate(struct i2c_periph *periph, int bitrate) __attribute__((unused));
44 
45 
48 
49 
50 // Error bit mask
51 // XXX: consider moving this define into libopencm3
52 #define I2C_SR1_ERR_MASK (I2C_SR1_SMBALERT | \
53  I2C_SR1_TIMEOUT | \
54  I2C_SR1_PECERR | \
55  I2C_SR1_OVR | \
56  I2C_SR1_AF | \
57  I2C_SR1_ARLO | \
58  I2C_SR1_BERR)
59 
60 // Bit Control
61 
62 #define BIT_X_IS_SET_IN_REG(X,REG) (((REG) & (X)) == (X))
63 
64 // disable and enable irq functions are not implemented in libopencm3 defining them here
65 // XXX: consider moving this definitions into libopencm3
66 static inline void __disable_irq(void) { asm volatile("cpsid i"); }
67 static inline void __enable_irq(void) { asm volatile("cpsie i"); }
68 
69 // Critical Zones
70 
71 #define __I2C_REG_CRITICAL_ZONE_START __disable_irq();
72 #define __I2C_REG_CRITICAL_ZONE_STOP __enable_irq();
73 
74 
75 #ifndef NVIC_I2C_IRQ_PRIO
76 #define NVIC_I2C1_IRQ_PRIO 0
77 #define NVIC_I2C2_IRQ_PRIO 0
78 #define NVIC_I2C3_IRQ_PRIO 0
79 #else
80 #define NVIC_I2C1_IRQ_PRIO NVIC_I2C_IRQ_PRIO
81 #define NVIC_I2C2_IRQ_PRIO NVIC_I2C_IRQ_PRIO
82 #define NVIC_I2C3_IRQ_PRIO NVIC_I2C_IRQ_PRIO
83 #endif
84 
85 #if USE_I2C1 || USE_I2C2 || USE_I2C3
86 #if defined(STM32F1)
87 static void i2c_setup_gpio(uint32_t i2c)
88 {
89  switch (i2c) {
90 #if USE_I2C1
91  case I2C1:
93  gpio_set_mode(I2C1_GPIO_PORT, GPIO_MODE_OUTPUT_2_MHZ,
94  GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN,
96  break;
97 #endif
98 #if USE_I2C2
99  case I2C2:
101  gpio_set_mode(I2C2_GPIO_PORT, GPIO_MODE_OUTPUT_2_MHZ,
102  GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN,
104  break;
105 #endif
106  default:
107  break;
108  }
109 }
110 
111 #elif defined(STM32F4)
112 #ifndef I2C1_GPIO_AF
113 #define I2C1_GPIO_AF GPIO_AF4
114 #endif
115 
116 #ifndef I2C2_GPIO_AF
117 #define I2C2_GPIO_AF GPIO_AF4
118 #endif
119 
120 #ifndef I2C3_GPIO_SCL_AF
121 #define I2C3_GPIO_SCL_AF GPIO_AF4
122 #endif
123 #ifndef I2C3_GPIO_SDA_AF
124 #define I2C3_GPIO_SDA_AF GPIO_AF4
125 #endif
126 
127 static void i2c_setup_gpio(uint32_t i2c)
128 {
129  switch (i2c) {
130 #if USE_I2C1
131  case I2C1:
133  gpio_mode_setup(I2C1_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE,
135  gpio_set_output_options(GPIOB, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ,
137  gpio_set_af(I2C1_GPIO_PORT, I2C1_GPIO_AF, I2C1_GPIO_SCL | I2C1_GPIO_SDA);
138  break;
139 #endif
140 #if USE_I2C2
141  case I2C2:
143  gpio_mode_setup(I2C2_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE,
145  gpio_set_output_options(I2C2_GPIO_PORT, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ,
147  gpio_set_af(I2C2_GPIO_PORT, I2C2_GPIO_AF, I2C2_GPIO_SCL | I2C2_GPIO_SDA);
148  break;
149 #endif
150 #if USE_I2C3
151  case I2C3:
153  gpio_mode_setup(I2C3_GPIO_PORT_SCL, GPIO_MODE_AF, GPIO_PUPD_NONE, I2C3_GPIO_SCL);
154  gpio_set_output_options(I2C3_GPIO_PORT_SCL, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ,
155  I2C3_GPIO_SCL);
156  gpio_set_af(I2C3_GPIO_PORT_SCL, I2C3_GPIO_SCL_AF, I2C3_GPIO_SCL);
157 
159  gpio_mode_setup(I2C3_GPIO_PORT_SDA, GPIO_MODE_AF, GPIO_PUPD_NONE, I2C3_GPIO_SDA);
160  gpio_set_output_options(I2C3_GPIO_PORT_SDA, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ,
161  I2C3_GPIO_SDA);
163  break;
164 #endif
165  default:
166  break;
167  }
168 }
169 #endif
170 #endif // USE_I2Cx
171 
172 static inline void PPRZ_I2C_SEND_STOP(uint32_t i2c)
173 {
174  // Man: p722: Stop generation after the current byte transfer or after the current Start condition is sent.
175  i2c_send_stop(i2c);
176 }
177 
178 // (RE)START
179 
180 static inline void PPRZ_I2C_SEND_START(struct i2c_periph *periph)
181 {
182  uint32_t i2c = (uint32_t) periph->reg_addr;
183 
184  // Reset the buffer pointer to the first byte
185  periph->idx_buf = 0;
186  periph->watchdog = 0;
187 
188  // Enable Error IRQ, Event IRQ but disable Buffer IRQ
189  i2c_enable_interrupt(i2c, I2C_CR2_ITERREN);
190  i2c_enable_interrupt(i2c, I2C_CR2_ITEVTEN);
191  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
192 
193  // Issue a new start
194  i2c_nack_current(i2c);
195  i2c_disable_ack(i2c);
196  i2c_clear_stop(i2c);
197  i2c_peripheral_enable(i2c);
198  i2c_send_start(i2c);
199  periph->status = I2CStartRequested;
200 
201 }
202 
203 // STOP
204 
207 //
208 // SUBTRANSACTION SEQUENCES
209 // -We arrive here every time a ISR is called with no error
210 
216 };
217 
218 // Doc ID 13902 Rev 11 p 710/1072
219 // Transfer Sequence Diagram for Master Transmitter
220 static inline enum STMI2CSubTransactionStatus stmi2c_send(uint32_t i2c, struct i2c_periph *periph,
221  struct i2c_transaction *trans)
222 {
223  uint16_t SR1 = I2C_SR1(i2c);
224 
225  // Start Condition Was Just Generated
226  if (BIT_X_IS_SET_IN_REG(I2C_SR1_SB, SR1)) {
227  // Disable buffer interrupt
228  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
229  // Send Slave address and wait for ADDR interrupt
230  i2c_send_data(i2c, trans->slave_addr);
231  // Document the current Status
232  periph->status = I2CAddrWrSent;
233  }
234  // Address Was Sent
235  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1)) {
236  // Now read SR2 to clear the ADDR status Bit
237  uint16_t SR2 __attribute__((unused)) = I2C_SR2(i2c);
238 
239  // Maybe check we are transmitting (did not loose arbitration for instance)
240  // if (! BIT_X_IS_SET_IN_REG(I2C_SR2_TRA, SR2)) { }
241  // update: this should be caught by the ARLO error: so we will not arrive here
242 
243  // Send First max 2 bytes
244  i2c_send_data(i2c, trans->buf[0]);
245  if (trans->len_w > 1) {
246  i2c_send_data(i2c, trans->buf[1]);
247  periph->idx_buf = 2;
248  } else {
249  periph->idx_buf = 1;
250  }
251 
252  // Enable buffer-space available interrupt
253  // only if there is more to send: wait for TXE, no more to send: wait for BTF
254  if (periph->idx_buf < trans->len_w) {
255  i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN);
256  }
257 
258  // Document the current Status
259  periph->status = I2CSendingByte;
260  }
261  // The buffer is not full anymore AND we were not waiting for BTF
262  else if ((BIT_X_IS_SET_IN_REG(I2C_SR1_TxE, SR1)) && (BIT_X_IS_SET_IN_REG(I2C_CR2_ITBUFEN, I2C_CR2(i2c)))) {
263  // Send the next byte
264  i2c_send_data(i2c, trans->buf[periph->idx_buf]);
265  periph->idx_buf++;
266 
267  // All bytes Sent? Then wait for BTF instead
268  if (periph->idx_buf >= trans->len_w) {
269  // Not interested anymore to know the buffer has space left
270  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
271  // Next interrupt will be BTF (or error)
272  }
273  }
274  // BTF: means last byte was sent
275  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1)) {
276  if (trans->type == I2CTransTx) {
277  // Tell the driver we are ready
278  trans->status = I2CTransSuccess;
279  }
280  // Otherwise we still need to do the receiving part
281 
282  return STMI2C_SubTra_Ready;
283  } else { // Event Logic Error
284  return STMI2C_SubTra_Error;
285  }
286 
287  return STMI2C_SubTra_Busy;
288 }
289 
290 // Doc ID 13902 Rev 11 p 714/1072
291 // Transfer Sequence Diagram for Master Receiver for N=1
292 static inline enum STMI2CSubTransactionStatus stmi2c_read1(uint32_t i2c, struct i2c_periph *periph,
293  struct i2c_transaction *trans)
294 {
295  uint16_t SR1 = I2C_SR1(i2c);
296 
297  // Start Condition Was Just Generated
298  if (BIT_X_IS_SET_IN_REG(I2C_SR1_SB, SR1)) {
299  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
300  i2c_send_data(i2c, trans->slave_addr | 0x01);
301 
302  // Document the current Status
303  periph->status = I2CAddrRdSent;
304  }
305  // Address Was Sent
306  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1)) {
307  // First Clear the ACK bit: after the next byte we do not want new bytes
308  i2c_nack_current(i2c);
309  i2c_disable_ack(i2c);
310 
311  // --- next to steps MUST be executed together to avoid missing the stop
313 
314  // Only after setting ACK, read SR2 to clear the ADDR (next byte will start arriving)
315  uint16_t SR2 __attribute__((unused)) = I2C_SR2(i2c);
316 
317  // Schedule a Stop
318  PPRZ_I2C_SEND_STOP(i2c);
319 
321  // --- end of critical zone -----------
322 
323  // Enable the RXNE: it will trigger as soon as the 1 byte is received to get the result
324  i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN);
325 
326  // Document the current Status
327  periph->status = I2CReadingLastByte;
328  }
329  // As soon as there is 1 byte ready to read, we have our byte
330  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_RxNE, SR1)) {
331  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
332  trans->buf[0] = I2C_DR(i2c);
333 
334  // We got all the results (stop condition might still be in progress but this is the last interrupt)
335  trans->status = I2CTransSuccess;
336 
337  // Document the current Status:
338  // -the stop was actually already requested in the previous step
339  periph->status = I2CStopRequested;
340 
342  } else { // Event Logic Error
343  return STMI2C_SubTra_Error;
344  }
345 
346  return STMI2C_SubTra_Busy;
347 }
348 
349 // Doc ID 13902 Rev 11 p 713/1072
350 // Transfer Sequence Diagram for Master Receiver for N=2
351 static inline enum STMI2CSubTransactionStatus stmi2c_read2(uint32_t i2c, struct i2c_periph *periph,
352  struct i2c_transaction *trans)
353 {
354  uint16_t SR1 = I2C_SR1(i2c);
355 
356  // Start Condition Was Just Generated
357  if (BIT_X_IS_SET_IN_REG(I2C_SR1_SB, SR1)) {
358  // according to the datasheet: instantly shedule a NAK on the second received byte:
359  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
360  i2c_enable_ack(i2c);
361  i2c_nack_next(i2c);
362  i2c_send_data(i2c, trans->slave_addr | 0x01);
363 
364  // Document the current Status
365  periph->status = I2CAddrRdSent;
366  }
367  // Address Was Sent
368  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1)) {
369  // --- make absolutely sure this command is not delayed too much after the previous:
370  // --- the NAK bits must be set before the first byte arrived: allow other interrupts here
372 
373  // if transfer of DR was finished already then we will get too many bytes
374  // BEFORE clearing ACK, read SR2 to clear the ADDR (next byte will start arriving)
375  // clearing ACK after the byte transfer has already started will NACK the next (2nd)
376  uint16_t SR2 __attribute__((unused)) = I2C_SR2(i2c);
377 
378  // NOT First Clear the ACK bit but only AFTER clearing ADDR
379  i2c_disable_ack(i2c);
380 
381  // Disable the RXNE and wait for BTF
382  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
383 
385  // --- end of critical zone -----------
386 
387  // We do not set the RxE but wait for both bytes to arrive using BTF
388 
389  // Document the current Status
390  periph->status = I2CReadingByte;
391  }
392  // Receive buffer if full, master is halted: BTF
393  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1)) {
394  // Stop condition MUST be set BEFORE reading the DR
395  // otherwise since there is new buffer space a new byte will be read
396  PPRZ_I2C_SEND_STOP(i2c);
397 
398  // Document the current Status
399  periph->status = I2CStopRequested;
400 
401  trans->buf[0] = I2C_DR(i2c);
402  trans->buf[1] = I2C_DR(i2c);
403 
404  // We got all the results
405  trans->status = I2CTransSuccess;
406 
408  } else { // Event Logic Error
409  return STMI2C_SubTra_Error;
410  }
411 
412  return STMI2C_SubTra_Busy;
413 }
414 
415 // Doc ID 13902 Rev 11 p 712/1072
416 // Transfer Sequence Diagram for Master Receiver for N>2
417 static inline enum STMI2CSubTransactionStatus stmi2c_readmany(uint32_t i2c, struct i2c_periph *periph,
418  struct i2c_transaction *trans)
419 {
420  uint16_t SR1 = I2C_SR1(i2c);
421 
422  // Start Condition Was Just Generated
423  if (BIT_X_IS_SET_IN_REG(I2C_SR1_SB, SR1)) {
424  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
425  // The first data byte will be acked in read many so the slave knows it should send more
426  i2c_nack_current(i2c);
427  i2c_enable_ack(i2c);
428  // Clear the SB flag
429  i2c_send_data(i2c, trans->slave_addr | 0x01);
430 
431  // Document the current Status
432  periph->status = I2CAddrRdSent;
433  }
434  // Address Was Sent
435  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1)) {
436  periph->idx_buf = 0;
437 
438  // Enable RXNE: receive an interrupt any time a byte is available
439  // only enable if MORE than 3 bytes need to be read
440  if (periph->idx_buf < (trans->len_r - 3)) {
441  i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN);
442  }
443 
444  // ACK is still on to get more DATA
445  // Read SR2 to clear the ADDR (next byte will start arriving)
446  uint16_t SR2 __attribute__((unused)) = I2C_SR2(i2c);
447 
448  // Document the current Status
449  periph->status = I2CReadingByte;
450  }
451  // one or more bytes are available AND we were interested in Buffer interrupts
452  else if ((BIT_X_IS_SET_IN_REG(I2C_SR1_RxNE, SR1)) && (BIT_X_IS_SET_IN_REG(I2C_CR2_ITBUFEN, I2C_CR2(i2c)))) {
453  // read byte until 3 bytes remain to be read (e.g. len_r = 6, -> idx=3 means idx 3,4,5 = 3 remain to be read
454  if (periph->idx_buf < (trans->len_r - 3)) {
455  trans->buf[periph->idx_buf] = I2C_DR(i2c);
456  periph->idx_buf ++;
457  }
458  // from : 3bytes -> last byte: do nothing
459  //
460  // finally: this was the last byte
461  else if (periph->idx_buf >= (trans->len_r - 1)) {
462  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
463 
464  // Last Value
465  trans->buf[periph->idx_buf] = i2c_get_data(i2c);
466  periph->idx_buf ++;
467 
468  // We got all the results
469  trans->status = I2CTransSuccess;
470 
472  }
473 
474  // Check for end of transaction: start waiting for BTF instead of RXNE
475  if (periph->idx_buf < (trans->len_r - 3)) {
476  i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN);
477  } else { // idx >= len-3: there are 3 bytes to be read
478  // We want to halt I2C to have sufficient time to clear ACK, so:
479  // Stop listening to RXNE as it will be triggered infinitely since we did not empty the buffer
480  // on the next (second in buffer) received byte BTF will be set (buffer full and I2C halted)
481  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
482  }
483  }
484  // Buffer is full while this was not a RXNE interrupt
485  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1)) {
486  // Now the shift register and data register contain data(n-2) and data(n-1)
487  // And I2C is halted so we have time
488 
489  // --- Make absolutely sure the next 2 I2C actions are performed with no delay
491 
492  // First we clear the ACK while the SCL is held low by BTF
493  i2c_disable_ack(i2c);
494 
495  // Now that ACK is cleared we read one byte: instantly the last byte is being clocked in...
496  trans->buf[periph->idx_buf] = i2c_get_data(i2c);
497  periph->idx_buf ++;
498 
499  // Now the last byte is being clocked. Stop in MUST be set BEFORE the transfer of the last byte is complete
500  PPRZ_I2C_SEND_STOP(i2c);
501 
503 
504 
505  // --- end of critical zone -----------
506 
507  // Document the current Status
508  periph->status = I2CStopRequested;
509 
510  // read the byte2 we had in the buffer (BTF means 2 bytes available)
511  trans->buf[periph->idx_buf] = i2c_get_data(i2c);
512  periph->idx_buf ++;
513 
514  // Ask for an interrupt to read the last byte (which is normally still busy now)
515  // The last byte will be received with RXNE
516  i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN);
517  } else { // Event Logic Error
518  return STMI2C_SubTra_Error;
519  }
520 
521  return STMI2C_SubTra_Busy;
522 }
523 
525 // Restore bus conditions to normal after errors
526 
527 static inline void i2c_error(struct i2c_periph *periph)
528 {
529  periph->errors->er_irq_cnt++;
530  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_AF) != 0) { /* Acknowledge failure */
531  periph->errors->ack_fail_cnt++;
532  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_AF;
533  }
534  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_BERR) != 0) { /* Misplaced Start or Stop condition */
535  periph->errors->miss_start_stop_cnt++;
536  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_BERR;
537  }
538  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_ARLO) != 0) { /* Arbitration lost */
539  periph->errors->arb_lost_cnt++;
540  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_ARLO;
541  }
542  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_OVR) != 0) { /* Overrun/Underrun */
543  periph->errors->over_under_cnt++;
544  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_OVR;
545  }
546  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_PECERR) != 0) { /* PEC Error in reception */
547  periph->errors->pec_recep_cnt++;
548  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_PECERR;
549  }
550  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_TIMEOUT) != 0) { /* Timeout or Tlow error */
551  periph->errors->timeout_tlow_cnt++;
552  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_TIMEOUT;
553  }
554  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_SMBALERT) != 0) { /* SMBus alert */
555  periph->errors->smbus_alert_cnt++;
556  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_SMBALERT;
557  }
558 
559  return;
560 }
561 
562 
564 {
565  uint16_t SR1 = I2C_SR1(i2c);
566 
567  // Certainly do not wait for buffer interrupts:
568  // -------------------------------------------
569  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN); // Disable TXE, RXNE
570 
571  // Error interrupts are handled separately:
572  // ---------------------------------------
573 
574  // Clear Event interrupt conditions:
575  // --------------------------------
576 
577  // Start Condition Was Generated
578  if (BIT_X_IS_SET_IN_REG(I2C_SR1_SB, SR1)) {
579  // SB: cleared by software when reading SR1 and writing to DR
580  i2c_send_data(i2c, 0x00);
581  }
582  // Address Was Sent
583  if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1)) {
584  // ADDR: Cleared by software when reading SR1 and then SR2
585  uint16_t SR2 __attribute__((unused)) = I2C_SR2(i2c);
586  }
587  // Byte Transfer Finished
588  if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1)) {
589  // SB: cleared by software when reading SR1 and reading/writing to DR
590  uint8_t dummy __attribute__((unused)) = i2c_get_data(i2c);
591  i2c_send_data(i2c, 0x00);
592  }
593 
594 }
595 
596 
598 // Restore bus conditions to normal after errors
599 
600 static inline void i2c_irq(struct i2c_periph *periph)
601 {
602 
603  /*
604  There are 7 possible event reasons to get here + all errors
605 
606  If IT_EV_FEN
607  -------------------------
608 
609  We are always interested in all IT_EV_FEV: all are required.
610 
611  1) SB // Start Condition Success in Master mode
612  2) ADDR // Address sent received Acknowledge
613  [ADDR10] // -- 10bit address stuff: not used
614  [STOPF] // -- only for slaves: master has no stop interrupt: not used
615  3) BTF // I2C has stopped working (it is waiting for new data, all buffers are tx_empty/rx_full)
616 
617  // Beware: using the buffered I2C has some interesting properties:
618  - in master receive mode: BTF only occurs after the 2nd received byte: after the first byte is received it is
619  in RD but the I2C can still receive a second byte. Only when the 2nd byte is received while the RxNE is 1
620  then a BTF occurs (I2C can not continue receiving bytes or they will get lost). During BTF I2C is halted (SCL held low)
621  - in master transmit mode: when writing a byte to WD, you instantly get a new TxE interrupt while the first is not
622  transmitted yet. The byte was pushed to the I2C shift register and the buffer is ready for more. You can already
623  fill new data in the buffer while the first is still being transmitted for max performance transmission.
624 
625  // Beware: besides data buffering you can/must plan several consecutive actions. You can send 2 bytes to the buffer, ask for a stop and
626  a new start in one go.
627 
628  - thanks to / because of this buffering and event sheduling there is not 1 interrupt per start / byte / stop
629  This also means you must think more in advance and a transaction could be popped from the transaction stack even before it's
630  stop condition is actually generated.
631 
632  // Beware: the order in which Status (and other register) is read determines how flags are cleared.
633  You should NOT simply read SR1 & SR2 every time
634 
635  If IT_EV_FEN AND IT_EV_BUF
636  --------------------------
637 
638  Buffer event are not always wanted and are typically switched on during longer data transfers. Make sure to turn off in time.
639 
640  4) RxNE
641  5) TxE
642 
643  --------------------------------------------------------------------------------------------------
644 
645  The STM waits indefinitely (holding SCL low) for user interaction:
646  a) after a master-start (waiting for address)
647  b) after an address (waiting for data)
648  not during data sending when using buffered
649  c) after the last byte is transmitted (waiting for either stop or restart)
650  not during data receiving when using buffered
651  not after the last byte is received
652 
653  - The STM I2C stalls indefinitely when a stop condition was attempted that
654  did not succeed. The BUSY flag remains on.
655  - There is no STOP interrupt.
656 
657  Caution Reading the status:
658  - Caution: this clears several flags and can start transmissions etc...
659  - Certain flags like STOP / (N)ACK need to be guaranteed to be set before
660  the transmission of the byte is finished. At higher clock rates that can be
661  quite fast: so we allow no other interrupt to be triggered in between
662  reading the status and setting all needed flags
663 
664  */
665 
666  // Here we go ...
667 
668  // Apparently we got an I2C interrupt: EVT BUF or ERR
669 
670  // Save Some Direct Access to the I2C Registers ...
671  uint32_t i2c = (uint32_t) periph->reg_addr;
672 
674  // Check if we were ready ...
675  if (periph->trans_extract_idx == periph->trans_insert_idx) {
676  // Nothing Left To Do
677 
678  // If we still get an interrupt but there are no more things to do
679  // (which can happen if an event was sheduled just before a bus error occurs)
680  // (or can happen if both error and event interrupts were called together [the 2nd will then get this error])
681 
682  // since there is nothing more to do: its easy: just stop: clear all interrupt generating bits
683 
684  // Count The Errors
685  i2c_error(periph);
686 
687  // Clear Running Events
689 
690  // Mark this as a special error
691  periph->errors->last_unexpected_event++;
692 
693  // Document the current Status
694  periph->status = I2CIdle;
695 
696  // There are no transactions anymore: return
697  // further-on in this routine we need a transaction pointer: so we are not allowed to continue
698  return;
699  }
700 
701  // get the I2C transaction we were working on ...
702 
703  enum STMI2CSubTransactionStatus ret = 0;
704  struct i2c_transaction *trans = periph->trans[periph->trans_extract_idx];
705 
707  // If there was an error:
708  if ((I2C_SR1(i2c) & I2C_SR1_ERR_MASK) != 0x0000) {
709 
710  // Notify everyone about the error ...
711 
712  // Set result in transaction
713  trans->status = I2CTransFailed;
714 
715  // Document the current Status
716  periph->status = I2CFailed;
717 
718  // Make sure a TxRx does not Restart
719  trans->type = I2CTransRx;
720 
721  // Count The Errors
722  i2c_error(periph);
723 
724  // Clear Running Events
726 
727  // Now continue as if everything was normal from now on
728  ret = STMI2C_SubTra_Ready;
729 
730  }
731 
733  // Normal Event:
734  else {
735 
738  //
739  // SUB-TRANSACTION HANDLER
740 
741  if (trans->type == I2CTransRx) { // TxRx are converted to Rx after the Tx Part
742  switch (trans->len_r) {
743  case 1:
744  ret = stmi2c_read1(i2c, periph, trans);
745  break;
746  case 2:
747  ret = stmi2c_read2(i2c, periph, trans);
748  break;
749  default:
750  ret = stmi2c_readmany(i2c, periph, trans);
751  break;
752  }
753  } else { // TxRx or Tx
754  ret = stmi2c_send(i2c, periph, trans);
755  }
756  }
757 
759  // Sub-transaction has finished
760  if (ret != STMI2C_SubTra_Busy) {
761  // Ready or SubTraError
762  // -ready: with or without stop already asked
763 
764  // In case of unexpected event condition during subtransaction handling:
765  if (ret == STMI2C_SubTra_Error) {
766  // Tell everyone about the subtransaction error:
767  // this is the previously called SPURRIOUS INTERRUPT
768  periph->status = I2CFailed;
769  trans->type = I2CTransRx; // Avoid possible restart
770  trans->status = I2CTransFailed; // Notify Ready
771  periph->errors->unexpected_event_cnt++;
772 
773  // Clear Running Events
775  }
776 
777  // RxTx -> Restart and do Rx part
778  if (trans->type == I2CTransTxRx) {
779  trans->type = I2CTransRx;
780  periph->status = I2CStartRequested;
781  i2c_send_start(i2c);
782 
783  // Silent any BTF that would occur before SB
784  i2c_send_data(i2c, 0x00);
785  }
786  // If a restart is not needed: Rx part or Tx-only
787  else {
788  // Ready, no stop condition set yet
789  if (ret == STMI2C_SubTra_Ready) {
790 
791  // Program a stop
792  PPRZ_I2C_SEND_STOP(i2c);
793 
794  // Silent any BTF that would occur before STOP is executed
795  i2c_send_data(i2c, 0x00);
796  }
797 
798  // Jump to the next transaction
799  periph->trans_extract_idx++;
801  periph->trans_extract_idx = 0;
802  }
803 
804  // Tell everyone we are ready
805  periph->status = I2CIdle;
806 
807 
808  // if we have no more transaction to process, stop here
809  if (periph->trans_extract_idx == periph->trans_insert_idx) {
810 
811  periph->watchdog = -1; // stop watchdog
812  }
813  // if not, start next transaction
814  else {
815  // Restart transaction doing the Rx part now
816  // --- moved to idle function
817  PPRZ_I2C_SEND_START(periph);
818  // ------
819  }
820  }
821  }
822 
823  return;
824 }
825 
826 
827 /*
828 // Make sure the bus is free before resetting (p722)
829 if (regs->SR2 & (I2C_FLAG_BUSY >> 16)) {
830 // Reset the I2C block
831 I2C_SoftwareResetCmd(periph->reg_addr, ENABLE);
832 I2C_SoftwareResetCmd(periph->reg_addr, DISABLE);
833 }
834 */
835 
836 
837 #if USE_I2C0
838 #error "The STM32 doesn't have I2C0, use I2C1 or I2C2"
839 #endif
840 
841 #if USE_I2C1
842 
844 #ifndef I2C1_CLOCK_SPEED
845 #define I2C1_CLOCK_SPEED 200000
846 #endif
847 PRINT_CONFIG_VAR(I2C1_CLOCK_SPEED)
848 
849 struct i2c_errors i2c1_errors;
850 
851 void i2c1_hw_init(void)
852 {
853  i2c1.idle = i2c_stm32_idle;
854  i2c1.submit = i2c_stm32_submit;
855  i2c1.setbitrate = i2c_stm32_setbitrate;
856 
857  i2c1.reg_addr = (void *)I2C1;
858  i2c1.init_struct = NULL;
859  i2c1.errors = &i2c1_errors;
860  i2c1.watchdog = -1;
861 
862  /* zeros error counter */
863  ZEROS_ERR_COUNTER(i2c1_errors);
864 
865  /* reset peripheral to default state ( sometimes not achieved on reset :( ) */
866  //rcc_periph_reset_pulse(RST_I2C1);
867 
868  /* Configure and enable I2C1 event interrupt --------------------------------*/
869  nvic_set_priority(NVIC_I2C1_EV_IRQ, NVIC_I2C1_IRQ_PRIO);
870  nvic_enable_irq(NVIC_I2C1_EV_IRQ);
871 
872  /* Configure and enable I2C1 err interrupt ----------------------------------*/
873  nvic_set_priority(NVIC_I2C1_ER_IRQ, NVIC_I2C1_IRQ_PRIO + 1);
874  nvic_enable_irq(NVIC_I2C1_ER_IRQ);
875 
876  /* Enable peripheral clocks -------------------------------------------------*/
877  /* Enable I2C1 clock */
878  rcc_periph_clock_enable(RCC_I2C1);
879  /* setup gpio clock and pins */
880  i2c_setup_gpio(I2C1);
881 
882  rcc_periph_reset_pulse(RST_I2C1);
883 
884  // enable peripheral
885  i2c_peripheral_enable(I2C1);
886 
887  i2c_set_own_7bit_slave_address(I2C1, 0);
888 
889  // enable error interrupts
890  i2c_enable_interrupt(I2C1, I2C_CR2_ITERREN);
891 
893 }
894 
895 void i2c1_ev_isr(void)
896 {
897  uint32_t i2c = (uint32_t) i2c1.reg_addr;
898  i2c_disable_interrupt(i2c, I2C_CR2_ITERREN);
899  i2c1.watchdog = 0; // restart watchdog
900  i2c_irq(&i2c1);
901  i2c_enable_interrupt(i2c, I2C_CR2_ITERREN);
902 }
903 
904 void i2c1_er_isr(void)
905 {
906  uint32_t i2c = (uint32_t) i2c1.reg_addr;
907  i2c_disable_interrupt(i2c, I2C_CR2_ITEVTEN);
908  i2c1.watchdog = 0; // restart watchdog
909  i2c_irq(&i2c1);
910  i2c_enable_interrupt(i2c, I2C_CR2_ITEVTEN);
911 }
912 
913 #endif /* USE_I2C1 */
914 
915 #if USE_I2C2
916 
918 #ifndef I2C2_CLOCK_SPEED
919 #define I2C2_CLOCK_SPEED 300000
920 #endif
921 PRINT_CONFIG_VAR(I2C2_CLOCK_SPEED)
922 
923 struct i2c_errors i2c2_errors;
924 
925 void i2c2_hw_init(void)
926 {
927  i2c2.idle = i2c_stm32_idle;
928  i2c2.submit = i2c_stm32_submit;
929  i2c2.setbitrate = i2c_stm32_setbitrate;
930 
931  i2c2.reg_addr = (void *)I2C2;
932  i2c2.init_struct = NULL;
933  i2c2.errors = &i2c2_errors;
934  i2c2.watchdog = -1;
935 
936  /* zeros error counter */
937  ZEROS_ERR_COUNTER(i2c2_errors);
938 
939  /* reset peripheral to default state ( sometimes not achieved on reset :( ) */
940  //rcc_periph_reset_pulse(RST_I2C2);
941 
942  /* Configure and enable I2C2 event interrupt --------------------------------*/
943  nvic_set_priority(NVIC_I2C2_EV_IRQ, NVIC_I2C2_IRQ_PRIO);
944  nvic_enable_irq(NVIC_I2C2_EV_IRQ);
945 
946  /* Configure and enable I2C2 err interrupt ----------------------------------*/
947  nvic_set_priority(NVIC_I2C2_ER_IRQ, NVIC_I2C2_IRQ_PRIO + 1);
948  nvic_enable_irq(NVIC_I2C2_ER_IRQ);
949 
950  /* Enable peripheral clocks -------------------------------------------------*/
951  /* Enable I2C2 clock */
952  rcc_periph_clock_enable(RCC_I2C2);
953 
954  /* setup gpio clock and pins */
955  i2c_setup_gpio(I2C2);
956 
957  rcc_periph_reset_pulse(RST_I2C2);
958 
959  // enable peripheral
960  i2c_peripheral_enable(I2C2);
961 
962  i2c_set_own_7bit_slave_address(I2C2, 0);
963 
964  // enable error interrupts
965  i2c_enable_interrupt(I2C2, I2C_CR2_ITERREN);
966 
968 }
969 
970 void i2c2_ev_isr(void)
971 {
972  uint32_t i2c = (uint32_t) i2c2.reg_addr;
973  i2c_disable_interrupt(i2c, I2C_CR2_ITERREN);
974  i2c2.watchdog = 0; // restart watchdog
975  i2c_irq(&i2c2);
976  i2c_enable_interrupt(i2c, I2C_CR2_ITERREN);
977 }
978 
979 void i2c2_er_isr(void)
980 {
981  uint32_t i2c = (uint32_t) i2c2.reg_addr;
982  i2c_disable_interrupt(i2c, I2C_CR2_ITEVTEN);
983  i2c2.watchdog = 0; // restart watchdog
984  i2c_irq(&i2c2);
985  i2c_enable_interrupt(i2c, I2C_CR2_ITEVTEN);
986 }
987 
988 #endif /* USE_I2C2 */
989 
990 
991 #if USE_I2C3 && defined STM32F4
992 
994 #ifndef I2C3_CLOCK_SPEED
995 #define I2C3_CLOCK_SPEED 300000
996 #endif
997 PRINT_CONFIG_VAR(I2C3_CLOCK_SPEED)
998 
999 struct i2c_errors i2c3_errors;
1000 
1001 void i2c3_hw_init(void)
1002 {
1003  i2c3.idle = i2c_stm32_idle;
1004  i2c3.submit = i2c_stm32_submit;
1005  i2c3.setbitrate = i2c_stm32_setbitrate;
1006 
1007  i2c3.reg_addr = (void *)I2C3;
1008  i2c3.init_struct = NULL;
1009  i2c3.errors = &i2c3_errors;
1010  i2c3.watchdog = -1;
1011 
1012  /* zeros error counter */
1013  ZEROS_ERR_COUNTER(i2c3_errors);
1014 
1015  /* reset peripheral to default state ( sometimes not achieved on reset :( ) */
1016  //rcc_periph_reset_pulse(RST_I2C3);
1017 
1018  /* Configure and enable I2C3 event interrupt --------------------------------*/
1019  nvic_set_priority(NVIC_I2C3_EV_IRQ, NVIC_I2C3_IRQ_PRIO);
1020  nvic_enable_irq(NVIC_I2C3_EV_IRQ);
1021 
1022  /* Configure and enable I2C3 err interrupt ----------------------------------*/
1023  nvic_set_priority(NVIC_I2C3_ER_IRQ, NVIC_I2C3_IRQ_PRIO + 1);
1024  nvic_enable_irq(NVIC_I2C3_ER_IRQ);
1025 
1026  /* Enable peripheral clocks -------------------------------------------------*/
1027  /* Enable I2C3 clock */
1028  rcc_periph_clock_enable(RCC_I2C3);
1029 
1030  /* setup gpio clock and pins */
1031  i2c_setup_gpio(I2C3);
1032 
1033  rcc_periph_reset_pulse(RST_I2C3);
1034 
1035  // enable peripheral
1036  i2c_peripheral_enable(I2C3);
1037 
1038  i2c_set_own_7bit_slave_address(I2C3, 0);
1039 
1040  // enable error interrupts
1041  i2c_enable_interrupt(I2C3, I2C_CR2_ITERREN);
1042 
1044 }
1045 
1046 void i2c3_ev_isr(void)
1047 {
1048  uint32_t i2c = (uint32_t) i2c3.reg_addr;
1049  i2c_disable_interrupt(i2c, I2C_CR2_ITERREN);
1050  i2c3.watchdog = 0; // restart watchdog
1051  i2c_irq(&i2c3);
1052  i2c_enable_interrupt(i2c, I2C_CR2_ITERREN);
1053 }
1054 
1055 void i2c3_er_isr(void)
1056 {
1057  uint32_t i2c = (uint32_t) i2c3.reg_addr;
1058  i2c_disable_interrupt(i2c, I2C_CR2_ITEVTEN);
1059  i2c3.watchdog = 0; // restart watchdog
1060  i2c_irq(&i2c3);
1061  i2c_enable_interrupt(i2c, I2C_CR2_ITEVTEN);
1062 }
1063 
1064 #endif /* USE_I2C3 */
1065 
1067 // Set Bitrate to Match your application:
1068 // -short wires, low capacitance bus: IMU: high speed
1069 // -long wires with a lot of capacitance: motor controller: put speed as low as possible
1070 
1071 static void i2c_stm32_setbitrate(struct i2c_periph *periph, int bitrate)
1072 {
1073  // If NOT Busy
1074  if (i2c_idle(periph)) {
1075  volatile int devider;
1076  volatile int risetime;
1077 
1078  uint32_t i2c = (uint32_t) periph->reg_addr;
1079 
1080  /*****************************************************
1081  Bitrate:
1082 
1083  -CR2 + CCR + TRISE registers
1084  -only change when PE=0
1085 
1086  e.g.
1087 
1088  10kHz: 36MHz + Standard 0x708 + 0x25
1089  70kHz: 36MHz + Standard 0x101 +
1090  400kHz: 36MHz + Fast 0x1E + 0xb
1091 
1092  // 1) Program peripheral input clock CR2: to get correct timings
1093  // 2) Configure clock control registers
1094  // 3) Configure rise time register
1095  ******************************************************/
1096 
1097  if (bitrate < 3000) {
1098  bitrate = 3000;
1099  }
1100 
1101  // rcc_apb1_frequency is normally configured to max: 36MHz on F1 and 42MHz on F4
1102  // in fast mode: 2counts low 1 count high -> / 3:
1103  // in standard mode: 1 count low, 1 count high -> /2:
1104  devider = (rcc_apb1_frequency / 2000) / (bitrate / 1000);
1105 
1106  // never allow faster than 600kbps
1107  if (devider < 20) {
1108  devider = 20;
1109  }
1110 
1111  // no overflow either
1112  if (devider >= 4095) {
1113  devider = 4095;
1114  }
1115 
1116  // risetime can be up to 1/6th of the period
1117  risetime = 1000000 / (bitrate / 1000) / 6 / 28;
1118 
1119  if (risetime < 10) {
1120  risetime = 10;
1121  }
1122 
1123  // more will overflow the register: for more you should lower the FREQ
1124  if (risetime >= 31) {
1125  risetime = 31;
1126  }
1127 
1128  // we do not expect an interrupt as the interface should have been idle, but just in case...
1129  __disable_irq(); // this code is in user space:
1130 
1131  // CCR can only be written when PE is disabled
1132  // p731 note 5
1133  i2c_peripheral_disable(i2c);
1134 
1135  // 1)
1136 #ifdef STM32F1
1137  i2c_set_clock_frequency(i2c, I2C_CR2_FREQ_36MHZ);
1138 #else // STM32F4
1139  i2c_set_clock_frequency(i2c, I2C_CR2_FREQ_42MHZ);
1140 #endif
1141  // 2)
1142  //i2c_set_fast_mode(i2c);
1143  i2c_set_ccr(i2c, devider);
1144  // 3)
1145  i2c_set_trise(i2c, risetime);
1146 
1147  // Re-Enable
1148  i2c_peripheral_enable(i2c);
1149 
1150  __enable_irq();
1151 
1152  }
1153 }
1154 
1155 #define WD_DELAY 20 // number of ticks with 2ms - 40ms delay before resetting the bus
1156 #define WD_RECOVERY_TICKS 18 // number of generated SCL clocking pulses
1157 
1158 #if USE_I2C1 || USE_I2C2 || USE_I2C3
1159 static inline void i2c_scl_set(uint32_t i2c)
1160 {
1161 #if USE_I2C1
1162  if (i2c == I2C1) {
1164  }
1165 #endif
1166 #if USE_I2C2
1167  if (i2c == I2C2) {
1169  }
1170 #endif
1171 #if USE_I2C3
1172  if (i2c == I2C3) {
1174  }
1175 #endif
1176 }
1177 
1178 static inline void i2c_scl_toggle(uint32_t i2c)
1179 {
1180 #if USE_I2C1
1181  if (i2c == I2C1) {
1183  }
1184 #endif
1185 #if USE_I2C2
1186  if (i2c == I2C2) {
1188  }
1189 #endif
1190 #if USE_I2C3
1191  if (i2c == I2C3) {
1193  }
1194 #endif
1195 }
1196 
1197 static inline bool i2c_sda_get(uint32_t i2c)
1198 {
1199  bool res = false;
1200 #if USE_I2C1
1201  if (i2c == I2C1) {
1203  }
1204 #endif
1205 #if USE_I2C2
1206  if (i2c == I2C2) {
1208  }
1209 #endif
1210 #if USE_I2C3
1211  if (i2c == I2C3) {
1213  }
1214 #endif
1215  return res;
1216 }
1217 
1218 static void i2c_wd_check(struct i2c_periph *periph)
1219 {
1220  uint32_t i2c = (uint32_t) periph->reg_addr;
1221 
1222  if (periph->watchdog > WD_DELAY) {
1223  if (periph->watchdog == WD_DELAY + 1) {
1224 
1225  i2c_disable_interrupt(i2c, I2C_CR2_ITEVTEN);
1226  i2c_disable_interrupt(i2c, I2C_CR2_ITERREN);
1227 
1228  periph->trans_insert_idx = 0;
1229  periph->trans_extract_idx = 0;
1230  periph->status = I2CIdle;
1231  struct i2c_transaction *trans;
1232  for (uint8_t i = 0; i < I2C_TRANSACTION_QUEUE_LEN; i++) {
1233  trans = periph->trans[i];
1234  trans->status = I2CTransFailed;
1235  }
1236 
1237  i2c_peripheral_disable(i2c);
1238 
1239 #if USE_I2C1
1240  if (i2c == I2C1) {
1243  }
1244 #endif
1245 #if USE_I2C2
1246  if (i2c == I2C2) {
1249  }
1250 #endif
1251 #if USE_I2C3
1252  if (i2c == I2C3) {
1255  }
1256 #endif
1257 
1258  i2c_scl_set(i2c);
1259  } else if (periph->watchdog < WD_DELAY + WD_RECOVERY_TICKS) {
1260  if (i2c_sda_get(i2c)) {
1261  periph->watchdog = WD_DELAY + WD_RECOVERY_TICKS;
1262  }
1263  i2c_scl_toggle(i2c);
1264  } else {
1265  i2c_scl_set(i2c);
1266 
1267  /* setup gpios for normal i2c operation again */
1268  i2c_setup_gpio(i2c);
1269 
1270  i2c_reset(i2c);
1271 
1272  i2c_peripheral_enable(i2c);
1273  i2c_set_own_7bit_slave_address(i2c, 0);
1274  i2c_enable_interrupt(i2c, I2C_CR2_ITERREN);
1275 
1276 #if USE_I2C1
1277  if (i2c == I2C1) {
1279  }
1280 #endif
1281 #if USE_I2C2
1282  if (i2c == I2C2) {
1284  }
1285 #endif
1286 #if USE_I2C3
1287  if (i2c == I2C3) {
1289  }
1290 #endif
1291 
1292  periph->watchdog = 0; // restart watchdog
1293 
1294  periph->errors->wd_reset_cnt++;
1295 
1296  return;
1297  }
1298  }
1299  if (periph->watchdog >= 0) {
1300  periph->watchdog++;
1301  }
1302 }
1303 #endif // USE_I2Cx
1304 
1305 #include "mcu_periph/sys_time.h"
1306 
1307 void i2c_event(void)
1308 {
1309  static uint32_t i2c_wd_timer;
1310 
1311  if (SysTimeTimer(i2c_wd_timer) > 2000) { // 2ms (500Hz) periodic watchdog check
1312  SysTimeTimerStart(i2c_wd_timer);
1313 #if USE_I2C1
1314  i2c_wd_check(&i2c1);
1315 #endif
1316 
1317 #if USE_I2C2
1318  i2c_wd_check(&i2c2);
1319 #endif
1320 #if USE_I2C3
1321  i2c_wd_check(&i2c3);
1322 #endif
1323  }
1324 }
1325 
1327 // Implement Interface Functions
1328 
1329 static bool i2c_stm32_submit(struct i2c_periph *periph, struct i2c_transaction *t)
1330 {
1331  if (periph->watchdog > WD_DELAY) {
1332  return false;
1333  }
1334 
1335  uint8_t temp;
1336  temp = periph->trans_insert_idx + 1;
1337  if (temp >= I2C_TRANSACTION_QUEUE_LEN) { temp = 0; }
1338  if (temp == periph->trans_extract_idx) {
1339  // queue full
1340  periph->errors->queue_full_cnt++;
1341  t->status = I2CTransFailed;
1342  return false;
1343  }
1344 
1345  t->status = I2CTransPending;
1346 
1347  __disable_irq();
1348  /* put transacation in queue */
1349  periph->trans[periph->trans_insert_idx] = t;
1350  periph->trans_insert_idx = temp;
1351 
1352  /* if peripheral is idle, start the transaction */
1353  // if (PPRZ_I2C_IS_IDLE(p))
1354  if (periph->status == I2CIdle) {
1355  //if (i2c_idle(periph))
1356  {
1357  PPRZ_I2C_SEND_START(periph);
1358  }
1359  }
1360  /* else it will be started by the interrupt handler when the previous transactions completes */
1361  __enable_irq();
1362 
1363  return true;
1364 }
1365 
1366 static bool i2c_stm32_idle(struct i2c_periph *periph)
1367 {
1368  // This is actually a difficult function:
1369  // -simply reading the status flags can clear bits and corrupt the transaction
1370 
1371  uint32_t i2c = (uint32_t) periph->reg_addr;
1372 
1373  // First we check if the software thinks it is ready
1374  if (periph->status == I2CIdle) {
1375  return !(BIT_X_IS_SET_IN_REG(I2C_SR2_BUSY, I2C_SR2(i2c)));
1376  } else {
1377  return false;
1378  }
1379 }
1380 
unsigned short uint16_t
Definition: types.h:16
volatile uint16_t arb_lost_cnt
Definition: i2c.h:170
volatile uint8_t idx_buf
Definition: i2c.h:156
#define I2C_TRANSACTION_QUEUE_LEN
I2C transaction queue length.
Definition: i2c.h:133
I2C errors counter.
Definition: i2c.h:165
#define I2C3_GPIO_SCL
Definition: krooz_sd.h:134
#define I2C3_GPIO_PORT_SCL
Definition: krooz_sd.h:132
#define I2C3_CLOCK_SPEED
Definition: crazyflie.h:238
#define I2C1
Definition: LPC21xx.h:166
volatile uint16_t miss_start_stop_cnt
Definition: i2c.h:169
volatile uint8_t buf[I2C_BUF_LEN]
Transaction buffer With I2C_BUF_LEN number of bytes.
Definition: i2c.h:122
uint16_t len_r
Number of bytes to read/receive.
Definition: i2c.h:110
static void __enable_irq(void)
Definition: i2c_arch.c:67
transaction successfully finished by I2C driver
Definition: i2c.h:57
static bool i2c_idle(struct i2c_periph *p)
Check if I2C bus is idle.
Definition: i2c.h:256
static void i2c_irq(struct i2c_periph *periph)
Definition: i2c_arch.c:600
#define I2C2_GPIO_PORT
Definition: apogee_1.0.h:214
#define I2C3_GPIO_SDA
Definition: krooz_sd.h:135
Some architecture independent helper functions for GPIOs.
transmit and receive transaction
Definition: i2c.h:49
uint8_t trans_extract_idx
Definition: i2c.h:153
#define WD_DELAY
Definition: i2c_arch.c:1155
static void __disable_irq(void)
Definition: i2c_arch.c:66
Definition: i2c.h:66
volatile uint16_t queue_full_cnt
Definition: i2c.h:167
#define GPIOB
Definition: gpio_arch.h:37
#define BIT_X_IS_SET_IN_REG(X, REG)
Definition: i2c_arch.c:62
struct i2c_errors * errors
Definition: i2c.h:159
#define __I2C_REG_CRITICAL_ZONE_STOP
Definition: i2c_arch.c:72
enum I2CStatus status
Definition: i2c.h:155
static enum STMI2CSubTransactionStatus stmi2c_readmany(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
Definition: i2c_arch.c:417
void gpio_setup_output(ioportid_t port, uint16_t gpios)
Setup one or more pins of the given GPIO port as outputs.
Definition: gpio_arch.c:33
volatile uint32_t er_irq_cnt
Definition: i2c.h:177
static void gpio_toggle(ioportid_t port, uint16_t pin)
Toggle a gpio output to low level.
Definition: gpio_arch.h:118
#define I2C3_GPIO_PORT_SDA
Definition: krooz_sd.h:133
void * reg_addr
Definition: i2c.h:157
#define I2C1_GPIO_SDA
Definition: apogee_1.0.h:212
void gpio_enable_clock(uint32_t port)
Enable the relevant clock.
Definition: gpio_arch.c:34
#define __I2C_REG_CRITICAL_ZONE_START
Definition: i2c_arch.c:71
#define I2C_SR1_ERR_MASK
Definition: i2c_arch.c:52
uint8_t len_w
Number of bytes to write/transmit.
Definition: i2c.h:116
#define NVIC_I2C1_IRQ_PRIO
Definition: i2c_arch.c:76
#define ZEROS_ERR_COUNTER(_i2c_err)
Definition: i2c.h:181
static enum STMI2CSubTransactionStatus stmi2c_read2(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
Definition: i2c_arch.c:351
Architecture independent timing functions.
static void i2c_error(struct i2c_periph *periph)
Definition: i2c_arch.c:527
static bool i2c_stm32_idle(struct i2c_periph *periph)
Definition: i2c_arch.c:1366
unsigned long uint32_t
Definition: types.h:18
struct i2c_transaction * trans[I2C_TRANSACTION_QUEUE_LEN]
Definition: i2c.h:151
static void i2c_stm32_setbitrate(struct i2c_periph *periph, int bitrate)
Definition: i2c_arch.c:1071
volatile uint16_t over_under_cnt
Definition: i2c.h:171
transaction failed
Definition: i2c.h:58
Definition: i2c.h:77
static enum STMI2CSubTransactionStatus stmi2c_read1(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
Definition: i2c_arch.c:292
I2C transaction structure.
Definition: i2c.h:93
enum I2CTransactionStatus status
Transaction status.
Definition: i2c.h:126
#define SysTimeTimer(_t)
Definition: sys_time.h:219
#define NVIC_I2C2_IRQ_PRIO
Definition: i2c_arch.c:77
volatile uint16_t unexpected_event_cnt
Definition: i2c.h:175
uint8_t slave_addr
Slave address.
Definition: i2c.h:104
static uint8_t gpio_get(ioportid_t port, uint16_t pin)
Get level of a gpio.
Definition: gpio_arch.h:88
unsigned char uint8_t
Definition: types.h:14
STMI2CSubTransactionStatus
Definition: i2c_arch.c:211
#define NVIC_I2C3_IRQ_PRIO
Definition: i2c_arch.c:78
static bool i2c_stm32_submit(struct i2c_periph *periph, struct i2c_transaction *t)
Definition: i2c_arch.c:1329
transmit only transaction
Definition: i2c.h:47
volatile int16_t watchdog
Definition: i2c.h:160
volatile uint32_t last_unexpected_event
Definition: i2c.h:176
static void i2c_setbitrate(struct i2c_periph *p, int bitrate)
Set I2C bitrate.
Definition: i2c.h:274
#define I2C2_GPIO_SCL
Definition: apogee_1.0.h:215
static enum STMI2CSubTransactionStatus stmi2c_send(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
Definition: i2c_arch.c:220
volatile uint16_t wd_reset_cnt
Definition: i2c.h:166
volatile uint16_t smbus_alert_cnt
Definition: i2c.h:174
#define WD_RECOVERY_TICKS
Definition: i2c_arch.c:1156
#define I2C2_GPIO_SDA
Definition: apogee_1.0.h:216
void i2c_event(void)
i2c_event() function
Definition: i2c_arch.c:428
enum I2CTransactionType type
Transaction type.
Definition: i2c.h:98
#define I2C1_CLOCK_SPEED
I2C defines.
Definition: board.h:479
#define SysTimeTimerStart(_t)
Definition: sys_time.h:218
uint8_t trans_insert_idx
Definition: i2c.h:152
volatile uint16_t pec_recep_cnt
Definition: i2c.h:172
#define I2C1_GPIO_SCL
Definition: apogee_1.0.h:211
void gpio_setup_input(ioportid_t port, uint16_t gpios)
Setup one or more pins of the given GPIO port as inputs.
Definition: gpio_arch.c:40
static void PPRZ_I2C_SEND_START(struct i2c_periph *periph)
Definition: i2c_arch.c:180
receive only transaction
Definition: i2c.h:48
#define I2C2_CLOCK_SPEED
Definition: board.h:495
static void gpio_set(ioportid_t port, uint16_t pin)
Set a gpio output to high level.
Definition: gpio_arch.h:98
transaction is pending in queue
Definition: i2c.h:55
static void stmi2c_clear_pending_interrupts(uint32_t i2c)
Definition: i2c_arch.c:563
#define I2C1_GPIO_PORT
Definition: apogee_1.0.h:210
#define I2C3_GPIO_SDA_AF
static void PPRZ_I2C_SEND_STOP(uint32_t i2c)
Definition: i2c_arch.c:172
volatile uint16_t ack_fail_cnt
Definition: i2c.h:168
volatile uint16_t timeout_tlow_cnt
Definition: i2c.h:173
Architecture independent I2C (Inter-Integrated Circuit Bus) API.