Paparazzi UAS  v5.15_devel-47-g0391b4d
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i2c_arch.c
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22 
29 #include "mcu_periph/i2c.h"
30 
31 #include BOARD_CONFIG
32 
33 #include <libopencm3/stm32/rcc.h>
34 #include <libopencm3/stm32/gpio.h>
35 #include <libopencm3/cm3/nvic.h>
36 #include <libopencm3/cm3/scb.h>
37 
38 #include "mcu_periph/gpio.h"
39 
40 
43 
44 
45 // Error bit mask
46 // XXX: consider moving this define into libopencm3
47 #define I2C_SR1_ERR_MASK (I2C_SR1_SMBALERT | \
48  I2C_SR1_TIMEOUT | \
49  I2C_SR1_PECERR | \
50  I2C_SR1_OVR | \
51  I2C_SR1_AF | \
52  I2C_SR1_ARLO | \
53  I2C_SR1_BERR)
54 
55 // Bit Control
56 
57 #define BIT_X_IS_SET_IN_REG(X,REG) (((REG) & (X)) == (X))
58 
59 // disable and enable irq functions are not implemented in libopencm3 defining them here
60 // XXX: consider moving this definitions into libopencm3
61 static inline void __disable_irq(void) { asm volatile("cpsid i"); }
62 static inline void __enable_irq(void) { asm volatile("cpsie i"); }
63 
64 // Critical Zones
65 
66 #define __I2C_REG_CRITICAL_ZONE_START __disable_irq();
67 #define __I2C_REG_CRITICAL_ZONE_STOP __enable_irq();
68 
69 
70 #ifndef NVIC_I2C_IRQ_PRIO
71 #define NVIC_I2C1_IRQ_PRIO 0
72 #define NVIC_I2C2_IRQ_PRIO 0
73 #define NVIC_I2C3_IRQ_PRIO 0
74 #else
75 #define NVIC_I2C1_IRQ_PRIO NVIC_I2C_IRQ_PRIO
76 #define NVIC_I2C2_IRQ_PRIO NVIC_I2C_IRQ_PRIO
77 #define NVIC_I2C3_IRQ_PRIO NVIC_I2C_IRQ_PRIO
78 #endif
79 
80 #if USE_I2C1 || USE_I2C2 || USE_I2C3
81 #if defined(STM32F1)
82 static void i2c_setup_gpio(uint32_t i2c)
83 {
84  switch (i2c) {
85 #if USE_I2C1
86  case I2C1:
88  gpio_set_mode(I2C1_GPIO_PORT, GPIO_MODE_OUTPUT_2_MHZ,
89  GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN,
91  break;
92 #endif
93 #if USE_I2C2
94  case I2C2:
96  gpio_set_mode(I2C2_GPIO_PORT, GPIO_MODE_OUTPUT_2_MHZ,
97  GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN,
99  break;
100 #endif
101  default:
102  break;
103  }
104 }
105 
106 #elif defined(STM32F4)
107 #ifndef I2C1_GPIO_AF
108 #define I2C1_GPIO_AF GPIO_AF4
109 #endif
110 
111 #ifndef I2C2_GPIO_AF
112 #define I2C2_GPIO_AF GPIO_AF4
113 #endif
114 
115 #ifndef I2C3_GPIO_SCL_AF
116 #define I2C3_GPIO_SCL_AF GPIO_AF4
117 #endif
118 #ifndef I2C3_GPIO_SDA_AF
119 #define I2C3_GPIO_SDA_AF GPIO_AF4
120 #endif
121 
122 static void i2c_setup_gpio(uint32_t i2c)
123 {
124  switch (i2c) {
125 #if USE_I2C1
126  case I2C1:
128  gpio_mode_setup(I2C1_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE,
130  gpio_set_output_options(GPIOB, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ,
132  gpio_set_af(I2C1_GPIO_PORT, I2C1_GPIO_AF, I2C1_GPIO_SCL | I2C1_GPIO_SDA);
133  break;
134 #endif
135 #if USE_I2C2
136  case I2C2:
138  gpio_mode_setup(I2C2_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE,
140  gpio_set_output_options(I2C2_GPIO_PORT, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ,
142  gpio_set_af(I2C2_GPIO_PORT, I2C2_GPIO_AF, I2C2_GPIO_SCL | I2C2_GPIO_SDA);
143  break;
144 #endif
145 #if USE_I2C3
146  case I2C3:
148  gpio_mode_setup(I2C3_GPIO_PORT_SCL, GPIO_MODE_AF, GPIO_PUPD_NONE, I2C3_GPIO_SCL);
149  gpio_set_output_options(I2C3_GPIO_PORT_SCL, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ,
150  I2C3_GPIO_SCL);
151  gpio_set_af(I2C3_GPIO_PORT_SCL, I2C3_GPIO_SCL_AF, I2C3_GPIO_SCL);
152 
154  gpio_mode_setup(I2C3_GPIO_PORT_SDA, GPIO_MODE_AF, GPIO_PUPD_NONE, I2C3_GPIO_SDA);
155  gpio_set_output_options(I2C3_GPIO_PORT_SDA, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ,
156  I2C3_GPIO_SDA);
158  break;
159 #endif
160  default:
161  break;
162  }
163 }
164 #endif
165 #endif // USE_I2Cx
166 
167 static inline void PPRZ_I2C_SEND_STOP(uint32_t i2c)
168 {
169  // Man: p722: Stop generation after the current byte transfer or after the current Start condition is sent.
170  i2c_send_stop(i2c);
171 }
172 
173 // (RE)START
174 
175 static inline void PPRZ_I2C_SEND_START(struct i2c_periph *periph)
176 {
177  uint32_t i2c = (uint32_t) periph->reg_addr;
178 
179  // Reset the buffer pointer to the first byte
180  periph->idx_buf = 0;
181  periph->watchdog = 0;
182 
183  // Enable Error IRQ, Event IRQ but disable Buffer IRQ
184  i2c_enable_interrupt(i2c, I2C_CR2_ITERREN);
185  i2c_enable_interrupt(i2c, I2C_CR2_ITEVTEN);
186  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
187 
188  // Issue a new start
189  i2c_nack_current(i2c);
190  i2c_disable_ack(i2c);
191  i2c_clear_stop(i2c);
192  i2c_peripheral_enable(i2c);
193  i2c_send_start(i2c);
194  periph->status = I2CStartRequested;
195 
196 }
197 
198 // STOP
199 
202 //
203 // SUBTRANSACTION SEQUENCES
204 // -We arrive here every time a ISR is called with no error
205 
211 };
212 
213 // Doc ID 13902 Rev 11 p 710/1072
214 // Transfer Sequence Diagram for Master Transmitter
215 static inline enum STMI2CSubTransactionStatus stmi2c_send(uint32_t i2c, struct i2c_periph *periph,
216  struct i2c_transaction *trans)
217 {
218  uint16_t SR1 = I2C_SR1(i2c);
219 
220  // Start Condition Was Just Generated
221  if (BIT_X_IS_SET_IN_REG(I2C_SR1_SB, SR1)) {
222  // Disable buffer interrupt
223  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
224  // Send Slave address and wait for ADDR interrupt
225  i2c_send_data(i2c, trans->slave_addr);
226  // Document the current Status
227  periph->status = I2CAddrWrSent;
228  }
229  // Address Was Sent
230  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1)) {
231  // Now read SR2 to clear the ADDR status Bit
232  uint16_t SR2 __attribute__((unused)) = I2C_SR2(i2c);
233 
234  // Maybe check we are transmitting (did not loose arbitration for instance)
235  // if (! BIT_X_IS_SET_IN_REG(I2C_SR2_TRA, SR2)) { }
236  // update: this should be caught by the ARLO error: so we will not arrive here
237 
238  // Send First max 2 bytes
239  i2c_send_data(i2c, trans->buf[0]);
240  if (trans->len_w > 1) {
241  i2c_send_data(i2c, trans->buf[1]);
242  periph->idx_buf = 2;
243  } else {
244  periph->idx_buf = 1;
245  }
246 
247  // Enable buffer-space available interrupt
248  // only if there is more to send: wait for TXE, no more to send: wait for BTF
249  if (periph->idx_buf < trans->len_w) {
250  i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN);
251  }
252 
253  // Document the current Status
254  periph->status = I2CSendingByte;
255  }
256  // The buffer is not full anymore AND we were not waiting for BTF
257  else if ((BIT_X_IS_SET_IN_REG(I2C_SR1_TxE, SR1)) && (BIT_X_IS_SET_IN_REG(I2C_CR2_ITBUFEN, I2C_CR2(i2c)))) {
258  // Send the next byte
259  i2c_send_data(i2c, trans->buf[periph->idx_buf]);
260  periph->idx_buf++;
261 
262  // All bytes Sent? Then wait for BTF instead
263  if (periph->idx_buf >= trans->len_w) {
264  // Not interested anymore to know the buffer has space left
265  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
266  // Next interrupt will be BTF (or error)
267  }
268  }
269  // BTF: means last byte was sent
270  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1)) {
271  if (trans->type == I2CTransTx) {
272  // Tell the driver we are ready
273  trans->status = I2CTransSuccess;
274  }
275  // Otherwise we still need to do the receiving part
276 
277  return STMI2C_SubTra_Ready;
278  } else { // Event Logic Error
279  return STMI2C_SubTra_Error;
280  }
281 
282  return STMI2C_SubTra_Busy;
283 }
284 
285 // Doc ID 13902 Rev 11 p 714/1072
286 // Transfer Sequence Diagram for Master Receiver for N=1
287 static inline enum STMI2CSubTransactionStatus stmi2c_read1(uint32_t i2c, struct i2c_periph *periph,
288  struct i2c_transaction *trans)
289 {
290  uint16_t SR1 = I2C_SR1(i2c);
291 
292  // Start Condition Was Just Generated
293  if (BIT_X_IS_SET_IN_REG(I2C_SR1_SB, SR1)) {
294  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
295  i2c_send_data(i2c, trans->slave_addr | 0x01);
296 
297  // Document the current Status
298  periph->status = I2CAddrRdSent;
299  }
300  // Address Was Sent
301  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1)) {
302  // First Clear the ACK bit: after the next byte we do not want new bytes
303  i2c_nack_current(i2c);
304  i2c_disable_ack(i2c);
305 
306  // --- next to steps MUST be executed together to avoid missing the stop
308 
309  // Only after setting ACK, read SR2 to clear the ADDR (next byte will start arriving)
310  uint16_t SR2 __attribute__((unused)) = I2C_SR2(i2c);
311 
312  // Schedule a Stop
313  PPRZ_I2C_SEND_STOP(i2c);
314 
316  // --- end of critical zone -----------
317 
318  // Enable the RXNE: it will trigger as soon as the 1 byte is received to get the result
319  i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN);
320 
321  // Document the current Status
322  periph->status = I2CReadingLastByte;
323  }
324  // As soon as there is 1 byte ready to read, we have our byte
325  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_RxNE, SR1)) {
326  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
327  trans->buf[0] = I2C_DR(i2c);
328 
329  // We got all the results (stop condition might still be in progress but this is the last interrupt)
330  trans->status = I2CTransSuccess;
331 
332  // Document the current Status:
333  // -the stop was actually already requested in the previous step
334  periph->status = I2CStopRequested;
335 
337  } else { // Event Logic Error
338  return STMI2C_SubTra_Error;
339  }
340 
341  return STMI2C_SubTra_Busy;
342 }
343 
344 // Doc ID 13902 Rev 11 p 713/1072
345 // Transfer Sequence Diagram for Master Receiver for N=2
346 static inline enum STMI2CSubTransactionStatus stmi2c_read2(uint32_t i2c, struct i2c_periph *periph,
347  struct i2c_transaction *trans)
348 {
349  uint16_t SR1 = I2C_SR1(i2c);
350 
351  // Start Condition Was Just Generated
352  if (BIT_X_IS_SET_IN_REG(I2C_SR1_SB, SR1)) {
353  // according to the datasheet: instantly shedule a NAK on the second received byte:
354  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
355  i2c_enable_ack(i2c);
356  i2c_nack_next(i2c);
357  i2c_send_data(i2c, trans->slave_addr | 0x01);
358 
359  // Document the current Status
360  periph->status = I2CAddrRdSent;
361  }
362  // Address Was Sent
363  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1)) {
364  // --- make absolutely sure this command is not delayed too much after the previous:
365  // --- the NAK bits must be set before the first byte arrived: allow other interrupts here
367 
368  // if transfer of DR was finished already then we will get too many bytes
369  // BEFORE clearing ACK, read SR2 to clear the ADDR (next byte will start arriving)
370  // clearing ACK after the byte transfer has already started will NACK the next (2nd)
371  uint16_t SR2 __attribute__((unused)) = I2C_SR2(i2c);
372 
373  // NOT First Clear the ACK bit but only AFTER clearing ADDR
374  i2c_disable_ack(i2c);
375 
376  // Disable the RXNE and wait for BTF
377  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
378 
380  // --- end of critical zone -----------
381 
382  // We do not set the RxE but wait for both bytes to arrive using BTF
383 
384  // Document the current Status
385  periph->status = I2CReadingByte;
386  }
387  // Receive buffer if full, master is halted: BTF
388  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1)) {
389  // Stop condition MUST be set BEFORE reading the DR
390  // otherwise since there is new buffer space a new byte will be read
391  PPRZ_I2C_SEND_STOP(i2c);
392 
393  // Document the current Status
394  periph->status = I2CStopRequested;
395 
396  trans->buf[0] = I2C_DR(i2c);
397  trans->buf[1] = I2C_DR(i2c);
398 
399  // We got all the results
400  trans->status = I2CTransSuccess;
401 
403  } else { // Event Logic Error
404  return STMI2C_SubTra_Error;
405  }
406 
407  return STMI2C_SubTra_Busy;
408 }
409 
410 // Doc ID 13902 Rev 11 p 712/1072
411 // Transfer Sequence Diagram for Master Receiver for N>2
412 static inline enum STMI2CSubTransactionStatus stmi2c_readmany(uint32_t i2c, struct i2c_periph *periph,
413  struct i2c_transaction *trans)
414 {
415  uint16_t SR1 = I2C_SR1(i2c);
416 
417  // Start Condition Was Just Generated
418  if (BIT_X_IS_SET_IN_REG(I2C_SR1_SB, SR1)) {
419  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
420  // The first data byte will be acked in read many so the slave knows it should send more
421  i2c_nack_current(i2c);
422  i2c_enable_ack(i2c);
423  // Clear the SB flag
424  i2c_send_data(i2c, trans->slave_addr | 0x01);
425 
426  // Document the current Status
427  periph->status = I2CAddrRdSent;
428  }
429  // Address Was Sent
430  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1)) {
431  periph->idx_buf = 0;
432 
433  // Enable RXNE: receive an interrupt any time a byte is available
434  // only enable if MORE than 3 bytes need to be read
435  if (periph->idx_buf < (trans->len_r - 3)) {
436  i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN);
437  }
438 
439  // ACK is still on to get more DATA
440  // Read SR2 to clear the ADDR (next byte will start arriving)
441  uint16_t SR2 __attribute__((unused)) = I2C_SR2(i2c);
442 
443  // Document the current Status
444  periph->status = I2CReadingByte;
445  }
446  // one or more bytes are available AND we were interested in Buffer interrupts
447  else if ((BIT_X_IS_SET_IN_REG(I2C_SR1_RxNE, SR1)) && (BIT_X_IS_SET_IN_REG(I2C_CR2_ITBUFEN, I2C_CR2(i2c)))) {
448  // read byte until 3 bytes remain to be read (e.g. len_r = 6, -> idx=3 means idx 3,4,5 = 3 remain to be read
449  if (periph->idx_buf < (trans->len_r - 3)) {
450  trans->buf[periph->idx_buf] = I2C_DR(i2c);
451  periph->idx_buf ++;
452  }
453  // from : 3bytes -> last byte: do nothing
454  //
455  // finally: this was the last byte
456  else if (periph->idx_buf >= (trans->len_r - 1)) {
457  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
458 
459  // Last Value
460  trans->buf[periph->idx_buf] = i2c_get_data(i2c);
461  periph->idx_buf ++;
462 
463  // We got all the results
464  trans->status = I2CTransSuccess;
465 
467  }
468 
469  // Check for end of transaction: start waiting for BTF instead of RXNE
470  if (periph->idx_buf < (trans->len_r - 3)) {
471  i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN);
472  } else { // idx >= len-3: there are 3 bytes to be read
473  // We want to halt I2C to have sufficient time to clear ACK, so:
474  // Stop listening to RXNE as it will be triggered infinitely since we did not empty the buffer
475  // on the next (second in buffer) received byte BTF will be set (buffer full and I2C halted)
476  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
477  }
478  }
479  // Buffer is full while this was not a RXNE interrupt
480  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1)) {
481  // Now the shift register and data register contain data(n-2) and data(n-1)
482  // And I2C is halted so we have time
483 
484  // --- Make absolutely sure the next 2 I2C actions are performed with no delay
486 
487  // First we clear the ACK while the SCL is held low by BTF
488  i2c_disable_ack(i2c);
489 
490  // Now that ACK is cleared we read one byte: instantly the last byte is being clocked in...
491  trans->buf[periph->idx_buf] = i2c_get_data(i2c);
492  periph->idx_buf ++;
493 
494  // Now the last byte is being clocked. Stop in MUST be set BEFORE the transfer of the last byte is complete
495  PPRZ_I2C_SEND_STOP(i2c);
496 
498 
499 
500  // --- end of critical zone -----------
501 
502  // Document the current Status
503  periph->status = I2CStopRequested;
504 
505  // read the byte2 we had in the buffer (BTF means 2 bytes available)
506  trans->buf[periph->idx_buf] = i2c_get_data(i2c);
507  periph->idx_buf ++;
508 
509  // Ask for an interrupt to read the last byte (which is normally still busy now)
510  // The last byte will be received with RXNE
511  i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN);
512  } else { // Event Logic Error
513  return STMI2C_SubTra_Error;
514  }
515 
516  return STMI2C_SubTra_Busy;
517 }
518 
520 // Restore bus conditions to normal after errors
521 
522 static inline void i2c_error(struct i2c_periph *periph)
523 {
524  periph->errors->er_irq_cnt++;
525  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_AF) != 0) { /* Acknowledge failure */
526  periph->errors->ack_fail_cnt++;
527  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_AF;
528  }
529  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_BERR) != 0) { /* Misplaced Start or Stop condition */
530  periph->errors->miss_start_stop_cnt++;
531  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_BERR;
532  }
533  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_ARLO) != 0) { /* Arbitration lost */
534  periph->errors->arb_lost_cnt++;
535  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_ARLO;
536  }
537  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_OVR) != 0) { /* Overrun/Underrun */
538  periph->errors->over_under_cnt++;
539  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_OVR;
540  }
541  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_PECERR) != 0) { /* PEC Error in reception */
542  periph->errors->pec_recep_cnt++;
543  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_PECERR;
544  }
545  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_TIMEOUT) != 0) { /* Timeout or Tlow error */
546  periph->errors->timeout_tlow_cnt++;
547  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_TIMEOUT;
548  }
549  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_SMBALERT) != 0) { /* SMBus alert */
550  periph->errors->smbus_alert_cnt++;
551  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_SMBALERT;
552  }
553 
554  return;
555 }
556 
557 
559 {
560  uint16_t SR1 = I2C_SR1(i2c);
561 
562  // Certainly do not wait for buffer interrupts:
563  // -------------------------------------------
564  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN); // Disable TXE, RXNE
565 
566  // Error interrupts are handled separately:
567  // ---------------------------------------
568 
569  // Clear Event interrupt conditions:
570  // --------------------------------
571 
572  // Start Condition Was Generated
573  if (BIT_X_IS_SET_IN_REG(I2C_SR1_SB, SR1)) {
574  // SB: cleared by software when reading SR1 and writing to DR
575  i2c_send_data(i2c, 0x00);
576  }
577  // Address Was Sent
578  if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1)) {
579  // ADDR: Cleared by software when reading SR1 and then SR2
580  uint16_t SR2 __attribute__((unused)) = I2C_SR2(i2c);
581  }
582  // Byte Transfer Finished
583  if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1)) {
584  // SB: cleared by software when reading SR1 and reading/writing to DR
585  uint8_t dummy __attribute__((unused)) = i2c_get_data(i2c);
586  i2c_send_data(i2c, 0x00);
587  }
588 
589 }
590 
591 
593 // Restore bus conditions to normal after errors
594 
595 static inline void i2c_irq(struct i2c_periph *periph)
596 {
597 
598  /*
599  There are 7 possible event reasons to get here + all errors
600 
601  If IT_EV_FEN
602  -------------------------
603 
604  We are always interested in all IT_EV_FEV: all are required.
605 
606  1) SB // Start Condition Success in Master mode
607  2) ADDR // Address sent received Acknowledge
608  [ADDR10] // -- 10bit address stuff: not used
609  [STOPF] // -- only for slaves: master has no stop interrupt: not used
610  3) BTF // I2C has stopped working (it is waiting for new data, all buffers are tx_empty/rx_full)
611 
612  // Beware: using the buffered I2C has some interesting properties:
613  - in master receive mode: BTF only occurs after the 2nd received byte: after the first byte is received it is
614  in RD but the I2C can still receive a second byte. Only when the 2nd byte is received while the RxNE is 1
615  then a BTF occurs (I2C can not continue receiving bytes or they will get lost). During BTF I2C is halted (SCL held low)
616  - in master transmit mode: when writing a byte to WD, you instantly get a new TxE interrupt while the first is not
617  transmitted yet. The byte was pushed to the I2C shift register and the buffer is ready for more. You can already
618  fill new data in the buffer while the first is still being transmitted for max performance transmission.
619 
620  // Beware: besides data buffering you can/must plan several consecutive actions. You can send 2 bytes to the buffer, ask for a stop and
621  a new start in one go.
622 
623  - thanks to / because of this buffering and event sheduling there is not 1 interrupt per start / byte / stop
624  This also means you must think more in advance and a transaction could be popped from the transaction stack even before it's
625  stop condition is actually generated.
626 
627  // Beware: the order in which Status (and other register) is read determines how flags are cleared.
628  You should NOT simply read SR1 & SR2 every time
629 
630  If IT_EV_FEN AND IT_EV_BUF
631  --------------------------
632 
633  Buffer event are not always wanted and are typically switched on during longer data transfers. Make sure to turn off in time.
634 
635  4) RxNE
636  5) TxE
637 
638  --------------------------------------------------------------------------------------------------
639 
640  The STM waits indefinitely (holding SCL low) for user interaction:
641  a) after a master-start (waiting for address)
642  b) after an address (waiting for data)
643  not during data sending when using buffered
644  c) after the last byte is transmitted (waiting for either stop or restart)
645  not during data receiving when using buffered
646  not after the last byte is received
647 
648  - The STM I2C stalls indefinitely when a stop condition was attempted that
649  did not succeed. The BUSY flag remains on.
650  - There is no STOP interrupt.
651 
652  Caution Reading the status:
653  - Caution: this clears several flags and can start transmissions etc...
654  - Certain flags like STOP / (N)ACK need to be guaranteed to be set before
655  the transmission of the byte is finished. At higher clock rates that can be
656  quite fast: so we allow no other interrupt to be triggered in between
657  reading the status and setting all needed flags
658 
659  */
660 
661  // Here we go ...
662 
663  // Apparently we got an I2C interrupt: EVT BUF or ERR
664 
665  // Save Some Direct Access to the I2C Registers ...
666  uint32_t i2c = (uint32_t) periph->reg_addr;
667 
669  // Check if we were ready ...
670  if (periph->trans_extract_idx == periph->trans_insert_idx) {
671  // Nothing Left To Do
672 
673  // If we still get an interrupt but there are no more things to do
674  // (which can happen if an event was sheduled just before a bus error occurs)
675  // (or can happen if both error and event interrupts were called together [the 2nd will then get this error])
676 
677  // since there is nothing more to do: its easy: just stop: clear all interrupt generating bits
678 
679  // Count The Errors
680  i2c_error(periph);
681 
682  // Clear Running Events
684 
685  // Mark this as a special error
686  periph->errors->last_unexpected_event++;
687 
688  // Document the current Status
689  periph->status = I2CIdle;
690 
691  // There are no transactions anymore: return
692  // further-on in this routine we need a transaction pointer: so we are not allowed to continue
693  return;
694  }
695 
696  // get the I2C transaction we were working on ...
697 
698  enum STMI2CSubTransactionStatus ret = 0;
699  struct i2c_transaction *trans = periph->trans[periph->trans_extract_idx];
700 
702  // If there was an error:
703  if ((I2C_SR1(i2c) & I2C_SR1_ERR_MASK) != 0x0000) {
704 
705  // Notify everyone about the error ...
706 
707  // Set result in transaction
708  trans->status = I2CTransFailed;
709 
710  // Document the current Status
711  periph->status = I2CFailed;
712 
713  // Make sure a TxRx does not Restart
714  trans->type = I2CTransRx;
715 
716  // Count The Errors
717  i2c_error(periph);
718 
719  // Clear Running Events
721 
722  // Now continue as if everything was normal from now on
723  ret = STMI2C_SubTra_Ready;
724 
725  }
726 
728  // Normal Event:
729  else {
730 
733  //
734  // SUB-TRANSACTION HANDLER
735 
736  if (trans->type == I2CTransRx) { // TxRx are converted to Rx after the Tx Part
737  switch (trans->len_r) {
738  case 1:
739  ret = stmi2c_read1(i2c, periph, trans);
740  break;
741  case 2:
742  ret = stmi2c_read2(i2c, periph, trans);
743  break;
744  default:
745  ret = stmi2c_readmany(i2c, periph, trans);
746  break;
747  }
748  } else { // TxRx or Tx
749  ret = stmi2c_send(i2c, periph, trans);
750  }
751  }
752 
754  // Sub-transaction has finished
755  if (ret != STMI2C_SubTra_Busy) {
756  // Ready or SubTraError
757  // -ready: with or without stop already asked
758 
759  // In case of unexpected event condition during subtransaction handling:
760  if (ret == STMI2C_SubTra_Error) {
761  // Tell everyone about the subtransaction error:
762  // this is the previously called SPURRIOUS INTERRUPT
763  periph->status = I2CFailed;
764  trans->type = I2CTransRx; // Avoid possible restart
765  trans->status = I2CTransFailed; // Notify Ready
766  periph->errors->unexpected_event_cnt++;
767 
768  // Clear Running Events
770  }
771 
772  // RxTx -> Restart and do Rx part
773  if (trans->type == I2CTransTxRx) {
774  trans->type = I2CTransRx;
775  periph->status = I2CStartRequested;
776  i2c_send_start(i2c);
777 
778  // Silent any BTF that would occur before SB
779  i2c_send_data(i2c, 0x00);
780  }
781  // If a restart is not needed: Rx part or Tx-only
782  else {
783  // Ready, no stop condition set yet
784  if (ret == STMI2C_SubTra_Ready) {
785 
786  // Program a stop
787  PPRZ_I2C_SEND_STOP(i2c);
788 
789  // Silent any BTF that would occur before STOP is executed
790  i2c_send_data(i2c, 0x00);
791  }
792 
793  // Jump to the next transaction
794  periph->trans_extract_idx++;
796  periph->trans_extract_idx = 0;
797  }
798 
799  // Tell everyone we are ready
800  periph->status = I2CIdle;
801 
802 
803  // if we have no more transaction to process, stop here
804  if (periph->trans_extract_idx == periph->trans_insert_idx) {
805 
806  periph->watchdog = -1; // stop watchdog
807  }
808  // if not, start next transaction
809  else {
810  // Restart transaction doing the Rx part now
811  // --- moved to idle function
812  PPRZ_I2C_SEND_START(periph);
813  // ------
814  }
815  }
816  }
817 
818  return;
819 }
820 
821 
822 /*
823 // Make sure the bus is free before resetting (p722)
824 if (regs->SR2 & (I2C_FLAG_BUSY >> 16)) {
825 // Reset the I2C block
826 I2C_SoftwareResetCmd(periph->reg_addr, ENABLE);
827 I2C_SoftwareResetCmd(periph->reg_addr, DISABLE);
828 }
829 */
830 
831 
832 #if USE_I2C0
833 #error "The STM32 doesn't have I2C0, use I2C1 or I2C2"
834 #endif
835 
836 #if USE_I2C1
837 
839 #ifndef I2C1_CLOCK_SPEED
840 #define I2C1_CLOCK_SPEED 200000
841 #endif
842 PRINT_CONFIG_VAR(I2C1_CLOCK_SPEED)
843 
844 struct i2c_errors i2c1_errors;
845 
846 void i2c1_hw_init(void)
847 {
848 
849  i2c1.reg_addr = (void *)I2C1;
850  i2c1.init_struct = NULL;
851  i2c1.errors = &i2c1_errors;
852  i2c1.watchdog = -1;
853 
854  /* zeros error counter */
855  ZEROS_ERR_COUNTER(i2c1_errors);
856 
857  /* reset peripheral to default state ( sometimes not achieved on reset :( ) */
858  //rcc_periph_reset_pulse(RST_I2C1);
859 
860  /* Configure and enable I2C1 event interrupt --------------------------------*/
861  nvic_set_priority(NVIC_I2C1_EV_IRQ, NVIC_I2C1_IRQ_PRIO);
862  nvic_enable_irq(NVIC_I2C1_EV_IRQ);
863 
864  /* Configure and enable I2C1 err interrupt ----------------------------------*/
865  nvic_set_priority(NVIC_I2C1_ER_IRQ, NVIC_I2C1_IRQ_PRIO + 1);
866  nvic_enable_irq(NVIC_I2C1_ER_IRQ);
867 
868  /* Enable peripheral clocks -------------------------------------------------*/
869  /* Enable I2C1 clock */
870  rcc_periph_clock_enable(RCC_I2C1);
871  /* setup gpio clock and pins */
872  i2c_setup_gpio(I2C1);
873 
874  rcc_periph_reset_pulse(RST_I2C1);
875 
876  // enable peripheral
877  i2c_peripheral_enable(I2C1);
878 
879  i2c_set_own_7bit_slave_address(I2C1, 0);
880 
881  // enable error interrupts
882  i2c_enable_interrupt(I2C1, I2C_CR2_ITERREN);
883 
885 }
886 
887 void i2c1_ev_isr(void)
888 {
889  uint32_t i2c = (uint32_t) i2c1.reg_addr;
890  i2c_disable_interrupt(i2c, I2C_CR2_ITERREN);
891  i2c1.watchdog = 0; // restart watchdog
892  i2c_irq(&i2c1);
893  i2c_enable_interrupt(i2c, I2C_CR2_ITERREN);
894 }
895 
896 void i2c1_er_isr(void)
897 {
898  uint32_t i2c = (uint32_t) i2c1.reg_addr;
899  i2c_disable_interrupt(i2c, I2C_CR2_ITEVTEN);
900  i2c1.watchdog = 0; // restart watchdog
901  i2c_irq(&i2c1);
902  i2c_enable_interrupt(i2c, I2C_CR2_ITEVTEN);
903 }
904 
905 #endif /* USE_I2C1 */
906 
907 #if USE_I2C2
908 
910 #ifndef I2C2_CLOCK_SPEED
911 #define I2C2_CLOCK_SPEED 300000
912 #endif
913 PRINT_CONFIG_VAR(I2C2_CLOCK_SPEED)
914 
915 struct i2c_errors i2c2_errors;
916 
917 void i2c2_hw_init(void)
918 {
919 
920  i2c2.reg_addr = (void *)I2C2;
921  i2c2.init_struct = NULL;
922  i2c2.errors = &i2c2_errors;
923  i2c2.watchdog = -1;
924 
925  /* zeros error counter */
926  ZEROS_ERR_COUNTER(i2c2_errors);
927 
928  /* reset peripheral to default state ( sometimes not achieved on reset :( ) */
929  //rcc_periph_reset_pulse(RST_I2C2);
930 
931  /* Configure and enable I2C2 event interrupt --------------------------------*/
932  nvic_set_priority(NVIC_I2C2_EV_IRQ, NVIC_I2C2_IRQ_PRIO);
933  nvic_enable_irq(NVIC_I2C2_EV_IRQ);
934 
935  /* Configure and enable I2C2 err interrupt ----------------------------------*/
936  nvic_set_priority(NVIC_I2C2_ER_IRQ, NVIC_I2C2_IRQ_PRIO + 1);
937  nvic_enable_irq(NVIC_I2C2_ER_IRQ);
938 
939  /* Enable peripheral clocks -------------------------------------------------*/
940  /* Enable I2C2 clock */
941  rcc_periph_clock_enable(RCC_I2C2);
942 
943  /* setup gpio clock and pins */
944  i2c_setup_gpio(I2C2);
945 
946  rcc_periph_reset_pulse(RST_I2C2);
947 
948  // enable peripheral
949  i2c_peripheral_enable(I2C2);
950 
951  i2c_set_own_7bit_slave_address(I2C2, 0);
952 
953  // enable error interrupts
954  i2c_enable_interrupt(I2C2, I2C_CR2_ITERREN);
955 
957 }
958 
959 void i2c2_ev_isr(void)
960 {
961  uint32_t i2c = (uint32_t) i2c2.reg_addr;
962  i2c_disable_interrupt(i2c, I2C_CR2_ITERREN);
963  i2c2.watchdog = 0; // restart watchdog
964  i2c_irq(&i2c2);
965  i2c_enable_interrupt(i2c, I2C_CR2_ITERREN);
966 }
967 
968 void i2c2_er_isr(void)
969 {
970  uint32_t i2c = (uint32_t) i2c2.reg_addr;
971  i2c_disable_interrupt(i2c, I2C_CR2_ITEVTEN);
972  i2c2.watchdog = 0; // restart watchdog
973  i2c_irq(&i2c2);
974  i2c_enable_interrupt(i2c, I2C_CR2_ITEVTEN);
975 }
976 
977 #endif /* USE_I2C2 */
978 
979 
980 #if USE_I2C3 && defined STM32F4
981 
983 #ifndef I2C3_CLOCK_SPEED
984 #define I2C3_CLOCK_SPEED 300000
985 #endif
986 PRINT_CONFIG_VAR(I2C3_CLOCK_SPEED)
987 
988 struct i2c_errors i2c3_errors;
989 
990 void i2c3_hw_init(void)
991 {
992 
993  i2c3.reg_addr = (void *)I2C3;
994  i2c3.init_struct = NULL;
995  i2c3.errors = &i2c3_errors;
996  i2c3.watchdog = -1;
997 
998  /* zeros error counter */
999  ZEROS_ERR_COUNTER(i2c3_errors);
1000 
1001  /* reset peripheral to default state ( sometimes not achieved on reset :( ) */
1002  //rcc_periph_reset_pulse(RST_I2C3);
1003 
1004  /* Configure and enable I2C3 event interrupt --------------------------------*/
1005  nvic_set_priority(NVIC_I2C3_EV_IRQ, NVIC_I2C3_IRQ_PRIO);
1006  nvic_enable_irq(NVIC_I2C3_EV_IRQ);
1007 
1008  /* Configure and enable I2C3 err interrupt ----------------------------------*/
1009  nvic_set_priority(NVIC_I2C3_ER_IRQ, NVIC_I2C3_IRQ_PRIO + 1);
1010  nvic_enable_irq(NVIC_I2C3_ER_IRQ);
1011 
1012  /* Enable peripheral clocks -------------------------------------------------*/
1013  /* Enable I2C3 clock */
1014  rcc_periph_clock_enable(RCC_I2C3);
1015 
1016  /* setup gpio clock and pins */
1017  i2c_setup_gpio(I2C3);
1018 
1019  rcc_periph_reset_pulse(RST_I2C3);
1020 
1021  // enable peripheral
1022  i2c_peripheral_enable(I2C3);
1023 
1024  i2c_set_own_7bit_slave_address(I2C3, 0);
1025 
1026  // enable error interrupts
1027  i2c_enable_interrupt(I2C3, I2C_CR2_ITERREN);
1028 
1029  i2c_setbitrate(&i2c3, I2C3_CLOCK_SPEED);
1030 }
1031 
1032 void i2c3_ev_isr(void)
1033 {
1034  uint32_t i2c = (uint32_t) i2c3.reg_addr;
1035  i2c_disable_interrupt(i2c, I2C_CR2_ITERREN);
1036  i2c3.watchdog = 0; // restart watchdog
1037  i2c_irq(&i2c3);
1038  i2c_enable_interrupt(i2c, I2C_CR2_ITERREN);
1039 }
1040 
1041 void i2c3_er_isr(void)
1042 {
1043  uint32_t i2c = (uint32_t) i2c3.reg_addr;
1044  i2c_disable_interrupt(i2c, I2C_CR2_ITEVTEN);
1045  i2c3.watchdog = 0; // restart watchdog
1046  i2c_irq(&i2c3);
1047  i2c_enable_interrupt(i2c, I2C_CR2_ITEVTEN);
1048 }
1049 
1050 #endif /* USE_I2C3 */
1051 
1053 // Set Bitrate to Match your application:
1054 // -short wires, low capacitance bus: IMU: high speed
1055 // -long wires with a lot of capacitance: motor controller: put speed as low as possible
1056 
1057 void i2c_setbitrate(struct i2c_periph *periph, int bitrate)
1058 {
1059  // If NOT Busy
1060  if (i2c_idle(periph)) {
1061  volatile int devider;
1062  volatile int risetime;
1063 
1064  uint32_t i2c = (uint32_t) periph->reg_addr;
1065 
1066  /*****************************************************
1067  Bitrate:
1068 
1069  -CR2 + CCR + TRISE registers
1070  -only change when PE=0
1071 
1072  e.g.
1073 
1074  10kHz: 36MHz + Standard 0x708 + 0x25
1075  70kHz: 36MHz + Standard 0x101 +
1076  400kHz: 36MHz + Fast 0x1E + 0xb
1077 
1078  // 1) Program peripheral input clock CR2: to get correct timings
1079  // 2) Configure clock control registers
1080  // 3) Configure rise time register
1081  ******************************************************/
1082 
1083  if (bitrate < 3000) {
1084  bitrate = 3000;
1085  }
1086 
1087  // rcc_apb1_frequency is normally configured to max: 36MHz on F1 and 42MHz on F4
1088  // in fast mode: 2counts low 1 count high -> / 3:
1089  // in standard mode: 1 count low, 1 count high -> /2:
1090  devider = (rcc_apb1_frequency / 2000) / (bitrate / 1000);
1091 
1092  // never allow faster than 600kbps
1093  if (devider < 20) {
1094  devider = 20;
1095  }
1096 
1097  // no overflow either
1098  if (devider >= 4095) {
1099  devider = 4095;
1100  }
1101 
1102  // risetime can be up to 1/6th of the period
1103  risetime = 1000000 / (bitrate / 1000) / 6 / 28;
1104 
1105  if (risetime < 10) {
1106  risetime = 10;
1107  }
1108 
1109  // more will overflow the register: for more you should lower the FREQ
1110  if (risetime >= 31) {
1111  risetime = 31;
1112  }
1113 
1114  // we do not expect an interrupt as the interface should have been idle, but just in case...
1115  __disable_irq(); // this code is in user space:
1116 
1117  // CCR can only be written when PE is disabled
1118  // p731 note 5
1119  i2c_peripheral_disable(i2c);
1120 
1121  // 1)
1122 #ifdef STM32F1
1123  i2c_set_clock_frequency(i2c, I2C_CR2_FREQ_36MHZ);
1124 #else // STM32F4
1125  i2c_set_clock_frequency(i2c, I2C_CR2_FREQ_42MHZ);
1126 #endif
1127  // 2)
1128  //i2c_set_fast_mode(i2c);
1129  i2c_set_ccr(i2c, devider);
1130  // 3)
1131  i2c_set_trise(i2c, risetime);
1132 
1133  // Re-Enable
1134  i2c_peripheral_enable(i2c);
1135 
1136  __enable_irq();
1137 
1138  }
1139 }
1140 
1141 #define WD_DELAY 20 // number of ticks with 2ms - 40ms delay before resetting the bus
1142 #define WD_RECOVERY_TICKS 18 // number of generated SCL clocking pulses
1143 
1144 #if USE_I2C1 || USE_I2C2 || USE_I2C3
1145 static inline void i2c_scl_set(uint32_t i2c)
1146 {
1147 #if USE_I2C1
1148  if (i2c == I2C1) {
1150  }
1151 #endif
1152 #if USE_I2C2
1153  if (i2c == I2C2) {
1155  }
1156 #endif
1157 #if USE_I2C3
1158  if (i2c == I2C3) {
1160  }
1161 #endif
1162 }
1163 
1164 static inline void i2c_scl_toggle(uint32_t i2c)
1165 {
1166 #if USE_I2C1
1167  if (i2c == I2C1) {
1169  }
1170 #endif
1171 #if USE_I2C2
1172  if (i2c == I2C2) {
1174  }
1175 #endif
1176 #if USE_I2C3
1177  if (i2c == I2C3) {
1179  }
1180 #endif
1181 }
1182 
1183 static inline bool i2c_sda_get(uint32_t i2c)
1184 {
1185  bool res = false;
1186 #if USE_I2C1
1187  if (i2c == I2C1) {
1189  }
1190 #endif
1191 #if USE_I2C2
1192  if (i2c == I2C2) {
1194  }
1195 #endif
1196 #if USE_I2C3
1197  if (i2c == I2C3) {
1199  }
1200 #endif
1201  return res;
1202 }
1203 
1204 static void i2c_wd_check(struct i2c_periph *periph)
1205 {
1206  uint32_t i2c = (uint32_t) periph->reg_addr;
1207 
1208  if (periph->watchdog > WD_DELAY) {
1209  if (periph->watchdog == WD_DELAY + 1) {
1210 
1211  i2c_disable_interrupt(i2c, I2C_CR2_ITEVTEN);
1212  i2c_disable_interrupt(i2c, I2C_CR2_ITERREN);
1213 
1214  periph->trans_insert_idx = 0;
1215  periph->trans_extract_idx = 0;
1216  periph->status = I2CIdle;
1217  struct i2c_transaction *trans;
1218  for (uint8_t i = 0; i < I2C_TRANSACTION_QUEUE_LEN; i++) {
1219  trans = periph->trans[i];
1220  trans->status = I2CTransFailed;
1221  }
1222 
1223  i2c_peripheral_disable(i2c);
1224 
1225 #if USE_I2C1
1226  if (i2c == I2C1) {
1229  }
1230 #endif
1231 #if USE_I2C2
1232  if (i2c == I2C2) {
1235  }
1236 #endif
1237 #if USE_I2C3
1238  if (i2c == I2C3) {
1241  }
1242 #endif
1243 
1244  i2c_scl_set(i2c);
1245  } else if (periph->watchdog < WD_DELAY + WD_RECOVERY_TICKS) {
1246  if (i2c_sda_get(i2c)) {
1247  periph->watchdog = WD_DELAY + WD_RECOVERY_TICKS;
1248  }
1249  i2c_scl_toggle(i2c);
1250  } else {
1251  i2c_scl_set(i2c);
1252 
1253  /* setup gpios for normal i2c operation again */
1254  i2c_setup_gpio(i2c);
1255 
1256  i2c_reset(i2c);
1257 
1258  i2c_peripheral_enable(i2c);
1259  i2c_set_own_7bit_slave_address(i2c, 0);
1260  i2c_enable_interrupt(i2c, I2C_CR2_ITERREN);
1261 
1262 #if USE_I2C1
1263  if (i2c == I2C1) {
1265  }
1266 #endif
1267 #if USE_I2C2
1268  if (i2c == I2C2) {
1270  }
1271 #endif
1272 #if USE_I2C3
1273  if (i2c == I2C3) {
1274  i2c_setbitrate(periph, I2C3_CLOCK_SPEED);
1275  }
1276 #endif
1277 
1278  periph->watchdog = 0; // restart watchdog
1279 
1280  periph->errors->wd_reset_cnt++;
1281 
1282  return;
1283  }
1284  }
1285  if (periph->watchdog >= 0) {
1286  periph->watchdog++;
1287  }
1288 }
1289 #endif // USE_I2Cx
1290 
1291 #include "mcu_periph/sys_time.h"
1292 
1293 void i2c_event(void)
1294 {
1295  static uint32_t i2c_wd_timer;
1296 
1297  if (SysTimeTimer(i2c_wd_timer) > 2000) { // 2ms (500Hz) periodic watchdog check
1298  SysTimeTimerStart(i2c_wd_timer);
1299 #if USE_I2C1
1300  i2c_wd_check(&i2c1);
1301 #endif
1302 
1303 #if USE_I2C2
1304  i2c_wd_check(&i2c2);
1305 #endif
1306 #if USE_I2C3
1307  i2c_wd_check(&i2c3);
1308 #endif
1309  }
1310 }
1311 
1313 // Implement Interface Functions
1314 
1315 bool i2c_submit(struct i2c_periph *periph, struct i2c_transaction *t)
1316 {
1317  if (periph->watchdog > WD_DELAY) {
1318  return false;
1319  }
1320 
1321  uint8_t temp;
1322  temp = periph->trans_insert_idx + 1;
1323  if (temp >= I2C_TRANSACTION_QUEUE_LEN) { temp = 0; }
1324  if (temp == periph->trans_extract_idx) {
1325  // queue full
1326  periph->errors->queue_full_cnt++;
1327  t->status = I2CTransFailed;
1328  return false;
1329  }
1330 
1331  t->status = I2CTransPending;
1332 
1333  __disable_irq();
1334  /* put transacation in queue */
1335  periph->trans[periph->trans_insert_idx] = t;
1336  periph->trans_insert_idx = temp;
1337 
1338  /* if peripheral is idle, start the transaction */
1339  // if (PPRZ_I2C_IS_IDLE(p))
1340  if (periph->status == I2CIdle) {
1341  //if (i2c_idle(periph))
1342  {
1343  PPRZ_I2C_SEND_START(periph);
1344  }
1345  }
1346  /* else it will be started by the interrupt handler when the previous transactions completes */
1347  __enable_irq();
1348 
1349  return true;
1350 }
1351 
1352 bool i2c_idle(struct i2c_periph *periph)
1353 {
1354  // This is actually a difficult function:
1355  // -simply reading the status flags can clear bits and corrupt the transaction
1356 
1357  uint32_t i2c = (uint32_t) periph->reg_addr;
1358 
1359  // First we check if the software thinks it is ready
1360  if (periph->status == I2CIdle) {
1361  return !(BIT_X_IS_SET_IN_REG(I2C_SR2_BUSY, I2C_SR2(i2c)));
1362  } else {
1363  return false;
1364  }
1365 }
1366 
unsigned short uint16_t
Definition: types.h:16
volatile uint16_t arb_lost_cnt
Definition: i2c.h:159
volatile uint8_t idx_buf
Definition: i2c.h:145
#define I2C_TRANSACTION_QUEUE_LEN
I2C transaction queue length.
Definition: i2c.h:133
I2C errors counter.
Definition: i2c.h:154
#define I2C3_GPIO_SCL
Definition: krooz_sd.h:134
#define I2C3_GPIO_PORT_SCL
Definition: krooz_sd.h:132
#define I2C1
Definition: LPC21xx.h:166
volatile uint16_t miss_start_stop_cnt
Definition: i2c.h:158
volatile uint8_t buf[I2C_BUF_LEN]
Transaction buffer With I2C_BUF_LEN number of bytes.
Definition: i2c.h:122
uint16_t len_r
Number of bytes to read/receive.
Definition: i2c.h:110
static void __enable_irq(void)
Definition: i2c_arch.c:62
transaction successfully finished by I2C driver
Definition: i2c.h:57
static void i2c_irq(struct i2c_periph *periph)
Definition: i2c_arch.c:595
#define I2C2_GPIO_PORT
Definition: apogee_1.0.h:214
#define I2C3_GPIO_SDA
Definition: krooz_sd.h:135
Some architecture independent helper functions for GPIOs.
transmit and receive transaction
Definition: i2c.h:49
uint8_t trans_extract_idx
Definition: i2c.h:142
#define WD_DELAY
Definition: i2c_arch.c:1141
bool i2c_idle(struct i2c_periph *p)
i2c_idle() function
Definition: i2c_arch.c:417
static void __disable_irq(void)
Definition: i2c_arch.c:61
Definition: i2c.h:66
volatile uint16_t queue_full_cnt
Definition: i2c.h:156
#define GPIOB
Definition: gpio_arch.h:35
#define BIT_X_IS_SET_IN_REG(X, REG)
Definition: i2c_arch.c:57
void i2c_setbitrate(struct i2c_periph *p, int bitrate)
i2c_setbitrate() function
Definition: i2c_arch.c:359
struct i2c_errors * errors
Definition: i2c.h:148
#define __I2C_REG_CRITICAL_ZONE_STOP
Definition: i2c_arch.c:67
enum I2CStatus status
Definition: i2c.h:144
static enum STMI2CSubTransactionStatus stmi2c_readmany(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
Definition: i2c_arch.c:412
void gpio_setup_output(ioportid_t port, uint16_t gpios)
Setup one or more pins of the given GPIO port as outputs.
Definition: gpio_arch.c:33
volatile uint32_t er_irq_cnt
Definition: i2c.h:166
static void gpio_toggle(ioportid_t port, uint16_t pin)
Toggle a gpio output to low level.
Definition: gpio_arch.h:118
#define I2C3_GPIO_PORT_SDA
Definition: krooz_sd.h:133
void * reg_addr
Definition: i2c.h:146
#define I2C1_GPIO_SDA
Definition: apogee_1.0.h:212
void gpio_enable_clock(uint32_t port)
Enable the relevant clock.
Definition: gpio_arch.c:34
#define __I2C_REG_CRITICAL_ZONE_START
Definition: i2c_arch.c:66
#define I2C_SR1_ERR_MASK
Definition: i2c_arch.c:47
uint8_t len_w
Number of bytes to write/transmit.
Definition: i2c.h:116
#define NVIC_I2C1_IRQ_PRIO
Definition: i2c_arch.c:71
#define ZEROS_ERR_COUNTER(_i2c_err)
Definition: i2c.h:170
static enum STMI2CSubTransactionStatus stmi2c_read2(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
Definition: i2c_arch.c:346
Architecture independent timing functions.
static void i2c_error(struct i2c_periph *periph)
Definition: i2c_arch.c:522
unsigned long uint32_t
Definition: types.h:18
struct i2c_transaction * trans[I2C_TRANSACTION_QUEUE_LEN]
Definition: i2c.h:140
volatile uint16_t over_under_cnt
Definition: i2c.h:160
bool i2c_submit(struct i2c_periph *p, struct i2c_transaction *t)
i2c_submit() function
Definition: i2c_arch.c:378
transaction failed
Definition: i2c.h:58
Definition: i2c.h:77
static enum STMI2CSubTransactionStatus stmi2c_read1(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
Definition: i2c_arch.c:287
I2C transaction structure.
Definition: i2c.h:93
enum I2CTransactionStatus status
Transaction status.
Definition: i2c.h:126
#define SysTimeTimer(_t)
Definition: sys_time.h:219
#define NVIC_I2C2_IRQ_PRIO
Definition: i2c_arch.c:72
volatile uint16_t unexpected_event_cnt
Definition: i2c.h:164
uint8_t slave_addr
Slave address.
Definition: i2c.h:104
I2C peripheral structure.
Definition: i2c.h:138
static uint8_t gpio_get(ioportid_t port, uint16_t pin)
Get level of a gpio.
Definition: gpio_arch.h:88
unsigned char uint8_t
Definition: types.h:14
STMI2CSubTransactionStatus
Definition: i2c_arch.c:206
#define NVIC_I2C3_IRQ_PRIO
Definition: i2c_arch.c:73
transmit only transaction
Definition: i2c.h:47
volatile int16_t watchdog
Definition: i2c.h:149
volatile uint32_t last_unexpected_event
Definition: i2c.h:165
#define I2C2_GPIO_SCL
Definition: apogee_1.0.h:215
static enum STMI2CSubTransactionStatus stmi2c_send(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
Definition: i2c_arch.c:215
volatile uint16_t wd_reset_cnt
Definition: i2c.h:155
volatile uint16_t smbus_alert_cnt
Definition: i2c.h:163
#define WD_RECOVERY_TICKS
Definition: i2c_arch.c:1142
#define I2C2_GPIO_SDA
Definition: apogee_1.0.h:216
void i2c_event(void)
i2c_event() function
Definition: i2c_arch.c:351
enum I2CTransactionType type
Transaction type.
Definition: i2c.h:98
#define I2C1_CLOCK_SPEED
I2C defines.
Definition: board.h:476
#define SysTimeTimerStart(_t)
Definition: sys_time.h:218
uint8_t trans_insert_idx
Definition: i2c.h:141
volatile uint16_t pec_recep_cnt
Definition: i2c.h:161
#define I2C1_GPIO_SCL
Definition: apogee_1.0.h:211
void gpio_setup_input(ioportid_t port, uint16_t gpios)
Setup one or more pins of the given GPIO port as inputs.
Definition: gpio_arch.c:40
static void PPRZ_I2C_SEND_START(struct i2c_periph *periph)
Definition: i2c_arch.c:175
receive only transaction
Definition: i2c.h:48
#define I2C2_CLOCK_SPEED
Definition: board.h:492
static void gpio_set(ioportid_t port, uint16_t pin)
Set a gpio output to high level.
Definition: gpio_arch.h:98
transaction is pending in queue
Definition: i2c.h:55
static void stmi2c_clear_pending_interrupts(uint32_t i2c)
Definition: i2c_arch.c:558
#define I2C1_GPIO_PORT
Definition: apogee_1.0.h:210
#define I2C3_GPIO_SDA_AF
static void PPRZ_I2C_SEND_STOP(uint32_t i2c)
Definition: i2c_arch.c:167
volatile uint16_t ack_fail_cnt
Definition: i2c.h:157
volatile uint16_t timeout_tlow_cnt
Definition: i2c.h:162
Architecture independent I2C (Inter-Integrated Circuit Bus) API.