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uart_arch.c
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1 /*
2  * Copyright (C) 2009 Antoine Drouin <poinix@gmail.com>
3  * Copyright (C) 2013 Felix Ruess <felix.ruess@gmail.com>
4  *
5  * This file is part of paparazzi.
6  *
7  * paparazzi is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2, or (at your option)
10  * any later version.
11  *
12  * paparazzi is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with paparazzi; see the file COPYING. If not, write to
19  * the Free Software Foundation, 59 Temple Place - Suite 330,
20  * Boston, MA 02111-1307, USA.
21  */
22 
30 #include "mcu_periph/uart.h"
31 #include "mcu_periph/gpio.h"
32 
33 #include <libopencm3/stm32/gpio.h>
34 #include <libopencm3/stm32/rcc.h>
35 #include <libopencm3/stm32/usart.h>
36 #include <libopencm3/cm3/nvic.h>
37 
38 #include "std.h"
39 
40 #include BOARD_CONFIG
41 
43 {
44  p->baudrate = baud;
45 
46  /* Configure USART baudrate */
47  usart_set_baudrate((uint32_t)p->reg_addr, baud);
48 
49  /* Disable Idle Line interrupt */
50  USART_CR1((uint32_t)p->reg_addr) &= ~USART_CR1_IDLEIE;
51 
52  /* Disable LIN break detection interrupt */
53  USART_CR2((uint32_t)p->reg_addr) &= ~USART_CR2_LBDIE;
54 
55  /* Enable USART1 Receive interrupts */
56  USART_CR1((uint32_t)p->reg_addr) |= USART_CR1_RXNEIE;
57 
58  /* Enable the USART */
59  usart_enable((uint32_t)p->reg_addr);
60 
61 }
62 
64 {
65  /* Configure USART parity and data bits */
66  if (parity == UPARITY_EVEN) {
67  usart_set_parity((uint32_t)p->reg_addr, USART_PARITY_EVEN);
68  if (bits == UBITS_7) {
69  usart_set_databits((uint32_t)p->reg_addr, 8);
70  } else { // 8 data bits by default
71  usart_set_databits((uint32_t)p->reg_addr, 9);
72  }
73  } else if (parity == UPARITY_ODD) {
74  usart_set_parity((uint32_t)p->reg_addr, USART_PARITY_ODD);
75  if (bits == UBITS_7) {
76  usart_set_databits((uint32_t)p->reg_addr, 8);
77  } else { // 8 data bits by default
78  usart_set_databits((uint32_t)p->reg_addr, 9);
79  }
80  } else { // 8 data bist, NO_PARITY by default
81  usart_set_parity((uint32_t)p->reg_addr, USART_PARITY_NONE);
82  usart_set_databits((uint32_t)p->reg_addr, 8); // is 7bits without parity possible ?
83  }
84  /* Configure USART stop bits */
85  if (stop == USTOP_2) {
86  usart_set_stopbits((uint32_t)p->reg_addr, USART_STOPBITS_2);
87  } else { // 1 stop bit by default
88  usart_set_stopbits((uint32_t)p->reg_addr, USART_STOPBITS_1);
89  }
90 }
91 
92 void uart_periph_set_mode(struct uart_periph *p, bool tx_enabled, bool rx_enabled, bool hw_flow_control)
93 {
94  uint32_t mode = 0;
95  if (tx_enabled) {
96  mode |= USART_MODE_TX;
97  }
98  if (rx_enabled) {
99  mode |= USART_MODE_RX;
100  }
101 
102  /* set mode to Tx, Rx or TxRx */
103  usart_set_mode((uint32_t)p->reg_addr, mode);
104 
105  if (hw_flow_control) {
106  usart_set_flow_control((uint32_t)p->reg_addr, USART_FLOWCONTROL_RTS_CTS);
107  } else {
108  usart_set_flow_control((uint32_t)p->reg_addr, USART_FLOWCONTROL_NONE);
109  }
110 }
111 
112 void uart_put_byte(struct uart_periph *p, long fd __attribute__((unused)), uint8_t data)
113 {
114 
115  uint16_t temp = (p->tx_insert_idx + 1) % UART_TX_BUFFER_SIZE;
116 
117  if (temp == p->tx_extract_idx) {
118  return; // no room
119  }
120 
121  USART_CR1((uint32_t)p->reg_addr) &= ~USART_CR1_TXEIE; // Disable TX interrupt
122 
123  // check if in process of sending data
124  if (p->tx_running) { // yes, add to queue
125  p->tx_buf[p->tx_insert_idx] = data;
126  p->tx_insert_idx = temp;
127  } else { // no, set running flag and write to output register
128  p->tx_running = true;
129  usart_send((uint32_t)p->reg_addr, data);
130  }
131 
132  USART_CR1((uint32_t)p->reg_addr) |= USART_CR1_TXEIE; // Enable TX interrupt
133 
134 }
135 
136 static inline void usart_isr(struct uart_periph *p)
137 {
138 
139  if (((USART_CR1((uint32_t)p->reg_addr) & USART_CR1_TXEIE) != 0) &&
140  ((USART_SR((uint32_t)p->reg_addr) & USART_SR_TXE) != 0)) {
141  // check if more data to send
142  if (p->tx_insert_idx != p->tx_extract_idx) {
143  usart_send((uint32_t)p->reg_addr, p->tx_buf[p->tx_extract_idx]);
144  p->tx_extract_idx++;
146  } else {
147  p->tx_running = false; // clear running flag
148  USART_CR1((uint32_t)p->reg_addr) &= ~USART_CR1_TXEIE; // Disable TX interrupt
149  }
150  }
151 
152  if (((USART_CR1((uint32_t)p->reg_addr) & USART_CR1_RXNEIE) != 0) &&
153  ((USART_SR((uint32_t)p->reg_addr) & USART_SR_RXNE) != 0) &&
154  ((USART_SR((uint32_t)p->reg_addr) & USART_SR_ORE) == 0) &&
155  ((USART_SR((uint32_t)p->reg_addr) & USART_SR_NE) == 0) &&
156  ((USART_SR((uint32_t)p->reg_addr) & USART_SR_FE) == 0)) {
157  uint16_t temp = (p->rx_insert_idx + 1) % UART_RX_BUFFER_SIZE;;
158  p->rx_buf[p->rx_insert_idx] = usart_recv((uint32_t)p->reg_addr);
159  // check for more room in queue
160  if (temp != p->rx_extract_idx) {
161  p->rx_insert_idx = temp; // update insert index
162  }
163  } else {
164  /* ORE, NE or FE error - read USART_DR reg and log the error */
165  if (((USART_CR1((uint32_t)p->reg_addr) & USART_CR1_RXNEIE) != 0) &&
166  ((USART_SR((uint32_t)p->reg_addr) & USART_SR_ORE) != 0)) {
167  usart_recv((uint32_t)p->reg_addr);
168  p->ore++;
169  }
170  if (((USART_CR1((uint32_t)p->reg_addr) & USART_CR1_RXNEIE) != 0) &&
171  ((USART_SR((uint32_t)p->reg_addr) & USART_SR_NE) != 0)) {
172  usart_recv((uint32_t)p->reg_addr);
173  p->ne_err++;
174  }
175  if (((USART_CR1((uint32_t)p->reg_addr) & USART_CR1_RXNEIE) != 0) &&
176  ((USART_SR((uint32_t)p->reg_addr) & USART_SR_FE) != 0)) {
177  usart_recv((uint32_t)p->reg_addr);
178  p->fe_err++;
179  }
180  }
181 }
182 
183 static inline void usart_enable_irq(uint8_t IRQn)
184 {
185  /* Note:
186  * In libstm32 times the priority of this interrupt was set to
187  * preemption priority 2 and sub priority 1
188  */
189  /* Enable USART interrupts */
190  nvic_enable_irq(IRQn);
191 }
192 
193 
194 #if USE_UART1
195 
196 /* by default enable UART Tx and Rx */
197 #ifndef USE_UART1_TX
198 #define USE_UART1_TX TRUE
199 #endif
200 #ifndef USE_UART1_RX
201 #define USE_UART1_RX TRUE
202 #endif
203 
204 #ifndef UART1_HW_FLOW_CONTROL
205 #define UART1_HW_FLOW_CONTROL FALSE
206 #endif
207 
208 #ifndef UART1_BITS
209 #define UART1_BITS UBITS_8
210 #endif
211 
212 #ifndef UART1_STOP
213 #define UART1_STOP USTOP_1
214 #endif
215 
216 #ifndef UART1_PARITY
217 #define UART1_PARITY UPARITY_NO
218 #endif
219 
220 void uart1_init(void)
221 {
222 
223  uart_periph_init(&uart1);
224  uart1.reg_addr = (void *)USART1;
225 
226  /* init RCC and GPIOs */
227  rcc_periph_clock_enable(RCC_USART1);
228 
229 #if USE_UART1_TX
231 #endif
232 #if USE_UART1_RX
234 #endif
235 
236  /* Enable USART interrupts in the interrupt controller */
237  usart_enable_irq(NVIC_USART1_IRQ);
238 
239 #if UART1_HW_FLOW_CONTROL
240 #warning "USING UART1 FLOW CONTROL. Make sure to pull down CTS if you are not connecting any flow-control-capable hardware."
241  /* setup CTS and RTS gpios */
242  gpio_setup_pin_af(UART1_GPIO_PORT_CTS, UART1_GPIO_CTS, UART1_GPIO_AF, FALSE);
243  gpio_setup_pin_af(UART1_GPIO_PORT_RTS, UART1_GPIO_RTS, UART1_GPIO_AF, TRUE);
244 #endif
245 
246  /* Configure USART1, enable hardware flow control*/
247  uart_periph_set_mode(&uart1, USE_UART1_TX, USE_UART1_RX, UART1_HW_FLOW_CONTROL);
248 
249  /* Set USART1 parameters and enable interrupt */
250  uart_periph_set_bits_stop_parity(&uart1, UART1_BITS, UART1_STOP, UART1_PARITY);
251  uart_periph_set_baudrate(&uart1, UART1_BAUD);
252 }
253 
254 void usart1_isr(void) { usart_isr(&uart1); }
255 
256 #endif /* USE_UART1 */
257 
258 
259 #if USE_UART2
260 
261 /* by default enable UART Tx and Rx */
262 #ifndef USE_UART2_TX
263 #define USE_UART2_TX TRUE
264 #endif
265 #ifndef USE_UART2_RX
266 #define USE_UART2_RX TRUE
267 #endif
268 
269 #ifndef UART2_HW_FLOW_CONTROL
270 #define UART2_HW_FLOW_CONTROL FALSE
271 #endif
272 
273 #ifndef UART2_BITS
274 #define UART2_BITS UBITS_8
275 #endif
276 
277 #ifndef UART2_STOP
278 #define UART2_STOP USTOP_1
279 #endif
280 
281 #ifndef UART2_PARITY
282 #define UART2_PARITY UPARITY_NO
283 #endif
284 
285 void uart2_init(void)
286 {
287 
288  uart_periph_init(&uart2);
289  uart2.reg_addr = (void *)USART2;
290 
291  /* init RCC and GPIOs */
292  rcc_periph_clock_enable(RCC_USART2);
293 
294 #if USE_UART2_TX
296 #endif
297 #if USE_UART2_RX
299 #endif
300 
301  /* Enable USART interrupts in the interrupt controller */
302  usart_enable_irq(NVIC_USART2_IRQ);
303 
304 #if UART2_HW_FLOW_CONTROL && defined(STM32F4)
305 #warning "USING UART2 FLOW CONTROL. Make sure to pull down CTS if you are not connecting any flow-control-capable hardware."
306  /* setup CTS and RTS pins */
309 #endif
310 
311  /* Configure USART Tx,Rx, and hardware flow control*/
313 
314  /* Configure USART */
315  uart_periph_set_bits_stop_parity(&uart2, UART2_BITS, UART2_STOP, UART2_PARITY);
316  uart_periph_set_baudrate(&uart2, UART2_BAUD);
317 }
318 
319 void usart2_isr(void) { usart_isr(&uart2); }
320 
321 #endif /* USE_UART2 */
322 
323 
324 #if USE_UART3
325 
326 /* by default enable UART Tx and Rx */
327 #ifndef USE_UART3_TX
328 #define USE_UART3_TX TRUE
329 #endif
330 #ifndef USE_UART3_RX
331 #define USE_UART3_RX TRUE
332 #endif
333 
334 #ifndef UART3_HW_FLOW_CONTROL
335 #define UART3_HW_FLOW_CONTROL FALSE
336 #endif
337 
338 #ifndef UART3_BITS
339 #define UART3_BITS UBITS_8
340 #endif
341 
342 #ifndef UART3_STOP
343 #define UART3_STOP USTOP_1
344 #endif
345 
346 #ifndef UART3_PARITY
347 #define UART3_PARITY UPARITY_NO
348 #endif
349 
350 void uart3_init(void)
351 {
352 
353  uart_periph_init(&uart3);
354  uart3.reg_addr = (void *)USART3;
355 
356  /* init RCC */
357  rcc_periph_clock_enable(RCC_USART3);
358 
359 #if USE_UART3_TX
361 #endif
362 #if USE_UART3_RX
364 #endif
365 
366  /* Enable USART interrupts in the interrupt controller */
367  usart_enable_irq(NVIC_USART3_IRQ);
368 
369 #if UART3_HW_FLOW_CONTROL && defined(STM32F4)
370 #warning "USING UART3 FLOW CONTROL. Make sure to pull down CTS if you are not connecting any flow-control-capable hardware."
371  /* setup CTS and RTS pins */
374 #endif
375 
376  /* Configure USART Tx,Rx, and hardware flow control*/
377  uart_periph_set_mode(&uart3, USE_UART3_TX, USE_UART3_RX, UART3_HW_FLOW_CONTROL);
378 
379  /* Configure USART */
380  uart_periph_set_bits_stop_parity(&uart3, UART3_BITS, UART3_STOP, UART3_PARITY);
381  uart_periph_set_baudrate(&uart3, UART3_BAUD);
382 }
383 
384 void usart3_isr(void) { usart_isr(&uart3); }
385 
386 #endif /* USE_UART3 */
387 
388 
389 #if USE_UART4
390 
391 /* by default enable UART Tx and Rx */
392 #ifndef USE_UART4_TX
393 #define USE_UART4_TX TRUE
394 #endif
395 #ifndef USE_UART4_RX
396 #define USE_UART4_RX TRUE
397 #endif
398 
399 #ifndef UART4_BITS
400 #define UART4_BITS UBITS_8
401 #endif
402 
403 #ifndef UART4_STOP
404 #define UART4_STOP USTOP_1
405 #endif
406 
407 #ifndef UART4_PARITY
408 #define UART4_PARITY UPARITY_NO
409 #endif
410 
411 void uart4_init(void)
412 {
413 
414  uart_periph_init(&uart4);
415  uart4.reg_addr = (void *)UART4;
416 
417  /* init RCC and GPIOs */
418  rcc_periph_clock_enable(RCC_UART4);
419 
420 #if USE_UART4_TX
422 #endif
423 #if USE_UART4_RX
425 #endif
426 
427  /* Enable USART interrupts in the interrupt controller */
428  usart_enable_irq(NVIC_UART4_IRQ);
429 
430  /* Configure USART */
432  uart_periph_set_bits_stop_parity(&uart4, UART4_BITS, UART4_STOP, UART4_PARITY);
433  uart_periph_set_baudrate(&uart4, UART4_BAUD);
434 }
435 
436 void uart4_isr(void) { usart_isr(&uart4); }
437 
438 #endif /* USE_UART4 */
439 
440 
441 #if USE_UART5
442 
443 /* by default enable UART Tx and Rx */
444 #ifndef USE_UART5_TX
445 #define USE_UART5_TX TRUE
446 #endif
447 #ifndef USE_UART5_RX
448 #define USE_UART5_RX TRUE
449 #endif
450 
451 #ifndef UART5_BITS
452 #define UART5_BITS UBITS_8
453 #endif
454 
455 #ifndef UART5_STOP
456 #define UART5_STOP USTOP_1
457 #endif
458 
459 #ifndef UART5_PARITY
460 #define UART5_PARITY UPARITY_NO
461 #endif
462 
463 void uart5_init(void)
464 {
465 
466  uart_periph_init(&uart5);
467  uart5.reg_addr = (void *)UART5;
468 
469  /* init RCC and GPIOs */
470  rcc_periph_clock_enable(RCC_UART5);
471 
472 #if USE_UART5_TX
474 #endif
475 #if USE_UART5_RX
477 #endif
478 
479  /* Enable USART interrupts in the interrupt controller */
480  usart_enable_irq(NVIC_UART5_IRQ);
481 
482  /* Configure USART */
483  uart_periph_set_mode(&uart5, USE_UART5_TX, USE_UART5_RX, FALSE);
484  uart_periph_set_bits_stop_parity(&uart5, UART5_BITS, UART5_STOP, UART5_PARITY);
485  uart_periph_set_baudrate(&uart5, UART5_BAUD);
486 }
487 
488 void uart5_isr(void) { usart_isr(&uart5); }
489 
490 #endif /* USE_UART5 */
491 
492 
493 #if USE_UART6 && defined STM32F4
494 
495 /* by default enable UART Tx and Rx */
496 #ifndef USE_UART6_TX
497 #define USE_UART6_TX TRUE
498 #endif
499 #ifndef USE_UART6_RX
500 #define USE_UART6_RX TRUE
501 #endif
502 
503 #ifndef UART6_HW_FLOW_CONTROL
504 #define UART6_HW_FLOW_CONTROL FALSE
505 #endif
506 
507 #ifndef UART6_BITS
508 #define UART6_BITS UBITS_8
509 #endif
510 
511 #ifndef UART6_STOP
512 #define UART6_STOP USTOP_1
513 #endif
514 
515 #ifndef UART6_PARITY
516 #define UART6_PARITY UPARITY_NO
517 #endif
518 
519 void uart6_init(void)
520 {
521 
522  uart_periph_init(&uart6);
523  uart6.reg_addr = (void *)USART6;
524 
525  /* enable uart clock */
526  rcc_periph_clock_enable(RCC_USART6);
527 
528  /* init RCC and GPIOs */
529 #if USE_UART6_TX
531 #endif
532 #if USE_UART6_RX
534 #endif
535 
536  /* Enable USART interrupts in the interrupt controller */
537  usart_enable_irq(NVIC_USART6_IRQ);
538 
539 #if UART6_HW_FLOW_CONTROL
540 #warning "USING UART6 FLOW CONTROL. Make sure to pull down CTS if you are not connecting any flow-control-capable hardware."
541  /* setup CTS and RTS pins */
542  gpio_setup_pin_af(UART6_GPIO_PORT_CTS, UART6_GPIO_CTS, UART6_GPIO_AF, FALSE);
543  gpio_setup_pin_af(UART6_GPIO_PORT_RTS, UART6_GPIO_RTS, UART6_GPIO_AF, TRUE);
544 #endif
545 
546  /* Configure USART Tx,Rx and hardware flow control*/
547  uart_periph_set_mode(&uart6, USE_UART6_TX, USE_UART6_RX, UART6_HW_FLOW_CONTROL);
548  uart_periph_set_bits_stop_parity(&uart6, UART6_BITS, UART6_STOP, UART6_PARITY);
549  uart_periph_set_baudrate(&uart6, UART6_BAUD);
550 }
551 
552 void usart6_isr(void) { usart_isr(&uart6); }
553 
554 #endif /* USE_UART6 */
555 
556 
557 #if USE_UART7
558 
559 /* by default enable UART Tx and Rx */
560 #ifndef USE_UART7_TX
561 #define USE_UART7_TX TRUE
562 #endif
563 #ifndef USE_UART7_RX
564 #define USE_UART7_RX TRUE
565 #endif
566 
567 #ifndef UART7_BITS
568 #define UART7_BITS UBITS_8
569 #endif
570 
571 #ifndef UART7_STOP
572 #define UART7_STOP USTOP_1
573 #endif
574 
575 #ifndef UART7_PARITY
576 #define UART7_PARITY UPARITY_NO
577 #endif
578 
579 void uart7_init(void)
580 {
581 
582  uart_periph_init(&uart7);
583  uart7.reg_addr = (void *)UART7;
584 
585  /* init RCC and GPIOs */
586  rcc_periph_clock_enable(RCC_UART7);
587 
588 #if USE_UART7_TX
590 #endif
591 #if USE_UART7_RX
593 #endif
594 
595  /* Enable USART interrupts in the interrupt controller */
596  usart_enable_irq(NVIC_UART7_IRQ);
597 
598  /* Configure USART */
600  uart_periph_set_bits_stop_parity(&uart7, UART7_BITS, UART7_STOP, UART7_PARITY);
601  uart_periph_set_baudrate(&uart7, UART7_BAUD);
602 }
603 
604 void uart7_isr(void) { usart_isr(&uart7); }
605 
606 #endif /* USE_UART7 */
607 
608 
609 #if USE_UART8
610 
611 /* by default enable UART Tx and Rx */
612 #ifndef USE_UART8_TX
613 #define USE_UART8_TX TRUE
614 #endif
615 #ifndef USE_UART8_RX
616 #define USE_UART8_RX TRUE
617 #endif
618 
619 #ifndef UART8_BITS
620 #define UART8_BITS UBITS_8
621 #endif
622 
623 #ifndef UART8_STOP
624 #define UART8_STOP USTOP_1
625 #endif
626 
627 #ifndef UART8_PARITY
628 #define UART8_PARITY UPARITY_NO
629 #endif
630 
631 void uart8_init(void)
632 {
633 
634  uart_periph_init(&uart8);
635  uart8.reg_addr = (void *)UART8;
636 
637  /* init RCC and GPIOs */
638  rcc_periph_clock_enable(RCC_UART8);
639 
640 #if USE_UART8_TX
642 #endif
643 #if USE_UART8_RX
645 #endif
646 
647  /* Enable USART interrupts in the interrupt controller */
648  usart_enable_irq(NVIC_UART8_IRQ);
649 
650  /* Configure USART */
652  uart_periph_set_bits_stop_parity(&uart8, UART8_BITS, UART8_STOP, UART8_PARITY);
653  uart_periph_set_baudrate(&uart8, UART8_BAUD);
654 }
655 
656 void uart8_isr(void) { usart_isr(&uart8); }
657 
658 #endif /* USE_UART8 */
void gpio_setup_pin_af(ioportid_t port, uint16_t pin, uint8_t af, bool is_output)
Setup a gpio for input or output with alternate function.
Definition: gpio_arch.c:61
uint8_t tx_buf[UART_TX_BUFFER_SIZE]
Transmit buffer.
Definition: uart.h:76
unsigned short uint16_t
Definition: types.h:16
uint8_t rx_buf[UART_RX_BUFFER_SIZE]
Receive buffer.
Definition: uart.h:72
arch independent UART (Universal Asynchronous Receiver/Transmitter) API
#define UPARITY_EVEN
Definition: serial_port.c:57
void uart_periph_set_baudrate(struct uart_periph *p, uint32_t baud)
Set baudrate.
Definition: uart_arch.c:861
volatile uint8_t tx_running
Definition: uart.h:79
#define UART2_GPIO_CTS
Definition: px4fmu_4.0.h:67
#define UART5_GPIO_RX
Definition: elle0_common.h:113
#define UART6_GPIO_AF
Definition: apogee_1.0.h:129
#define UART2_GPIO_RTS
Definition: px4fmu_4.0.h:69
Some architecture independent helper functions for GPIOs.
#define UART2_GPIO_PORT_TX
UART2 (with optional flow control activated by default)
Definition: chimera.h:376
#define UART3_GPIO_PORT_RTS
Definition: px4fmu_4.0.h:79
#define UART3_GPIO_PORT_CTS
Definition: px4fmu_4.0.h:77
#define UART4_GPIO_AF
Definition: apogee_1.0.h:123
#define UART2_GPIO_RX
Definition: apogee_1.0.h:120
#define UART_RX_BUFFER_SIZE
Definition: uart_arch.h:31
#define UART5_GPIO_TX
Definition: elle0_common.h:115
static void usart_isr(struct uart_periph *p)
Definition: uart_arch.c:136
#define UART8_GPIO_RX
Definition: chimera.h:405
#define USE_UART4_RX
Definition: chimera.h:429
#define UART3_GPIO_TX
Definition: cc3d.h:52
#define USE_UART2_TX
Definition: apogee_1.0.h:121
#define USE_UART7_TX
Definition: chimera.h:423
void uart_periph_set_mode(struct uart_periph *p, bool tx_enabled, bool rx_enabled, bool hw_flow_control)
Set mode (not necessary, or can be set by SerialConfig)
Definition: uart_arch.c:876
#define USE_UART4_TX
Definition: chimera.h:430
void * reg_addr
UART Register.
Definition: uart.h:81
#define FALSE
Definition: std.h:5
#define USTOP_2
Definition: serial_port.c:53
#define UART8_GPIO_AF
Definition: chimera.h:406
#define USE_UART6_RX
Definition: tawaki.h:477
#define TRUE
Definition: std.h:4
#define UART7_GPIO_TX
Definition: px4fmu.h:264
#define UART5_GPIO_AF
Definition: elle0_common.h:111
#define UART3_GPIO_PORT_RX
Definition: cc3d.h:49
uint16_t rx_insert_idx
Definition: uart.h:73
#define UART2_HW_FLOW_CONTROL
Definition: chimera.h:382
#define UART7_GPIO_AF
Definition: chimera.h:427
#define UART5_GPIO_PORT_TX
Definition: elle0_common.h:114
#define UART8_GPIO_PORT_RX
Definition: chimera.h:404
#define UART1_GPIO_RX
Definition: apogee_1.0.h:114
UART peripheral.
Definition: uart.h:70
#define UBITS_7
Definition: serial_port.c:49
#define UART7_GPIO_PORT_RX
Definition: chimera.h:425
#define UART6_GPIO_PORT_TX
Definition: apogee_1.0.h:132
void uart_periph_init(struct uart_periph *p)
Definition: uart.c:231
unsigned long uint32_t
Definition: types.h:18
#define UART3_GPIO_AF
Definition: cc3d.h:48
#define UART4_GPIO_PORT_RX
Definition: apogee_1.0.h:124
#define UART7_GPIO_RX
Definition: chimera.h:426
#define UART8_GPIO_PORT_TX
Definition: chimera.h:402
#define UPARITY_ODD
Definition: serial_port.c:56
#define UART3_GPIO_CTS
Definition: px4fmu_4.0.h:78
#define UART1_GPIO_TX
Definition: apogee_1.0.h:116
uint16_t rx_extract_idx
Definition: uart.h:74
#define UART6_GPIO_PORT_RX
Definition: apogee_1.0.h:130
volatile uint16_t ne_err
noise error counter
Definition: uart.h:89
volatile uint16_t fe_err
framing error counter
Definition: uart.h:90
#define USE_UART7_RX
SBUS / Spektrum port.
Definition: chimera.h:421
uint16_t tx_insert_idx
Definition: uart.h:77
void uart_put_byte(struct uart_periph *p, long fd, uint8_t data)
Uart transmit implementation.
Definition: uart_arch.c:972
#define UART2_GPIO_PORT_CTS
Definition: px4fmu_4.0.h:66
#define UART1_GPIO_PORT_RX
Definition: apogee_1.0.h:113
#define UART6_GPIO_RX
Definition: apogee_1.0.h:131
#define UART5_GPIO_PORT_RX
Definition: elle0_common.h:112
#define UART8_GPIO_TX
Definition: chimera.h:403
unsigned char uint8_t
Definition: types.h:14
#define UART4_GPIO_RX
Definition: apogee_1.0.h:125
void uart_periph_set_bits_stop_parity(struct uart_periph *p, uint8_t bits, uint8_t stop, uint8_t parity)
Set parity and stop bits.
Definition: uart_arch.c:890
#define UART2_GPIO_TX
Definition: chimera.h:377
#define UART2_GPIO_PORT_RX
Definition: apogee_1.0.h:119
static uint8_t mode
mode holds the current sonar mode mode = 0 used at high altitude, uses 16 wave patterns mode = 1 used...
Definition: sonar_bebop.c:69
#define UART4_GPIO_PORT_TX
Definition: apogee_1.0.h:126
int fd
Definition: serial.c:26
#define UART3_GPIO_RTS
Definition: px4fmu_4.0.h:80
#define UART3_GPIO_PORT_TX
Definition: cc3d.h:51
#define USE_UART8_RX
SBUS / Spektrum port.
Definition: tawaki.h:468
#define UART2_GPIO_AF
Definition: apogee_1.0.h:118
int baudrate
UART Baudrate.
Definition: uart.h:83
#define UART_TX_BUFFER_SIZE
Definition: uart_arch.h:34
static float p[2][2]
#define UART3_GPIO_RX
Definition: cc3d.h:50
#define UART1_GPIO_PORT_TX
Definition: apogee_1.0.h:115
volatile uint16_t ore
overrun error counter
Definition: uart.h:88
#define USE_UART8_TX
Definition: tawaki.h:470
#define USE_UART6_TX
Definition: tawaki.h:478
#define UART1_GPIO_AF
Definition: apogee_1.0.h:112
#define UART6_GPIO_TX
Definition: apogee_1.0.h:133
#define UART4_GPIO_TX
Definition: apogee_1.0.h:127
#define UART2_GPIO_PORT_RTS
Definition: px4fmu_4.0.h:68
#define UART7_GPIO_PORT_TX
Definition: px4fmu.h:263
uint16_t tx_extract_idx
Definition: uart.h:78
static void usart_enable_irq(uint8_t IRQn)
Definition: uart_arch.c:183