Paparazzi UAS v7.0_unstable
Paparazzi is a free software Unmanned Aircraft System.
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uart_arch.c
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1/*
2 * Copyright (C) 2013 AggieAir, A Remote Sensing Unmanned Aerial System for Scientific Applications
3 * Utah State University, http://aggieair.usu.edu/
4 *
5 * Michal Podhradsky (michal.podhradsky@aggiemail.usu.edu)
6 * Calvin Coopmans (c.r.coopmans@ieee.org)
7 *
8 * Alexandre Bustico <alexandre.bustico@enac.fr>
9 * Gautier Hattenberger <gautier.hattenberger@enac.fr>
10 *
11 * This file is part of paparazzi.
12 *
13 * paparazzi is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
16 * any later version.
17 *
18 * paparazzi is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with paparazzi; see the file COPYING. If not, write to
25 * the Free Software Foundation, 59 Temple Place - Suite 330,
26 * Boston, MA 02111-1307, USA.
27 */
37#include "mcu_periph/uart_arch.h"
38#include <ch.h>
39#include <hal.h>
40#include "mcu_periph/gpio.h"
41#include BOARD_CONFIG
42
43#if HAL_USE_SERIAL
44
45// Default stack size
46#ifndef UART_THREAD_STACK_SIZE
47#define UART_THREAD_STACK_SIZE 512
48#endif
49
50struct SerialInit {
51 SerialConfig *conf;
52 semaphore_t *rx_sem;
53 semaphore_t *tx_sem;
54 mutex_t *rx_mtx;
55 mutex_t *tx_mtx;
56 ioportid_t cts_port;
57 uint16_t cts_pin;
58};
59
60#define SERIAL_INIT_NULL { NULL, NULL, NULL, NULL, NULL, 0, 0 }
61
65UNUSED static void handle_uart_rx(struct uart_periph *p)
66{
67 // wait for next incoming byte
68 uint8_t c = sdGet((SerialDriver *)(p->reg_addr));
69
70 struct SerialInit *init_struct = (struct SerialInit *)(p->init_struct);
71 chMtxLock(init_struct->rx_mtx);
72 uint16_t temp = (p->rx_insert_idx + 1) % UART_RX_BUFFER_SIZE;;
73 // insert new byte
74 p->rx_buf[p->rx_insert_idx] = c;
75 // check for more room in queue
76 if (temp != p->rx_extract_idx) {
77 p->rx_insert_idx = temp; // update insert index
78 }
79 chMtxUnlock(init_struct->rx_mtx);
80 chSemSignal(init_struct->rx_sem);
81}
82
86UNUSED static void handle_uart_tx(struct uart_periph *p)
87{
88 // check if more data to send
89 // send by block with sdWrite if possible: not compatible with soft flow control
90 struct SerialInit *init_struct = (struct SerialInit *)(p->init_struct);
91 chSemWait(init_struct->tx_sem);
92 p->tx_running = true;
93 while (p->tx_insert_idx != p->tx_extract_idx) {
94#if USE_UART_SOFT_FLOW_CONTROL
95 if (init_struct->cts_port != 0) {
96 // wait for CTS line to be set to send next byte
97 while (gpio_get(init_struct->cts_port, init_struct->cts_pin) == 1) ;
98 }
99 uint8_t data = p->tx_buf[p->tx_extract_idx];
100 sdPut((SerialDriver *)p->reg_addr, data);
101 chMtxLock(init_struct->tx_mtx);
102 p->tx_extract_idx++;
103 p->tx_extract_idx %= UART_TX_BUFFER_SIZE;
104 chMtxUnlock(init_struct->tx_mtx);
105 if (init_struct->cts_port != 0) {
106 // wait for physical transfer to be completed
107 while ((((SerialDriver *)p->reg_addr)->usart->SR & USART_SR_TC) == 0) ;
108 }
109#else // normal operation without soft flow control
110 chMtxLock(init_struct->tx_mtx);
111 if (p->tx_insert_idx > p->tx_extract_idx) {
112 sdWrite((SerialDriver *)p->reg_addr, &p->tx_buf[p->tx_extract_idx], p->tx_insert_idx - p->tx_extract_idx);
113 } else {
114 // wrapping circular buffer
115 sdWrite((SerialDriver *)p->reg_addr, &p->tx_buf[p->tx_extract_idx], UART_TX_BUFFER_SIZE - p->tx_extract_idx);
116 if(p->tx_insert_idx > 0) {
117 sdWrite((SerialDriver *)p->reg_addr, &p->tx_buf[0], p->tx_insert_idx);
118 }
119 }
120 p->tx_extract_idx = p->tx_insert_idx;
121 chMtxUnlock(init_struct->tx_mtx);
122#endif
123 }
124 p->tx_running = false;
125}
126
127#if USE_UART1
128
129#ifndef UART1_BAUD
130#define UART1_BAUD SERIAL_DEFAULT_BITRATE
131#endif
132
133/* by default enable UART Tx and Rx */
134#ifndef USE_UART1_TX
135#define USE_UART1_TX TRUE
136#endif
137#ifndef USE_UART1_RX
138#define USE_UART1_RX TRUE
139#endif
140
141#ifndef UART1_CR1
142#define UART1_CR1 0
143#endif
144
145#ifndef UART1_CR2
146#define UART1_CR2 USART_CR2_STOP1_BITS
147#endif
148
149#ifndef UART1_CR3
150#define UART1_CR3 0
151#endif
152
153static SerialConfig usart1_config = {
154 UART1_BAUD, /* BITRATE */
155 UART1_CR1, /* USART CR1 */
156 UART1_CR2, /* USART CR2 */
157 UART1_CR3 /* USART CR3 */
158};
159
160static struct SerialInit uart1_init_struct = SERIAL_INIT_NULL;
161
162// Threads RX and TX
163#if USE_UART1_RX
164static MUTEX_DECL(uart1_rx_mtx);
165static SEMAPHORE_DECL(uart1_rx_sem, 0);
166
167static __attribute__((noreturn)) void thd_uart1_rx(void *arg)
168{
169 (void) arg;
170 chRegSetThreadName("uart1_rx");
171
172 while (TRUE) {
173 handle_uart_rx(&uart1);
174 }
175}
176
177static THD_WORKING_AREA(wa_thd_uart1_rx, UART_THREAD_STACK_SIZE);
178#endif
179
180#if USE_UART1_TX
181static MUTEX_DECL(uart1_tx_mtx);
182static SEMAPHORE_DECL(uart1_tx_sem, 0);
183
184static __attribute__((noreturn)) void thd_uart1_tx(void *arg)
185{
186 (void) arg;
187 chRegSetThreadName("uart1_tx");
188
189 while (TRUE) {
190 handle_uart_tx(&uart1);
191 }
192}
193static THD_WORKING_AREA(wa_thd_uart1_tx, UART_THREAD_STACK_SIZE);
194#endif
195
196void uart1_init(void)
197{
198 uart_periph_init(&uart1);
199
200 // Only set pin if enabled and not statically defined in board file
201#if USE_UART1_TX && defined UART1_GPIO_PORT_TX
202 gpio_setup_pin_af(UART1_GPIO_PORT_TX, UART1_GPIO_TX, UART1_GPIO_AF, TRUE);
203#endif
204#if USE_UART1_RX && defined UART1_GPIO_PORT_RX
205 gpio_setup_pin_af(UART1_GPIO_PORT_RX, UART1_GPIO_RX, UART1_GPIO_AF, FALSE);
206#endif
207
208 sdStart(&SD1, &usart1_config);
209 uart1.reg_addr = &SD1;
210 uart1.baudrate = UART1_BAUD;
211 uart1.init_struct = &uart1_init_struct;
212 uart1_init_struct.conf = &usart1_config;
213
214 // Create threads
215#if USE_UART1_RX
216 uart1_init_struct.rx_mtx = &uart1_rx_mtx;
217 uart1_init_struct.rx_sem = &uart1_rx_sem;
218 chThdCreateStatic(wa_thd_uart1_rx, sizeof(wa_thd_uart1_rx),
219 NORMALPRIO + 1, thd_uart1_rx, NULL);
220#endif
221#if USE_UART1_TX
222 uart1_init_struct.tx_mtx = &uart1_tx_mtx;
223 uart1_init_struct.tx_sem = &uart1_tx_sem;
224 chThdCreateStatic(wa_thd_uart1_tx, sizeof(wa_thd_uart1_tx),
225 NORMALPRIO + 1, thd_uart1_tx, NULL);
226#endif
227}
228
229#endif
230
231
232#if USE_UART2
233
234#ifndef UART2_BAUD
235#define UART2_BAUD SERIAL_DEFAULT_BITRATE
236#endif
237
238/* by default enable UART Tx and Rx */
239#ifndef USE_UART2_TX
240#define USE_UART2_TX TRUE
241#endif
242#ifndef USE_UART2_RX
243#define USE_UART2_RX TRUE
244#endif
245
246
247/* by default disable HW flow control */
248#ifndef UART2_HW_FLOW_CONTROL
249#define UART2_HW_FLOW_CONTROL FALSE
250#endif
251
252#if UART2_HW_FLOW_CONTROL && defined(UART2_CR3)
253#warning "UART2_CR3 reset to your value, HW flow control not enabled! You may want to set USART_CR3_CTSE | USART_CR3_RTSE yourself."
254#endif
255
256#ifndef UART2_CR1
257#define UART2_CR1 0
258#endif
259
260#ifndef UART2_CR2
261#define UART2_CR2 USART_CR2_STOP1_BITS
262#endif
263
264#ifndef UART2_CR3
265#if UART2_HW_FLOW_CONTROL
266#define UART2_CR3 USART_CR3_CTSE | USART_CR3_RTSE
267#else
268#define UART2_CR3 0
269#endif
270#endif
271
272static SerialConfig usart2_config = {
273 UART2_BAUD, /* BITRATE */
274 UART2_CR1, /* USART CR1 */
275 UART2_CR2, /* USART CR2 */
276 UART2_CR3 /* USART CR3 */
277};
278
279static struct SerialInit uart2_init_struct = SERIAL_INIT_NULL;
280
281// Threads RX and TX
282#if USE_UART2_RX
283static MUTEX_DECL(uart2_rx_mtx);
284static SEMAPHORE_DECL(uart2_rx_sem, 0);
285
286static __attribute__((noreturn)) void thd_uart2_rx(void *arg)
287{
288 (void) arg;
289 chRegSetThreadName("uart2_rx");
290
291 while (TRUE) {
292 handle_uart_rx(&uart2);
293 }
294}
295
296static THD_WORKING_AREA(wa_thd_uart2_rx, UART_THREAD_STACK_SIZE);
297#endif
298
299#if USE_UART2_TX
300static MUTEX_DECL(uart2_tx_mtx);
301static SEMAPHORE_DECL(uart2_tx_sem, 0);
302
303static __attribute__((noreturn)) void thd_uart2_tx(void *arg)
304{
305 (void) arg;
306 chRegSetThreadName("uart2_tx");
307
308 while (TRUE) {
309 handle_uart_tx(&uart2);
310 }
311}
312static THD_WORKING_AREA(wa_thd_uart2_tx, UART_THREAD_STACK_SIZE);
313#endif
314
315void uart2_init(void)
316{
317 uart_periph_init(&uart2);
318
319 // Only set pin if enabled and not statically defined in board file
320#if USE_UART2_TX && defined UART2_GPIO_PORT_TX
321 gpio_setup_pin_af(UART2_GPIO_PORT_TX, UART2_GPIO_TX, UART2_GPIO_AF, TRUE);
322#endif
323#if USE_UART2_RX && defined UART2_GPIO_PORT_RX
324 gpio_setup_pin_af(UART2_GPIO_PORT_RX, UART2_GPIO_RX, UART2_GPIO_AF, FALSE);
325#endif
326
327 sdStart(&SD2, &usart2_config);
328 uart2.reg_addr = &SD2;
329 uart2.baudrate = UART2_BAUD;
330 uart2.init_struct = &uart2_init_struct;
331 uart2_init_struct.conf = &usart2_config;
332
333 // Create threads
334#if USE_UART2_RX
335 uart2_init_struct.rx_mtx = &uart2_rx_mtx;
336 uart2_init_struct.rx_sem = &uart2_rx_sem;
337 chThdCreateStatic(wa_thd_uart2_rx, sizeof(wa_thd_uart2_rx),
338 NORMALPRIO + 1, thd_uart2_rx, NULL);
339#endif
340#if USE_UART2_TX
341 uart2_init_struct.tx_mtx = &uart2_tx_mtx;
342 uart2_init_struct.tx_sem = &uart2_tx_sem;
343 chThdCreateStatic(wa_thd_uart2_tx, sizeof(wa_thd_uart2_tx),
344 NORMALPRIO + 1, thd_uart2_tx, NULL);
345#endif
346}
347
348#endif
349
350#if USE_UART3
351
352#ifndef UART3_BAUD
353#define UART3_BAUD SERIAL_DEFAULT_BITRATE
354#endif
355
356/* by default enable UART Tx and Rx */
357#ifndef USE_UART3_TX
358#define USE_UART3_TX TRUE
359#endif
360#ifndef USE_UART3_RX
361#define USE_UART3_RX TRUE
362#endif
363
364#ifndef UART3_CR1
365#define UART3_CR1 0
366#endif
367
368#ifndef UART3_CR2
369#define UART3_CR2 USART_CR2_STOP1_BITS
370#endif
371
372#ifndef UART3_CR3
373#define UART3_CR3 0
374#endif
375
376static SerialConfig usart3_config = {
377 UART3_BAUD, /* BITRATE */
378 UART3_CR1, /* USART CR1 */
379 UART3_CR2, /* USART CR2 */
380 UART3_CR3 /* USART CR3 */
381};
382
383static struct SerialInit uart3_init_struct = SERIAL_INIT_NULL;
384
385// Threads RX and TX
386#if USE_UART3_RX
387static MUTEX_DECL(uart3_rx_mtx);
388static SEMAPHORE_DECL(uart3_rx_sem, 0);
389
390static __attribute__((noreturn)) void thd_uart3_rx(void *arg)
391{
392 (void) arg;
393 chRegSetThreadName("uart3_rx");
394
395 while (TRUE) {
396 handle_uart_rx(&uart3);
397 }
398}
399
400static THD_WORKING_AREA(wa_thd_uart3_rx, UART_THREAD_STACK_SIZE);
401#endif
402
403#if USE_UART3_TX
404static MUTEX_DECL(uart3_tx_mtx);
405static SEMAPHORE_DECL(uart3_tx_sem, 0);
406
407static __attribute__((noreturn)) void thd_uart3_tx(void *arg)
408{
409 (void) arg;
410 chRegSetThreadName("uart3_tx");
411
412 while (TRUE) {
413 handle_uart_tx(&uart3);
414 }
415}
416static THD_WORKING_AREA(wa_thd_uart3_tx, UART_THREAD_STACK_SIZE);
417#endif
418
419void uart3_init(void)
420{
421 uart_periph_init(&uart3);
422
423 // Only set pin if enabled and not statically defined in board file
424#if USE_UART3_TX && defined UART3_GPIO_PORT_TX
425 gpio_setup_pin_af(UART3_GPIO_PORT_TX, UART3_GPIO_TX, UART3_GPIO_AF, TRUE);
426#endif
427#if USE_UART3_RX && defined UART3_GPIO_PORT_RX
428 gpio_setup_pin_af(UART3_GPIO_PORT_RX, UART3_GPIO_RX, UART3_GPIO_AF, FALSE);
429#endif
430
431 sdStart(&SD3, &usart3_config);
432 uart3.reg_addr = &SD3;
433 uart3.baudrate = UART3_BAUD;
434 uart3.init_struct = &uart3_init_struct;
435 uart3_init_struct.conf = &usart3_config;
436
437 // Create threads
438#if USE_UART3_RX
439 uart3_init_struct.rx_mtx = &uart3_rx_mtx;
440 uart3_init_struct.rx_sem = &uart3_rx_sem;
441 chThdCreateStatic(wa_thd_uart3_rx, sizeof(wa_thd_uart3_rx),
442 NORMALPRIO + 1, thd_uart3_rx, NULL);
443#endif
444#if USE_UART3_TX
445 uart3_init_struct.tx_mtx = &uart3_tx_mtx;
446 uart3_init_struct.tx_sem = &uart3_tx_sem;
447 chThdCreateStatic(wa_thd_uart3_tx, sizeof(wa_thd_uart3_tx),
448 NORMALPRIO + 1, thd_uart3_tx, NULL);
449#endif
450}
451
452#endif
453
454#if USE_UART4
455
456#ifndef UART4_BAUD
457#define UART4_BAUD SERIAL_DEFAULT_BITRATE
458#endif
459
460/* by default enable UART Tx and Rx */
461#ifndef USE_UART4_TX
462#define USE_UART4_TX TRUE
463#endif
464#ifndef USE_UART4_RX
465#define USE_UART4_RX TRUE
466#endif
467
468#ifndef UART4_CR1
469#define UART4_CR1 0
470#endif
471
472#ifndef UART4_CR2
473#define UART4_CR2 USART_CR2_STOP1_BITS
474#endif
475
476#ifndef UART4_CR3
477#define UART4_CR3 0
478#endif
479
480static SerialConfig usart4_config = {
481 UART4_BAUD, /* BITRATE */
482 UART4_CR1, /* USART CR1 */
483 UART4_CR2, /* USART CR2 */
484 UART4_CR3 /* USART CR3 */
485};
486
487static struct SerialInit uart4_init_struct = SERIAL_INIT_NULL;
488
489// Threads RX and TX
490#if USE_UART4_RX
491static MUTEX_DECL(uart4_rx_mtx);
492static SEMAPHORE_DECL(uart4_rx_sem, 0);
493
494static __attribute__((noreturn)) void thd_uart4_rx(void *arg)
495{
496 (void) arg;
497 chRegSetThreadName("uart4_rx");
498
499 while (TRUE) {
500 handle_uart_rx(&uart4);
501 }
502}
503
504static THD_WORKING_AREA(wa_thd_uart4_rx, UART_THREAD_STACK_SIZE);
505#endif
506
507#if USE_UART4_TX
508static MUTEX_DECL(uart4_tx_mtx);
509static SEMAPHORE_DECL(uart4_tx_sem, 0);
510
511static __attribute__((noreturn)) void thd_uart4_tx(void *arg)
512{
513 (void) arg;
514 chRegSetThreadName("uart4_tx");
515
516 while (TRUE) {
517 handle_uart_tx(&uart4);
518 }
519}
520static THD_WORKING_AREA(wa_thd_uart4_tx, UART_THREAD_STACK_SIZE);
521#endif
522
523void uart4_init(void)
524{
525 uart_periph_init(&uart4);
526
527 // Only set pin if enabled and not statically defined in board file
528#if USE_UART4_TX && defined UART4_GPIO_PORT_TX
529 gpio_setup_pin_af(UART4_GPIO_PORT_TX, UART4_GPIO_TX, UART4_GPIO_AF, TRUE);
530#endif
531#if USE_UART4_RX && defined UART4_GPIO_PORT_RX
532 gpio_setup_pin_af(UART4_GPIO_PORT_RX, UART4_GPIO_RX, UART4_GPIO_AF, FALSE);
533#endif
534
535 sdStart(&SD4, &usart4_config);
536 uart4.reg_addr = &SD4;
537 uart4.baudrate = UART4_BAUD;
538 uart4.init_struct = &uart4_init_struct;
539 uart4_init_struct.conf = &usart4_config;
540
541 // Create threads
542#if USE_UART4_RX
543 uart4_init_struct.rx_mtx = &uart4_rx_mtx;
544 uart4_init_struct.rx_sem = &uart4_rx_sem;
545 chThdCreateStatic(wa_thd_uart4_rx, sizeof(wa_thd_uart4_rx),
546 NORMALPRIO + 1, thd_uart4_rx, NULL);
547#endif
548#if USE_UART4_TX
549 uart4_init_struct.tx_mtx = &uart4_tx_mtx;
550 uart4_init_struct.tx_sem = &uart4_tx_sem;
551 chThdCreateStatic(wa_thd_uart4_tx, sizeof(wa_thd_uart4_tx),
552 NORMALPRIO + 1, thd_uart4_tx, NULL);
553#endif
554}
555
556#endif
557
558#if USE_UART5
559
560#ifndef UART5_BAUD
561#define UART5_BAUD SERIAL_DEFAULT_BITRATE
562#endif
563
564/* by default enable UART Tx and Rx */
565#ifndef USE_UART5_TX
566#define USE_UART5_TX TRUE
567#endif
568#ifndef USE_UART5_RX
569#define USE_UART5_RX TRUE
570#endif
571
572#ifndef UART5_CR1
573#define UART5_CR1 0
574#endif
575
576#ifndef UART5_CR2
577#define UART5_CR2 USART_CR2_STOP1_BITS
578#endif
579
580#ifndef UART5_CR3
581#define UART5_CR3 0
582#endif
583
584static SerialConfig usart5_config = {
585 UART5_BAUD, /* BITRATE */
586 UART5_CR1, /* USART CR1 */
587 UART5_CR2, /* USART CR2 */
588 UART5_CR3 /* USART CR3 */
589};
590
591static struct SerialInit uart5_init_struct = SERIAL_INIT_NULL;
592
593// Threads RX and TX
594#if USE_UART5_RX
595static MUTEX_DECL(uart5_rx_mtx);
596static SEMAPHORE_DECL(uart5_rx_sem, 0);
597
598static __attribute__((noreturn)) void thd_uart5_rx(void *arg)
599{
600 (void) arg;
601 chRegSetThreadName("uart5_rx");
602
603 while (TRUE) {
604 handle_uart_rx(&uart5);
605 }
606}
607
608static THD_WORKING_AREA(wa_thd_uart5_rx, UART_THREAD_STACK_SIZE);
609#endif
610
611#if USE_UART5_TX
612static MUTEX_DECL(uart5_tx_mtx);
613static SEMAPHORE_DECL(uart5_tx_sem, 0);
614
615static __attribute__((noreturn)) void thd_uart5_tx(void *arg)
616{
617 (void) arg;
618 chRegSetThreadName("uart5_tx");
619
620 while (TRUE) {
621 handle_uart_tx(&uart5);
622 }
623}
624static THD_WORKING_AREA(wa_thd_uart5_tx, UART_THREAD_STACK_SIZE);
625#endif
626
627void uart5_init(void)
628{
629 uart_periph_init(&uart5);
630
631 // Only set pin if enabled and not statically defined in board file
632#if USE_UART5_TX && defined UART5_GPIO_PORT_TX
633 gpio_setup_pin_af(UART5_GPIO_PORT_TX, UART5_GPIO_TX, UART5_GPIO_AF, TRUE);
634#endif
635#if USE_UART5_RX && defined UART5_GPIO_PORT_RX
636 gpio_setup_pin_af(UART5_GPIO_PORT_RX, UART5_GPIO_RX, UART5_GPIO_AF, FALSE);
637#endif
638
639 sdStart(&SD5, &usart5_config);
640 uart5.reg_addr = &SD5;
641 uart5.baudrate = UART5_BAUD;
642 uart5.init_struct = &uart5_init_struct;
643 uart5_init_struct.conf = &usart5_config;
644
645 // Create threads
646#if USE_UART5_RX
647 uart5_init_struct.rx_mtx = &uart5_rx_mtx;
648 uart5_init_struct.rx_sem = &uart5_rx_sem;
649 chThdCreateStatic(wa_thd_uart5_rx, sizeof(wa_thd_uart5_rx),
650 NORMALPRIO + 1, thd_uart5_rx, NULL);
651#endif
652#if USE_UART5_TX
653 uart5_init_struct.tx_mtx = &uart5_tx_mtx;
654 uart5_init_struct.tx_sem = &uart5_tx_sem;
655 chThdCreateStatic(wa_thd_uart5_tx, sizeof(wa_thd_uart5_tx),
656 NORMALPRIO + 1, thd_uart5_tx, NULL);
657#endif
658}
659
660#endif
661
662#if USE_UART6
663
664#ifndef UART6_BAUD
665#define UART6_BAUD SERIAL_DEFAULT_BITRATE
666#endif
667
668/* by default enable UART Tx and Rx */
669#ifndef USE_UART6_TX
670#define USE_UART6_TX TRUE
671#endif
672#ifndef USE_UART6_RX
673#define USE_UART6_RX TRUE
674#endif
675
676#ifndef UART6_CR1
677#define UART6_CR1 0
678#endif
679
680#ifndef UART6_CR2
681#define UART6_CR2 USART_CR2_STOP1_BITS
682#endif
683
684#ifndef UART6_CR3
685#define UART6_CR3 0
686#endif
687
688static SerialConfig usart6_config = {
689 UART6_BAUD, /* BITRATE */
690 UART6_CR1, /* USART CR1 */
691 UART6_CR2, /* USART CR2 */
692 UART6_CR3 /* USART CR3 */
693};
694
695static struct SerialInit uart6_init_struct = SERIAL_INIT_NULL;
696
697// Threads RX and TX
698#if USE_UART6_RX
699static MUTEX_DECL(uart6_rx_mtx);
700static SEMAPHORE_DECL(uart6_rx_sem, 0);
701
702static __attribute__((noreturn)) void thd_uart6_rx(void *arg)
703{
704 (void) arg;
705 chRegSetThreadName("uart6_rx");
706
707 while (TRUE) {
708 handle_uart_rx(&uart6);
709 }
710}
711
712static THD_WORKING_AREA(wa_thd_uart6_rx, UART_THREAD_STACK_SIZE);
713#endif
714
715#if USE_UART6_TX
716static MUTEX_DECL(uart6_tx_mtx);
717static SEMAPHORE_DECL(uart6_tx_sem, 0);
718
719static __attribute__((noreturn)) void thd_uart6_tx(void *arg)
720{
721 (void) arg;
722 chRegSetThreadName("uart6_tx");
723
724 while (TRUE) {
725 handle_uart_tx(&uart6);
726 }
727}
728static THD_WORKING_AREA(wa_thd_uart6_tx, UART_THREAD_STACK_SIZE);
729#endif
730
731void uart6_init(void)
732{
733 uart_periph_init(&uart6);
734
735 // Only set pin if enabled and not statically defined in board file
736#if USE_UART6_TX && defined UART6_GPIO_PORT_TX
737 gpio_setup_pin_af(UART6_GPIO_PORT_TX, UART6_GPIO_TX, UART6_GPIO_AF, TRUE);
738#endif
739#if USE_UART6_RX && defined UART6_GPIO_PORT_RX
740 gpio_setup_pin_af(UART6_GPIO_PORT_RX, UART6_GPIO_RX, UART6_GPIO_AF, FALSE);
741#endif
742
743 sdStart(&SD6, &usart6_config);
744 uart6.reg_addr = &SD6;
745 uart6.baudrate = UART6_BAUD;
746 uart6.init_struct = &uart6_init_struct;
747 uart6_init_struct.conf = &usart6_config;
748
749 // Create threads
750#if USE_UART6_RX
751 uart6_init_struct.rx_mtx = &uart6_rx_mtx;
752 uart6_init_struct.rx_sem = &uart6_rx_sem;
753 chThdCreateStatic(wa_thd_uart6_rx, sizeof(wa_thd_uart6_rx),
754 NORMALPRIO + 1, thd_uart6_rx, NULL);
755#endif
756#if USE_UART6_TX
757 uart6_init_struct.tx_mtx = &uart6_tx_mtx;
758 uart6_init_struct.tx_sem = &uart6_tx_sem;
759 chThdCreateStatic(wa_thd_uart6_tx, sizeof(wa_thd_uart6_tx),
760 NORMALPRIO + 1, thd_uart6_tx, NULL);
761#endif
762
763#if defined UART6_GPIO_CTS && defined UART6_GPIO_PORT_CTS
764 uart6_init_struct.cts_pin = UART6_GPIO_CTS;
765 uart6_init_struct.cts_port = UART6_GPIO_PORT_CTS;
766#endif
767}
768
769#endif
770
771#if USE_UART7
772
773#ifndef UART7_BAUD
774#define UART7_BAUD SERIAL_DEFAULT_BITRATE
775#endif
776
777/* by default enable UART Tx and Rx */
778#ifndef USE_UART7_TX
779#define USE_UART7_TX TRUE
780#endif
781#ifndef USE_UART7_RX
782#define USE_UART7_RX TRUE
783#endif
784
785#ifndef UART7_CR1
786#define UART7_CR1 0
787#endif
788
789#ifndef UART7_CR2
790#define UART7_CR2 USART_CR2_STOP1_BITS
791#endif
792
793#ifndef UART7_CR3
794#define UART7_CR3 0
795#endif
796
797static SerialConfig usart7_config = {
798 UART7_BAUD, /* BITRATE */
799 UART7_CR1, /* USART CR1 */
800 UART7_CR2, /* USART CR2 */
801 UART7_CR3 /* USART CR3 */
802};
803
804static struct SerialInit uart7_init_struct = SERIAL_INIT_NULL;
805
806// Threads RX and TX
807#if USE_UART7_RX
808static MUTEX_DECL(uart7_rx_mtx);
809static SEMAPHORE_DECL(uart7_rx_sem, 0);
810
811static __attribute__((noreturn)) void thd_uart7_rx(void *arg)
812{
813 (void) arg;
814 chRegSetThreadName("uart7_rx");
815
816 while (TRUE) {
817 handle_uart_rx(&uart7);
818 }
819}
820
821static THD_WORKING_AREA(wa_thd_uart7_rx, UART_THREAD_STACK_SIZE);
822#endif
823
824#if USE_UART7_TX
825static MUTEX_DECL(uart7_tx_mtx);
826static SEMAPHORE_DECL(uart7_tx_sem, 0);
827
828static __attribute__((noreturn)) void thd_uart7_tx(void *arg)
829{
830 (void) arg;
831 chRegSetThreadName("uart7_tx");
832
833 while (TRUE) {
834 handle_uart_tx(&uart7);
835 }
836}
837static THD_WORKING_AREA(wa_thd_uart7_tx, UART_THREAD_STACK_SIZE);
838#endif
839
840void uart7_init(void)
841{
842 uart_periph_init(&uart7);
843
844 // Only set pin if enabled and not statically defined in board file
845#if USE_UART7_TX && defined UART7_GPIO_PORT_TX
846 gpio_setup_pin_af(UART7_GPIO_PORT_TX, UART7_GPIO_TX, UART7_GPIO_AF, TRUE);
847#endif
848#if USE_UART7_RX && defined UART7_GPIO_PORT_RX
849 gpio_setup_pin_af(UART7_GPIO_PORT_RX, UART7_GPIO_RX, UART7_GPIO_AF, FALSE);
850#endif
851
852 sdStart(&SD7, &usart7_config);
853 uart7.reg_addr = &SD7;
854 uart7.baudrate = UART7_BAUD;
855 uart7.init_struct = &uart7_init_struct;
856 uart7_init_struct.conf = &usart7_config;
857
858 // Create threads
859#if USE_UART7_RX
860 uart7_init_struct.rx_mtx = &uart7_rx_mtx;
861 uart7_init_struct.rx_sem = &uart7_rx_sem;
862 chThdCreateStatic(wa_thd_uart7_rx, sizeof(wa_thd_uart7_rx),
863 NORMALPRIO + 1, thd_uart7_rx, NULL);
864#endif
865#if USE_UART7_TX
866 uart7_init_struct.tx_mtx = &uart7_tx_mtx;
867 uart7_init_struct.tx_sem = &uart7_tx_sem;
868 chThdCreateStatic(wa_thd_uart7_tx, sizeof(wa_thd_uart7_tx),
869 NORMALPRIO + 1, thd_uart7_tx, NULL);
870#endif
871}
872
873#endif
874
875#if USE_UART8
876
877#ifndef UART8_BAUD
878#define UART8_BAUD SERIAL_DEFAULT_BITRATE
879#endif
880
881/* by default enable UART Tx and Rx */
882#ifndef USE_UART8_TX
883#define USE_UART8_TX TRUE
884#endif
885#ifndef USE_UART8_RX
886#define USE_UART8_RX TRUE
887#endif
888
889#ifndef UART8_CR1
890#define UART8_CR1 0
891#endif
892
893#ifndef UART8_CR2
894#define UART8_CR2 USART_CR2_STOP1_BITS
895#endif
896
897#ifndef UART8_CR3
898#define UART8_CR3 0
899#endif
900
901static SerialConfig usart8_config = {
902 UART8_BAUD, /* BITRATE */
903 UART8_CR1, /* USART CR1 */
904 UART8_CR2, /* USART CR2 */
905 UART8_CR3 /* USART CR3 */
906};
907
908static struct SerialInit uart8_init_struct = SERIAL_INIT_NULL;
909
910// Threads RX and TX
911#if USE_UART8_RX
912static MUTEX_DECL(uart8_rx_mtx);
913static SEMAPHORE_DECL(uart8_rx_sem, 0);
914
915static __attribute__((noreturn)) void thd_uart8_rx(void *arg)
916{
917 (void) arg;
918 chRegSetThreadName("uart8_rx");
919
920 while (TRUE) {
921 handle_uart_rx(&uart8);
922 }
923}
924
925static THD_WORKING_AREA(wa_thd_uart8_rx, UART_THREAD_STACK_SIZE);
926#endif
927
928#if USE_UART8_TX
929static MUTEX_DECL(uart8_tx_mtx);
930static SEMAPHORE_DECL(uart8_tx_sem, 0);
931
932static __attribute__((noreturn)) void thd_uart8_tx(void *arg)
933{
934 (void) arg;
935 chRegSetThreadName("uart8_tx");
936
937 while (TRUE) {
938 handle_uart_tx(&uart8);
939 }
940}
941static THD_WORKING_AREA(wa_thd_uart8_tx, UART_THREAD_STACK_SIZE);
942#endif
943
944void uart8_init(void)
945{
946 uart_periph_init(&uart8);
947
948 // Only set pin if enabled and not statically defined in board file
949#if USE_UART8_TX && defined UART8_GPIO_PORT_TX
950 gpio_setup_pin_af(UART8_GPIO_PORT_TX, UART8_GPIO_TX, UART8_GPIO_AF, TRUE);
951#endif
952#if USE_UART8_RX && defined UART8_GPIO_PORT_RX
953 gpio_setup_pin_af(UART8_GPIO_PORT_RX, UART8_GPIO_RX, UART8_GPIO_AF, FALSE);
954#endif
955
956 sdStart(&SD8, &usart8_config);
957 uart8.reg_addr = &SD8;
958 uart8.baudrate = UART8_BAUD;
959 uart8.init_struct = &uart8_init_struct;
960 uart8_init_struct.conf = &usart8_config;
961
962 // Create threads
963#if USE_UART8_RX
964 uart8_init_struct.rx_mtx = &uart8_rx_mtx;
965 uart8_init_struct.rx_sem = &uart8_rx_sem;
966 chThdCreateStatic(wa_thd_uart8_rx, sizeof(wa_thd_uart8_rx),
967 NORMALPRIO + 1, thd_uart8_rx, NULL);
968#endif
969#if USE_UART8_TX
970 uart8_init_struct.tx_mtx = &uart8_tx_mtx;
971 uart8_init_struct.tx_sem = &uart8_tx_sem;
972 chThdCreateStatic(wa_thd_uart8_tx, sizeof(wa_thd_uart8_tx),
973 NORMALPRIO + 1, thd_uart8_tx, NULL);
974#endif
975}
976
977#endif
978
979
980uint8_t uart_getch(struct uart_periph *p)
981{
982 //to keep compatibility with loop oriented paparazzi architecture, read is not blocking
983 //struct SerialInit *init_struct = (struct SerialInit*)(p->init_struct);
984 //chSemWait (init_struct->rx_sem);
985 struct SerialInit *init_struct = (struct SerialInit *)(p->init_struct);
986 chMtxLock(init_struct->rx_mtx);
987 uint8_t ret = p->rx_buf[p->rx_extract_idx];
988 p->rx_extract_idx = (p->rx_extract_idx + 1) % UART_RX_BUFFER_SIZE;
989 chMtxUnlock(init_struct->rx_mtx);
990 return ret;
991}
992
996void uart_periph_set_baudrate(struct uart_periph *p, uint32_t baud)
997{
998 struct SerialInit *init_struct = (struct SerialInit *)(p->init_struct);
999 SerialConfig *conf = init_struct->conf;
1000 // set new baudrate
1001 conf->speed = baud;
1002 p->baudrate = baud;
1003 // restart periph
1004 sdStop((SerialDriver *)(p->reg_addr));
1005 sdStart((SerialDriver *)(p->reg_addr), conf);
1006}
1007
1011void uart_periph_set_mode(struct uart_periph *p __attribute__((unused)), bool tx_enabled __attribute__((unused)),
1012 bool rx_enabled __attribute__((unused)), bool hw_flow_control __attribute__((unused))) {}
1013#if defined(STM32H7XX)
1014#define __USART_CR1_M USART_CR1_M0
1015#elif defined(STM32F7XX)
1016#define __USART_CR1_M USART_CR1_M_0
1017#elif defined(STM32F1XX) || defined (STM32F3XX) || defined(STM32F4XX)
1018#define __USART_CR1_M USART_CR1_M
1019#else
1020#error Unsupported board
1021#endif
1022
1026void uart_periph_set_bits_stop_parity(struct uart_periph *p,
1027 uint8_t bits, uint8_t stop, uint8_t parity)
1028{
1029 struct SerialInit *init_struct = (struct SerialInit *)(p->init_struct);
1030 SerialConfig *conf = init_struct->conf;
1031
1032 /* Configure USART parity and data bits */
1033 if (parity == UPARITY_EVEN) {
1034 conf->cr1 |= USART_CR1_PCE; // set parity control bit
1035 conf->cr1 &= ~USART_CR1_PS; // clear parity selection bit
1036 if (bits == UBITS_7) {
1037 conf->cr1 &= ~__USART_CR1_M; // clear word length bit
1038 } else { // 8 data bits by default
1039 conf->cr1 |= __USART_CR1_M; // set word length bit
1040 }
1041 } else if (parity == UPARITY_ODD) {
1042 conf->cr1 |= USART_CR1_PCE; // set parity control bit
1043 conf->cr1 |= USART_CR1_PS; // set parity selection bit
1044 if (bits == UBITS_7) {
1045 conf->cr1 &= ~__USART_CR1_M; // clear word length bit
1046 } else { // 8 data bits by default
1047 conf->cr1 |= __USART_CR1_M; // set word length bit
1048 }
1049 } else { // 8 data bist, NO_PARITY by default
1050 conf->cr1 &= ~USART_CR1_PCE; // clear parity control bit
1051 conf->cr1 &= ~__USART_CR1_M; // clear word length bit
1052 }
1053 /* Configure USART stop bits */
1054 conf->cr2 &= ~USART_CR2_STOP; // clear stop bits
1055 if (stop == USTOP_2) {
1056 conf-> cr2 |= USART_CR2_STOP2_BITS; // set bits for 2 stops
1057 } else { // 1 stop bit by default
1058 conf-> cr2 |= USART_CR2_STOP1_BITS; // set bits for 1 stop
1059 }
1060
1061 sdStop((SerialDriver *)(p->reg_addr));
1062 sdStart((SerialDriver *)(p->reg_addr), conf);
1063}
1064
1065#if defined(STM32F7XX) || defined(STM32H7XX)
1069void uart_periph_invert_data_logic(struct uart_periph *p, bool invert_rx, bool invert_tx)
1070{
1071 struct SerialInit *init_struct = (struct SerialInit *)(p->init_struct);
1072 SerialConfig *conf = init_struct->conf;
1073 if (invert_rx) {
1074 conf->cr2 |= USART_CR2_RXINV; // set rxinv bit
1075 } else {
1076 conf->cr2 &= ~USART_CR2_RXINV; // clear rxinv bit
1077 }
1078 if (invert_tx) {
1079 conf->cr2 |= USART_CR2_TXINV; // set txinv bit
1080 } else {
1081 conf->cr2 &= ~USART_CR2_TXINV; // clear txinv bit
1082 }
1083 sdStop((SerialDriver *)(p->reg_addr));
1084 sdStart((SerialDriver *)(p->reg_addr), conf);
1085}
1086#endif
1087
1088// Check free space and set a positive value for fd if valid
1089// and lock driver with mutex
1090int uart_check_free_space(struct uart_periph *p, long *fd, uint16_t len)
1091{
1092 struct SerialInit *init_struct = (struct SerialInit *)(p->init_struct);
1093 int space = p->tx_extract_idx - p->tx_insert_idx - 1;
1094 if (space < 0) {
1095 space += UART_TX_BUFFER_SIZE;
1096 }
1097 if (space >= len) {
1098 *fd = 1;
1099 chMtxLock(init_struct->tx_mtx);
1100 return space;
1101 }
1102 return 0;
1103}
1104
1108void uart_put_byte(struct uart_periph *p, long fd, uint8_t data)
1109{
1110 struct SerialInit *init_struct = (struct SerialInit *)(p->init_struct);
1111 if (fd == 0) {
1112 // if fd is zero, assume the driver is not already locked
1113 chMtxLock(init_struct->tx_mtx);
1114 uint16_t temp = (p->tx_insert_idx + 1) % UART_TX_BUFFER_SIZE;
1115 if (temp == p->tx_extract_idx) {
1116 chMtxUnlock(init_struct->tx_mtx);
1117 return; // no room
1118 }
1119 p->tx_buf[p->tx_insert_idx] = data;
1120 p->tx_insert_idx = temp;
1121
1122 chMtxUnlock(init_struct->tx_mtx);
1123 // send signal to start transmission
1124 chSemSignal(init_struct->tx_sem);
1125 } else {
1126 // assume driver is locked and available space have been checked
1127 p->tx_buf[p->tx_insert_idx] = data;
1128 p->tx_insert_idx = (p->tx_insert_idx + 1) % UART_TX_BUFFER_SIZE;
1129 }
1130}
1131
1135void uart_put_buffer(struct uart_periph *p, long fd, const uint8_t *data, uint16_t len)
1136{
1137 struct SerialInit *init_struct = (struct SerialInit *)(p->init_struct);
1138 if (fd == 0) {
1139 // if fd is zero, assume the driver is not already locked
1140 // and available space should be checked
1141 chMtxLock(init_struct->tx_mtx);
1142 int16_t space = p->tx_extract_idx - p->tx_insert_idx;
1143 if (space <= 0) {
1144 space += UART_TX_BUFFER_SIZE;
1145 }
1146 if ((uint16_t)(space - 1) < len) {
1147 chMtxUnlock(init_struct->tx_mtx);
1148 return; // no room
1149 }
1150 }
1151 // insert data into buffer
1152 int i;
1153 for (i = 0; i < len; i++) {
1154 p->tx_buf[p->tx_insert_idx] = data[i];
1155 p->tx_insert_idx = (p->tx_insert_idx + 1) % UART_TX_BUFFER_SIZE;
1156 }
1157 // unlock if needed
1158 if (fd == 0) {
1159 chMtxUnlock(init_struct->tx_mtx);
1160 // send signal to start transmission
1161 chSemSignal(init_struct->tx_sem);
1162 }
1163}
1164
1165void uart_send_message(struct uart_periph *p, long fd)
1166{
1167 struct SerialInit *init_struct = (struct SerialInit *)(p->init_struct);
1168 // unlock driver in case it is not done (fd > 0)
1169 if (fd != 0) {
1170 chMtxUnlock(init_struct->tx_mtx);
1171 }
1172 // send signal to start transmission
1173 chSemSignal(init_struct->tx_sem);
1174}
1175
1176#endif // HAL_USE_SERIAL
1177
UART6_GPIO_RX
#define UART6_GPIO_RX
Definition apogee_1.0.h:131
UART1_GPIO_TX
#define UART1_GPIO_TX
Definition apogee_1.0.h:116
UART4_GPIO_PORT_RX
#define UART4_GPIO_PORT_RX
Definition apogee_1.0.h:124
UART1_GPIO_PORT_TX
#define UART1_GPIO_PORT_TX
Definition apogee_1.0.h:115
UART4_GPIO_RX
#define UART4_GPIO_RX
Definition apogee_1.0.h:125
UART6_GPIO_PORT_RX
#define UART6_GPIO_PORT_RX
Definition apogee_1.0.h:130
UART2_GPIO_PORT_RX
#define UART2_GPIO_PORT_RX
Definition apogee_1.0.h:119
UART6_GPIO_TX
#define UART6_GPIO_TX
Definition apogee_1.0.h:133
UART1_GPIO_PORT_RX
#define UART1_GPIO_PORT_RX
Definition apogee_1.0.h:113
UART6_GPIO_PORT_TX
#define UART6_GPIO_PORT_TX
Definition apogee_1.0.h:132
UART4_GPIO_TX
#define UART4_GPIO_TX
Definition apogee_1.0.h:127
UART1_GPIO_RX
#define UART1_GPIO_RX
Definition apogee_1.0.h:114
UART2_GPIO_RX
#define UART2_GPIO_RX
Definition apogee_1.0.h:120
UART4_GPIO_PORT_TX
#define UART4_GPIO_PORT_TX
Definition apogee_1.0.h:126
UNUSED
#define UNUSED(x)
Definition cc2500_frsky_x.c:12
UART3_GPIO_TX
#define UART3_GPIO_TX
Definition cc3d.h:52
UART3_GPIO_PORT_TX
#define UART3_GPIO_PORT_TX
Definition cc3d.h:51
UART3_GPIO_RX
#define UART3_GPIO_RX
Definition cc3d.h:50
UART3_GPIO_PORT_RX
#define UART3_GPIO_PORT_RX
Definition cc3d.h:49
gpio_setup_pin_af
void gpio_setup_pin_af(ioportid_t port, uint16_t pin, uint8_t af, bool is_output)
Setup a gpio for input or output with alternate function.
Definition gpio_arch.c:65
gpio_get
static uint8_t gpio_get(ioportid_t port, uint16_t pin)
Get level of a gpio.
Definition gpio_arch.h:94
THD_WORKING_AREA
static THD_WORKING_AREA(wa_thd_spi1, SPI_THREAD_STACK_SIZE)
MUTEX_DECL
static MUTEX_DECL(sys_time_mtx)
UART8_GPIO_PORT_RX
#define UART8_GPIO_PORT_RX
Definition chimera.h:391
UART7_GPIO_RX
#define UART7_GPIO_RX
Definition chimera.h:413
UART2_GPIO_TX
#define UART2_GPIO_TX
Definition chimera.h:364
UART7_GPIO_PORT_RX
#define UART7_GPIO_PORT_RX
Definition chimera.h:412
UART8_GPIO_PORT_TX
#define UART8_GPIO_PORT_TX
Definition chimera.h:389
UART8_GPIO_TX
#define UART8_GPIO_TX
Definition chimera.h:390
UART2_GPIO_PORT_TX
#define UART2_GPIO_PORT_TX
UART2 (with optional flow control activated by default)
Definition chimera.h:363
UART8_GPIO_RX
#define UART8_GPIO_RX
Definition chimera.h:392
UART3_GPIO_AF
#define UART3_GPIO_AF
Definition common_board.h:448
UART2_GPIO_AF
#define UART2_GPIO_AF
Definition common_board.h:432
UART7_GPIO_AF
#define UART7_GPIO_AF
Definition common_board.h:512
UART6_GPIO_AF
#define UART6_GPIO_AF
Definition common_board.h:496
UART1_GPIO_AF
#define UART1_GPIO_AF
UART defines.
Definition common_board.h:416
UART5_GPIO_AF
#define UART5_GPIO_AF
Definition common_board.h:480
UART8_GPIO_AF
#define UART8_GPIO_AF
Definition common_board.h:528
UART4_GPIO_AF
#define UART4_GPIO_AF
Definition common_board.h:464
UART6_GPIO_PORT_CTS
#define UART6_GPIO_PORT_CTS
Definition crazyflie.h:184
UART6_GPIO_CTS
#define UART6_GPIO_CTS
Definition crazyflie.h:185
UART5_GPIO_TX
#define UART5_GPIO_TX
Definition elle0_common.h:115
UART5_GPIO_PORT_TX
#define UART5_GPIO_PORT_TX
Definition elle0_common.h:114
UART5_GPIO_RX
#define UART5_GPIO_RX
Definition elle0_common.h:113
UART5_GPIO_PORT_RX
#define UART5_GPIO_PORT_RX
Definition elle0_common.h:112
gpio.h
Some architecture independent helper functions for GPIOs.
p
static float p[2][2]
Definition ins_alt_float.c:273
uart_put_byte
void uart_put_byte(struct uart_periph *periph, long fd, uint8_t data)
Definition uart_arch.c:306
uart_periph_set_bits_stop_parity
void uart_periph_set_bits_stop_parity(struct uart_periph *periph, uint8_t bits, uint8_t stop, uint8_t parity)
Definition uart_arch.c:296
uart_getch
uint8_t uart_getch(struct uart_periph *p)
Definition uart_arch.c:348
uart_periph_set_baudrate
void uart_periph_set_baudrate(struct uart_periph *periph, uint32_t baud)
Definition uart_arch.c:280
UART_TX_BUFFER_SIZE
#define UART_TX_BUFFER_SIZE
Definition uart_arch.h:34
UART_RX_BUFFER_SIZE
#define UART_RX_BUFFER_SIZE
Definition uart_arch.h:31
foo
uint16_t foo
Definition main_demo5.c:58
UART7_GPIO_PORT_TX
#define UART7_GPIO_PORT_TX
UART7 (Modem with optional flow control disabled by default)
Definition matekF765-WING.h:350
UART7_GPIO_TX
#define UART7_GPIO_TX
Definition matekF765-WING.h:351
fd
int fd
Definition serial.c:26
UBITS_7
#define UBITS_7
Definition serial_port.c:49
UPARITY_ODD
#define UPARITY_ODD
Definition serial_port.c:56
USTOP_2
#define USTOP_2
Definition serial_port.c:53
UPARITY_EVEN
#define UPARITY_EVEN
Definition serial_port.c:57
TRUE
#define TRUE
Definition std.h:4
FALSE
#define FALSE
Definition std.h:5
uart_periph_set_mode
void uart_periph_set_mode(struct uart_periph *p, bool tx_enabled, bool rx_enabled, bool hw_flow_control)
Definition uart_arch.c:92
uart_send_message
void WEAK uart_send_message(struct uart_periph *p, long fd)
Definition uart.c:170
uart_periph_init
void uart_periph_init(struct uart_periph *p)
Definition uart.c:126
uart_put_buffer
void WEAK uart_put_buffer(struct uart_periph *p, long fd, const uint8_t *data, uint16_t len)
Definition uart.c:161
uart_periph_invert_data_logic
void WEAK uart_periph_invert_data_logic(struct uart_periph *p, bool invert_rx, bool invert_tx)
Definition uart.c:194
uart_check_free_space
int WEAK uart_check_free_space(struct uart_periph *p, long *fd, uint16_t len)
Definition uart.c:151
uart_periph
UART peripheral.
Definition uart.h:72
uint16_t
unsigned short uint16_t
Typedef defining 16 bit unsigned short type.
Definition vl53l1_types.h:88
uint32_t
unsigned int uint32_t
Typedef defining 32 bit unsigned int type.
Definition vl53l1_types.h:78
int16_t
short int16_t
Typedef defining 16 bit short type.
Definition vl53l1_types.h:93
uint8_t
unsigned char uint8_t
Typedef defining 8 bit unsigned char type.
Definition vl53l1_types.h:98
SEMAPHORE_DECL
static SEMAPHORE_DECL(we_ukf_sem, 0)