Paparazzi UAS v7.0_unstable
Paparazzi is a free software Unmanned Aircraft System.
•All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Modules Pages
uart_arch.c
Go to the documentation of this file.
1/*
2 * Copyright (C) 2013 AggieAir, A Remote Sensing Unmanned Aerial System for Scientific Applications
3 * Utah State University, http://aggieair.usu.edu/
4 *
5 * Michal Podhradsky (michal.podhradsky@aggiemail.usu.edu)
6 * Calvin Coopmans (c.r.coopmans@ieee.org)
7 *
8 * Alexandre Bustico <alexandre.bustico@enac.fr>
9 * Gautier Hattenberger <gautier.hattenberger@enac.fr>
10 *
11 * This file is part of paparazzi.
12 *
13 * paparazzi is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
16 * any later version.
17 *
18 * paparazzi is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with paparazzi; see the file COPYING. If not, write to
25 * the Free Software Foundation, 59 Temple Place - Suite 330,
26 * Boston, MA 02111-1307, USA.
27 */
37#include "mcu_periph/uart_arch.h"
38#include <ch.h>
39#include <hal.h>
40#include "mcu_periph/gpio.h"
41#include BOARD_CONFIG
42
43#if HAL_USE_SERIAL
44
45// Default stack size
46#ifndef UART_THREAD_STACK_SIZE
47#define UART_THREAD_STACK_SIZE 512
48#endif
49
50struct SerialInit {
51 SerialConfig *conf;
52 semaphore_t *rx_sem;
53 semaphore_t *tx_sem;
54 mutex_t *rx_mtx;
55 mutex_t *tx_mtx;
56 ioportid_t cts_port;
57 uint16_t cts_pin;
58};
59
60#define SERIAL_INIT_NULL { NULL, NULL, NULL, NULL, NULL, 0, 0 }
61
65UNUSED static void handle_uart_rx(struct uart_periph *p)
66{
67 // wait for next incoming byte
68 uint8_t c = sdGet((SerialDriver *)(p->reg_addr));
69
70 struct SerialInit *init_struct = (struct SerialInit *)(p->init_struct);
71 chMtxLock(init_struct->rx_mtx);
72 uint16_t temp = (p->rx_insert_idx + 1) % UART_RX_BUFFER_SIZE;;
73 // insert new byte
74 p->rx_buf[p->rx_insert_idx] = c;
75 // check for more room in queue
76 if (temp != p->rx_extract_idx) {
77 p->rx_insert_idx = temp; // update insert index
78 }
79 chMtxUnlock(init_struct->rx_mtx);
80 chSemSignal(init_struct->rx_sem);
81}
82
86UNUSED static void handle_uart_tx(struct uart_periph *p)
87{
88 // check if more data to send
89 // send by block with sdWrite if possible: not compatible with soft flow control
90 struct SerialInit *init_struct = (struct SerialInit *)(p->init_struct);
91 chSemWait(init_struct->tx_sem);
92 p->tx_running = true;
93 while (p->tx_insert_idx != p->tx_extract_idx) {
94#if USE_UART_SOFT_FLOW_CONTROL
95 if (init_struct->cts_port != 0) {
96 // wait for CTS line to be set to send next byte
97 while (gpio_get(init_struct->cts_port, init_struct->cts_pin) == 1) ;
98 }
99 uint8_t data = p->tx_buf[p->tx_extract_idx];
100 sdPut((SerialDriver *)p->reg_addr, data);
101 chMtxLock(init_struct->tx_mtx);
102 p->tx_extract_idx++;
103 p->tx_extract_idx %= UART_TX_BUFFER_SIZE;
104 chMtxUnlock(init_struct->tx_mtx);
105 if (init_struct->cts_port != 0) {
106 // wait for physical transfer to be completed
107 while ((((SerialDriver *)p->reg_addr)->usart->SR & USART_SR_TC) == 0) ;
108 }
109#else // normal operation without soft flow control
110 chMtxLock(init_struct->tx_mtx);
111 if (p->tx_insert_idx > p->tx_extract_idx) {
112 sdWrite((SerialDriver *)p->reg_addr, &p->tx_buf[p->tx_extract_idx], p->tx_insert_idx - p->tx_extract_idx);
113 } else {
114 // wrapping circular buffer
115 sdWrite((SerialDriver *)p->reg_addr, &p->tx_buf[p->tx_extract_idx], UART_TX_BUFFER_SIZE - p->tx_extract_idx);
116 sdWrite((SerialDriver *)p->reg_addr, &p->tx_buf[0], p->tx_insert_idx);
117 }
118 p->tx_extract_idx = p->tx_insert_idx;
119 chMtxUnlock(init_struct->tx_mtx);
120#endif
121 }
122 p->tx_running = false;
123}
124
125#if USE_UART1
126
127#ifndef UART1_BAUD
128#define UART1_BAUD SERIAL_DEFAULT_BITRATE
129#endif
130
131/* by default enable UART Tx and Rx */
132#ifndef USE_UART1_TX
133#define USE_UART1_TX TRUE
134#endif
135#ifndef USE_UART1_RX
136#define USE_UART1_RX TRUE
137#endif
138
139#ifndef UART1_CR1
140#define UART1_CR1 0
141#endif
142
143#ifndef UART1_CR2
144#define UART1_CR2 USART_CR2_STOP1_BITS
145#endif
146
147#ifndef UART1_CR3
148#define UART1_CR3 0
149#endif
150
151static SerialConfig usart1_config = {
152 UART1_BAUD, /* BITRATE */
153 UART1_CR1, /* USART CR1 */
154 UART1_CR2, /* USART CR2 */
155 UART1_CR3 /* USART CR3 */
156};
157
158static struct SerialInit uart1_init_struct = SERIAL_INIT_NULL;
159
160// Threads RX and TX
161#if USE_UART1_RX
162static MUTEX_DECL(uart1_rx_mtx);
163static SEMAPHORE_DECL(uart1_rx_sem, 0);
164
165static __attribute__((noreturn)) void thd_uart1_rx(void *arg)
166{
167 (void) arg;
168 chRegSetThreadName("uart1_rx");
169
170 while (TRUE) {
171 handle_uart_rx(&uart1);
172 }
173}
174
175static THD_WORKING_AREA(wa_thd_uart1_rx, UART_THREAD_STACK_SIZE);
176#endif
177
178#if USE_UART1_TX
179static MUTEX_DECL(uart1_tx_mtx);
180static SEMAPHORE_DECL(uart1_tx_sem, 0);
181
182static __attribute__((noreturn)) void thd_uart1_tx(void *arg)
183{
184 (void) arg;
185 chRegSetThreadName("uart1_tx");
186
187 while (TRUE) {
188 handle_uart_tx(&uart1);
189 }
190}
191static THD_WORKING_AREA(wa_thd_uart1_tx, UART_THREAD_STACK_SIZE);
192#endif
193
194void uart1_init(void)
195{
196 uart_periph_init(&uart1);
197
198 // Only set pin if enabled and not statically defined in board file
199#if USE_UART1_TX && defined UART1_GPIO_PORT_TX
200 gpio_setup_pin_af(UART1_GPIO_PORT_TX, UART1_GPIO_TX, UART1_GPIO_AF, TRUE);
201#endif
202#if USE_UART1_RX && defined UART1_GPIO_PORT_RX
203 gpio_setup_pin_af(UART1_GPIO_PORT_RX, UART1_GPIO_RX, UART1_GPIO_AF, FALSE);
204#endif
205
206 sdStart(&SD1, &usart1_config);
207 uart1.reg_addr = &SD1;
208 uart1.baudrate = UART1_BAUD;
209 uart1.init_struct = &uart1_init_struct;
210 uart1_init_struct.conf = &usart1_config;
211
212 // Create threads
213#if USE_UART1_RX
214 uart1_init_struct.rx_mtx = &uart1_rx_mtx;
215 uart1_init_struct.rx_sem = &uart1_rx_sem;
216 chThdCreateStatic(wa_thd_uart1_rx, sizeof(wa_thd_uart1_rx),
217 NORMALPRIO + 1, thd_uart1_rx, NULL);
218#endif
219#if USE_UART1_TX
220 uart1_init_struct.tx_mtx = &uart1_tx_mtx;
221 uart1_init_struct.tx_sem = &uart1_tx_sem;
222 chThdCreateStatic(wa_thd_uart1_tx, sizeof(wa_thd_uart1_tx),
223 NORMALPRIO + 1, thd_uart1_tx, NULL);
224#endif
225}
226
227#endif
228
229
230#if USE_UART2
231
232#ifndef UART2_BAUD
233#define UART2_BAUD SERIAL_DEFAULT_BITRATE
234#endif
235
236/* by default enable UART Tx and Rx */
237#ifndef USE_UART2_TX
238#define USE_UART2_TX TRUE
239#endif
240#ifndef USE_UART2_RX
241#define USE_UART2_RX TRUE
242#endif
243
244
245/* by default disable HW flow control */
246#ifndef UART2_HW_FLOW_CONTROL
247#define UART2_HW_FLOW_CONTROL FALSE
248#endif
249
250#if UART2_HW_FLOW_CONTROL && defined(UART2_CR3)
251#warning "UART2_CR3 reset to your value, HW flow control not enabled! You may want to set USART_CR3_CTSE | USART_CR3_RTSE yourself."
252#endif
253
254#ifndef UART2_CR1
255#define UART2_CR1 0
256#endif
257
258#ifndef UART2_CR2
259#define UART2_CR2 USART_CR2_STOP1_BITS
260#endif
261
262#ifndef UART2_CR3
263#if UART2_HW_FLOW_CONTROL
264#define UART2_CR3 USART_CR3_CTSE | USART_CR3_RTSE
265#else
266#define UART2_CR3 0
267#endif
268#endif
269
270static SerialConfig usart2_config = {
271 UART2_BAUD, /* BITRATE */
272 UART2_CR1, /* USART CR1 */
273 UART2_CR2, /* USART CR2 */
274 UART2_CR3 /* USART CR3 */
275};
276
277static struct SerialInit uart2_init_struct = SERIAL_INIT_NULL;
278
279// Threads RX and TX
280#if USE_UART2_RX
281static MUTEX_DECL(uart2_rx_mtx);
282static SEMAPHORE_DECL(uart2_rx_sem, 0);
283
284static __attribute__((noreturn)) void thd_uart2_rx(void *arg)
285{
286 (void) arg;
287 chRegSetThreadName("uart2_rx");
288
289 while (TRUE) {
290 handle_uart_rx(&uart2);
291 }
292}
293
294static THD_WORKING_AREA(wa_thd_uart2_rx, UART_THREAD_STACK_SIZE);
295#endif
296
297#if USE_UART2_TX
298static MUTEX_DECL(uart2_tx_mtx);
299static SEMAPHORE_DECL(uart2_tx_sem, 0);
300
301static __attribute__((noreturn)) void thd_uart2_tx(void *arg)
302{
303 (void) arg;
304 chRegSetThreadName("uart2_tx");
305
306 while (TRUE) {
307 handle_uart_tx(&uart2);
308 }
309}
310static THD_WORKING_AREA(wa_thd_uart2_tx, UART_THREAD_STACK_SIZE);
311#endif
312
313void uart2_init(void)
314{
315 uart_periph_init(&uart2);
316
317 // Only set pin if enabled and not statically defined in board file
318#if USE_UART2_TX && defined UART2_GPIO_PORT_TX
319 gpio_setup_pin_af(UART2_GPIO_PORT_TX, UART2_GPIO_TX, UART2_GPIO_AF, TRUE);
320#endif
321#if USE_UART2_RX && defined UART2_GPIO_PORT_RX
322 gpio_setup_pin_af(UART2_GPIO_PORT_RX, UART2_GPIO_RX, UART2_GPIO_AF, FALSE);
323#endif
324
325 sdStart(&SD2, &usart2_config);
326 uart2.reg_addr = &SD2;
327 uart2.baudrate = UART2_BAUD;
328 uart2.init_struct = &uart2_init_struct;
329 uart2_init_struct.conf = &usart2_config;
330
331 // Create threads
332#if USE_UART2_RX
333 uart2_init_struct.rx_mtx = &uart2_rx_mtx;
334 uart2_init_struct.rx_sem = &uart2_rx_sem;
335 chThdCreateStatic(wa_thd_uart2_rx, sizeof(wa_thd_uart2_rx),
336 NORMALPRIO + 1, thd_uart2_rx, NULL);
337#endif
338#if USE_UART2_TX
339 uart2_init_struct.tx_mtx = &uart2_tx_mtx;
340 uart2_init_struct.tx_sem = &uart2_tx_sem;
341 chThdCreateStatic(wa_thd_uart2_tx, sizeof(wa_thd_uart2_tx),
342 NORMALPRIO + 1, thd_uart2_tx, NULL);
343#endif
344}
345
346#endif
347
348#if USE_UART3
349
350#ifndef UART3_BAUD
351#define UART3_BAUD SERIAL_DEFAULT_BITRATE
352#endif
353
354/* by default enable UART Tx and Rx */
355#ifndef USE_UART3_TX
356#define USE_UART3_TX TRUE
357#endif
358#ifndef USE_UART3_RX
359#define USE_UART3_RX TRUE
360#endif
361
362#ifndef UART3_CR1
363#define UART3_CR1 0
364#endif
365
366#ifndef UART3_CR2
367#define UART3_CR2 USART_CR2_STOP1_BITS
368#endif
369
370#ifndef UART3_CR3
371#define UART3_CR3 0
372#endif
373
374static SerialConfig usart3_config = {
375 UART3_BAUD, /* BITRATE */
376 UART3_CR1, /* USART CR1 */
377 UART3_CR2, /* USART CR2 */
378 UART3_CR3 /* USART CR3 */
379};
380
381static struct SerialInit uart3_init_struct = SERIAL_INIT_NULL;
382
383// Threads RX and TX
384#if USE_UART3_RX
385static MUTEX_DECL(uart3_rx_mtx);
386static SEMAPHORE_DECL(uart3_rx_sem, 0);
387
388static __attribute__((noreturn)) void thd_uart3_rx(void *arg)
389{
390 (void) arg;
391 chRegSetThreadName("uart3_rx");
392
393 while (TRUE) {
394 handle_uart_rx(&uart3);
395 }
396}
397
398static THD_WORKING_AREA(wa_thd_uart3_rx, UART_THREAD_STACK_SIZE);
399#endif
400
401#if USE_UART3_TX
402static MUTEX_DECL(uart3_tx_mtx);
403static SEMAPHORE_DECL(uart3_tx_sem, 0);
404
405static __attribute__((noreturn)) void thd_uart3_tx(void *arg)
406{
407 (void) arg;
408 chRegSetThreadName("uart3_tx");
409
410 while (TRUE) {
411 handle_uart_tx(&uart3);
412 }
413}
414static THD_WORKING_AREA(wa_thd_uart3_tx, UART_THREAD_STACK_SIZE);
415#endif
416
417void uart3_init(void)
418{
419 uart_periph_init(&uart3);
420
421 // Only set pin if enabled and not statically defined in board file
422#if USE_UART3_TX && defined UART3_GPIO_PORT_TX
423 gpio_setup_pin_af(UART3_GPIO_PORT_TX, UART3_GPIO_TX, UART3_GPIO_AF, TRUE);
424#endif
425#if USE_UART3_RX && defined UART3_GPIO_PORT_RX
426 gpio_setup_pin_af(UART3_GPIO_PORT_RX, UART3_GPIO_RX, UART3_GPIO_AF, FALSE);
427#endif
428
429 sdStart(&SD3, &usart3_config);
430 uart3.reg_addr = &SD3;
431 uart3.baudrate = UART3_BAUD;
432 uart3.init_struct = &uart3_init_struct;
433 uart3_init_struct.conf = &usart3_config;
434
435 // Create threads
436#if USE_UART3_RX
437 uart3_init_struct.rx_mtx = &uart3_rx_mtx;
438 uart3_init_struct.rx_sem = &uart3_rx_sem;
439 chThdCreateStatic(wa_thd_uart3_rx, sizeof(wa_thd_uart3_rx),
440 NORMALPRIO + 1, thd_uart3_rx, NULL);
441#endif
442#if USE_UART3_TX
443 uart3_init_struct.tx_mtx = &uart3_tx_mtx;
444 uart3_init_struct.tx_sem = &uart3_tx_sem;
445 chThdCreateStatic(wa_thd_uart3_tx, sizeof(wa_thd_uart3_tx),
446 NORMALPRIO + 1, thd_uart3_tx, NULL);
447#endif
448}
449
450#endif
451
452#if USE_UART4
453
454#ifndef UART4_BAUD
455#define UART4_BAUD SERIAL_DEFAULT_BITRATE
456#endif
457
458/* by default enable UART Tx and Rx */
459#ifndef USE_UART4_TX
460#define USE_UART4_TX TRUE
461#endif
462#ifndef USE_UART4_RX
463#define USE_UART4_RX TRUE
464#endif
465
466#ifndef UART4_CR1
467#define UART4_CR1 0
468#endif
469
470#ifndef UART4_CR2
471#define UART4_CR2 USART_CR2_STOP1_BITS
472#endif
473
474#ifndef UART4_CR3
475#define UART4_CR3 0
476#endif
477
478static SerialConfig usart4_config = {
479 UART4_BAUD, /* BITRATE */
480 UART4_CR1, /* USART CR1 */
481 UART4_CR2, /* USART CR2 */
482 UART4_CR3 /* USART CR3 */
483};
484
485static struct SerialInit uart4_init_struct = SERIAL_INIT_NULL;
486
487// Threads RX and TX
488#if USE_UART4_RX
489static MUTEX_DECL(uart4_rx_mtx);
490static SEMAPHORE_DECL(uart4_rx_sem, 0);
491
492static __attribute__((noreturn)) void thd_uart4_rx(void *arg)
493{
494 (void) arg;
495 chRegSetThreadName("uart4_rx");
496
497 while (TRUE) {
498 handle_uart_rx(&uart4);
499 }
500}
501
502static THD_WORKING_AREA(wa_thd_uart4_rx, UART_THREAD_STACK_SIZE);
503#endif
504
505#if USE_UART4_TX
506static MUTEX_DECL(uart4_tx_mtx);
507static SEMAPHORE_DECL(uart4_tx_sem, 0);
508
509static __attribute__((noreturn)) void thd_uart4_tx(void *arg)
510{
511 (void) arg;
512 chRegSetThreadName("uart4_tx");
513
514 while (TRUE) {
515 handle_uart_tx(&uart4);
516 }
517}
518static THD_WORKING_AREA(wa_thd_uart4_tx, UART_THREAD_STACK_SIZE);
519#endif
520
521void uart4_init(void)
522{
523 uart_periph_init(&uart4);
524
525 // Only set pin if enabled and not statically defined in board file
526#if USE_UART4_TX && defined UART4_GPIO_PORT_TX
527 gpio_setup_pin_af(UART4_GPIO_PORT_TX, UART4_GPIO_TX, UART4_GPIO_AF, TRUE);
528#endif
529#if USE_UART4_RX && defined UART4_GPIO_PORT_RX
530 gpio_setup_pin_af(UART4_GPIO_PORT_RX, UART4_GPIO_RX, UART4_GPIO_AF, FALSE);
531#endif
532
533 sdStart(&SD4, &usart4_config);
534 uart4.reg_addr = &SD4;
535 uart4.baudrate = UART4_BAUD;
536 uart4.init_struct = &uart4_init_struct;
537 uart4_init_struct.conf = &usart4_config;
538
539 // Create threads
540#if USE_UART4_RX
541 uart4_init_struct.rx_mtx = &uart4_rx_mtx;
542 uart4_init_struct.rx_sem = &uart4_rx_sem;
543 chThdCreateStatic(wa_thd_uart4_rx, sizeof(wa_thd_uart4_rx),
544 NORMALPRIO + 1, thd_uart4_rx, NULL);
545#endif
546#if USE_UART4_TX
547 uart4_init_struct.tx_mtx = &uart4_tx_mtx;
548 uart4_init_struct.tx_sem = &uart4_tx_sem;
549 chThdCreateStatic(wa_thd_uart4_tx, sizeof(wa_thd_uart4_tx),
550 NORMALPRIO + 1, thd_uart4_tx, NULL);
551#endif
552}
553
554#endif
555
556#if USE_UART5
557
558#ifndef UART5_BAUD
559#define UART5_BAUD SERIAL_DEFAULT_BITRATE
560#endif
561
562/* by default enable UART Tx and Rx */
563#ifndef USE_UART5_TX
564#define USE_UART5_TX TRUE
565#endif
566#ifndef USE_UART5_RX
567#define USE_UART5_RX TRUE
568#endif
569
570#ifndef UART5_CR1
571#define UART5_CR1 0
572#endif
573
574#ifndef UART5_CR2
575#define UART5_CR2 USART_CR2_STOP1_BITS
576#endif
577
578#ifndef UART5_CR3
579#define UART5_CR3 0
580#endif
581
582static SerialConfig usart5_config = {
583 UART5_BAUD, /* BITRATE */
584 UART5_CR1, /* USART CR1 */
585 UART5_CR2, /* USART CR2 */
586 UART5_CR3 /* USART CR3 */
587};
588
589static struct SerialInit uart5_init_struct = SERIAL_INIT_NULL;
590
591// Threads RX and TX
592#if USE_UART5_RX
593static MUTEX_DECL(uart5_rx_mtx);
594static SEMAPHORE_DECL(uart5_rx_sem, 0);
595
596static __attribute__((noreturn)) void thd_uart5_rx(void *arg)
597{
598 (void) arg;
599 chRegSetThreadName("uart5_rx");
600
601 while (TRUE) {
602 handle_uart_rx(&uart5);
603 }
604}
605
606static THD_WORKING_AREA(wa_thd_uart5_rx, UART_THREAD_STACK_SIZE);
607#endif
608
609#if USE_UART5_TX
610static MUTEX_DECL(uart5_tx_mtx);
611static SEMAPHORE_DECL(uart5_tx_sem, 0);
612
613static __attribute__((noreturn)) void thd_uart5_tx(void *arg)
614{
615 (void) arg;
616 chRegSetThreadName("uart5_tx");
617
618 while (TRUE) {
619 handle_uart_tx(&uart5);
620 }
621}
622static THD_WORKING_AREA(wa_thd_uart5_tx, UART_THREAD_STACK_SIZE);
623#endif
624
625void uart5_init(void)
626{
627 uart_periph_init(&uart5);
628
629 // Only set pin if enabled and not statically defined in board file
630#if USE_UART5_TX && defined UART5_GPIO_PORT_TX
631 gpio_setup_pin_af(UART5_GPIO_PORT_TX, UART5_GPIO_TX, UART5_GPIO_AF, TRUE);
632#endif
633#if USE_UART5_RX && defined UART5_GPIO_PORT_RX
634 gpio_setup_pin_af(UART5_GPIO_PORT_RX, UART5_GPIO_RX, UART5_GPIO_AF, FALSE);
635#endif
636
637 sdStart(&SD5, &usart5_config);
638 uart5.reg_addr = &SD5;
639 uart5.baudrate = UART5_BAUD;
640 uart5.init_struct = &uart5_init_struct;
641 uart5_init_struct.conf = &usart5_config;
642
643 // Create threads
644#if USE_UART5_RX
645 uart5_init_struct.rx_mtx = &uart5_rx_mtx;
646 uart5_init_struct.rx_sem = &uart5_rx_sem;
647 chThdCreateStatic(wa_thd_uart5_rx, sizeof(wa_thd_uart5_rx),
648 NORMALPRIO + 1, thd_uart5_rx, NULL);
649#endif
650#if USE_UART5_TX
651 uart5_init_struct.tx_mtx = &uart5_tx_mtx;
652 uart5_init_struct.tx_sem = &uart5_tx_sem;
653 chThdCreateStatic(wa_thd_uart5_tx, sizeof(wa_thd_uart5_tx),
654 NORMALPRIO + 1, thd_uart5_tx, NULL);
655#endif
656}
657
658#endif
659
660#if USE_UART6
661
662#ifndef UART6_BAUD
663#define UART6_BAUD SERIAL_DEFAULT_BITRATE
664#endif
665
666/* by default enable UART Tx and Rx */
667#ifndef USE_UART6_TX
668#define USE_UART6_TX TRUE
669#endif
670#ifndef USE_UART6_RX
671#define USE_UART6_RX TRUE
672#endif
673
674#ifndef UART6_CR1
675#define UART6_CR1 0
676#endif
677
678#ifndef UART6_CR2
679#define UART6_CR2 USART_CR2_STOP1_BITS
680#endif
681
682#ifndef UART6_CR3
683#define UART6_CR3 0
684#endif
685
686static SerialConfig usart6_config = {
687 UART6_BAUD, /* BITRATE */
688 UART6_CR1, /* USART CR1 */
689 UART6_CR2, /* USART CR2 */
690 UART6_CR3 /* USART CR3 */
691};
692
693static struct SerialInit uart6_init_struct = SERIAL_INIT_NULL;
694
695// Threads RX and TX
696#if USE_UART6_RX
697static MUTEX_DECL(uart6_rx_mtx);
698static SEMAPHORE_DECL(uart6_rx_sem, 0);
699
700static __attribute__((noreturn)) void thd_uart6_rx(void *arg)
701{
702 (void) arg;
703 chRegSetThreadName("uart6_rx");
704
705 while (TRUE) {
706 handle_uart_rx(&uart6);
707 }
708}
709
710static THD_WORKING_AREA(wa_thd_uart6_rx, UART_THREAD_STACK_SIZE);
711#endif
712
713#if USE_UART6_TX
714static MUTEX_DECL(uart6_tx_mtx);
715static SEMAPHORE_DECL(uart6_tx_sem, 0);
716
717static __attribute__((noreturn)) void thd_uart6_tx(void *arg)
718{
719 (void) arg;
720 chRegSetThreadName("uart6_tx");
721
722 while (TRUE) {
723 handle_uart_tx(&uart6);
724 }
725}
726static THD_WORKING_AREA(wa_thd_uart6_tx, UART_THREAD_STACK_SIZE);
727#endif
728
729void uart6_init(void)
730{
731 uart_periph_init(&uart6);
732
733 // Only set pin if enabled and not statically defined in board file
734#if USE_UART6_TX && defined UART6_GPIO_PORT_TX
735 gpio_setup_pin_af(UART6_GPIO_PORT_TX, UART6_GPIO_TX, UART6_GPIO_AF, TRUE);
736#endif
737#if USE_UART6_RX && defined UART6_GPIO_PORT_RX
738 gpio_setup_pin_af(UART6_GPIO_PORT_RX, UART6_GPIO_RX, UART6_GPIO_AF, FALSE);
739#endif
740
741 sdStart(&SD6, &usart6_config);
742 uart6.reg_addr = &SD6;
743 uart6.baudrate = UART6_BAUD;
744 uart6.init_struct = &uart6_init_struct;
745 uart6_init_struct.conf = &usart6_config;
746
747 // Create threads
748#if USE_UART6_RX
749 uart6_init_struct.rx_mtx = &uart6_rx_mtx;
750 uart6_init_struct.rx_sem = &uart6_rx_sem;
751 chThdCreateStatic(wa_thd_uart6_rx, sizeof(wa_thd_uart6_rx),
752 NORMALPRIO + 1, thd_uart6_rx, NULL);
753#endif
754#if USE_UART6_TX
755 uart6_init_struct.tx_mtx = &uart6_tx_mtx;
756 uart6_init_struct.tx_sem = &uart6_tx_sem;
757 chThdCreateStatic(wa_thd_uart6_tx, sizeof(wa_thd_uart6_tx),
758 NORMALPRIO + 1, thd_uart6_tx, NULL);
759#endif
760
761#if defined UART6_GPIO_CTS && defined UART6_GPIO_PORT_CTS
762 uart6_init_struct.cts_pin = UART6_GPIO_CTS;
763 uart6_init_struct.cts_port = UART6_GPIO_PORT_CTS;
764#endif
765}
766
767#endif
768
769#if USE_UART7
770
771#ifndef UART7_BAUD
772#define UART7_BAUD SERIAL_DEFAULT_BITRATE
773#endif
774
775/* by default enable UART Tx and Rx */
776#ifndef USE_UART7_TX
777#define USE_UART7_TX TRUE
778#endif
779#ifndef USE_UART7_RX
780#define USE_UART7_RX TRUE
781#endif
782
783#ifndef UART7_CR1
784#define UART7_CR1 0
785#endif
786
787#ifndef UART7_CR2
788#define UART7_CR2 USART_CR2_STOP1_BITS
789#endif
790
791#ifndef UART7_CR3
792#define UART7_CR3 0
793#endif
794
795static SerialConfig usart7_config = {
796 UART7_BAUD, /* BITRATE */
797 UART7_CR1, /* USART CR1 */
798 UART7_CR2, /* USART CR2 */
799 UART7_CR3 /* USART CR3 */
800};
801
802static struct SerialInit uart7_init_struct = SERIAL_INIT_NULL;
803
804// Threads RX and TX
805#if USE_UART7_RX
806static MUTEX_DECL(uart7_rx_mtx);
807static SEMAPHORE_DECL(uart7_rx_sem, 0);
808
809static __attribute__((noreturn)) void thd_uart7_rx(void *arg)
810{
811 (void) arg;
812 chRegSetThreadName("uart7_rx");
813
814 while (TRUE) {
815 handle_uart_rx(&uart7);
816 }
817}
818
819static THD_WORKING_AREA(wa_thd_uart7_rx, UART_THREAD_STACK_SIZE);
820#endif
821
822#if USE_UART7_TX
823static MUTEX_DECL(uart7_tx_mtx);
824static SEMAPHORE_DECL(uart7_tx_sem, 0);
825
826static __attribute__((noreturn)) void thd_uart7_tx(void *arg)
827{
828 (void) arg;
829 chRegSetThreadName("uart7_tx");
830
831 while (TRUE) {
832 handle_uart_tx(&uart7);
833 }
834}
835static THD_WORKING_AREA(wa_thd_uart7_tx, UART_THREAD_STACK_SIZE);
836#endif
837
838void uart7_init(void)
839{
840 uart_periph_init(&uart7);
841
842 // Only set pin if enabled and not statically defined in board file
843#if USE_UART7_TX && defined UART7_GPIO_PORT_TX
844 gpio_setup_pin_af(UART7_GPIO_PORT_TX, UART7_GPIO_TX, UART7_GPIO_AF, TRUE);
845#endif
846#if USE_UART7_RX && defined UART7_GPIO_PORT_RX
847 gpio_setup_pin_af(UART7_GPIO_PORT_RX, UART7_GPIO_RX, UART7_GPIO_AF, FALSE);
848#endif
849
850 sdStart(&SD7, &usart7_config);
851 uart7.reg_addr = &SD7;
852 uart7.baudrate = UART7_BAUD;
853 uart7.init_struct = &uart7_init_struct;
854 uart7_init_struct.conf = &usart7_config;
855
856 // Create threads
857#if USE_UART7_RX
858 uart7_init_struct.rx_mtx = &uart7_rx_mtx;
859 uart7_init_struct.rx_sem = &uart7_rx_sem;
860 chThdCreateStatic(wa_thd_uart7_rx, sizeof(wa_thd_uart7_rx),
861 NORMALPRIO + 1, thd_uart7_rx, NULL);
862#endif
863#if USE_UART7_TX
864 uart7_init_struct.tx_mtx = &uart7_tx_mtx;
865 uart7_init_struct.tx_sem = &uart7_tx_sem;
866 chThdCreateStatic(wa_thd_uart7_tx, sizeof(wa_thd_uart7_tx),
867 NORMALPRIO + 1, thd_uart7_tx, NULL);
868#endif
869}
870
871#endif
872
873#if USE_UART8
874
875#ifndef UART8_BAUD
876#define UART8_BAUD SERIAL_DEFAULT_BITRATE
877#endif
878
879/* by default enable UART Tx and Rx */
880#ifndef USE_UART8_TX
881#define USE_UART8_TX TRUE
882#endif
883#ifndef USE_UART8_RX
884#define USE_UART8_RX TRUE
885#endif
886
887#ifndef UART8_CR1
888#define UART8_CR1 0
889#endif
890
891#ifndef UART8_CR2
892#define UART8_CR2 USART_CR2_STOP1_BITS
893#endif
894
895#ifndef UART8_CR3
896#define UART8_CR3 0
897#endif
898
899static SerialConfig usart8_config = {
900 UART8_BAUD, /* BITRATE */
901 UART8_CR1, /* USART CR1 */
902 UART8_CR2, /* USART CR2 */
903 UART8_CR3 /* USART CR3 */
904};
905
906static struct SerialInit uart8_init_struct = SERIAL_INIT_NULL;
907
908// Threads RX and TX
909#if USE_UART8_RX
910static MUTEX_DECL(uart8_rx_mtx);
911static SEMAPHORE_DECL(uart8_rx_sem, 0);
912
913static __attribute__((noreturn)) void thd_uart8_rx(void *arg)
914{
915 (void) arg;
916 chRegSetThreadName("uart8_rx");
917
918 while (TRUE) {
919 handle_uart_rx(&uart8);
920 }
921}
922
923static THD_WORKING_AREA(wa_thd_uart8_rx, UART_THREAD_STACK_SIZE);
924#endif
925
926#if USE_UART8_TX
927static MUTEX_DECL(uart8_tx_mtx);
928static SEMAPHORE_DECL(uart8_tx_sem, 0);
929
930static __attribute__((noreturn)) void thd_uart8_tx(void *arg)
931{
932 (void) arg;
933 chRegSetThreadName("uart8_tx");
934
935 while (TRUE) {
936 handle_uart_tx(&uart8);
937 }
938}
939static THD_WORKING_AREA(wa_thd_uart8_tx, UART_THREAD_STACK_SIZE);
940#endif
941
942void uart8_init(void)
943{
944 uart_periph_init(&uart8);
945
946 // Only set pin if enabled and not statically defined in board file
947#if USE_UART8_TX && defined UART8_GPIO_PORT_TX
948 gpio_setup_pin_af(UART8_GPIO_PORT_TX, UART8_GPIO_TX, UART8_GPIO_AF, TRUE);
949#endif
950#if USE_UART8_RX && defined UART8_GPIO_PORT_RX
951 gpio_setup_pin_af(UART8_GPIO_PORT_RX, UART8_GPIO_RX, UART8_GPIO_AF, FALSE);
952#endif
953
954 sdStart(&SD8, &usart8_config);
955 uart8.reg_addr = &SD8;
956 uart8.baudrate = UART8_BAUD;
957 uart8.init_struct = &uart8_init_struct;
958 uart8_init_struct.conf = &usart8_config;
959
960 // Create threads
961#if USE_UART8_RX
962 uart8_init_struct.rx_mtx = &uart8_rx_mtx;
963 uart8_init_struct.rx_sem = &uart8_rx_sem;
964 chThdCreateStatic(wa_thd_uart8_rx, sizeof(wa_thd_uart8_rx),
965 NORMALPRIO + 1, thd_uart8_rx, NULL);
966#endif
967#if USE_UART8_TX
968 uart8_init_struct.tx_mtx = &uart8_tx_mtx;
969 uart8_init_struct.tx_sem = &uart8_tx_sem;
970 chThdCreateStatic(wa_thd_uart8_tx, sizeof(wa_thd_uart8_tx),
971 NORMALPRIO + 1, thd_uart8_tx, NULL);
972#endif
973}
974
975#endif
976
977
978uint8_t uart_getch(struct uart_periph *p)
979{
980 //to keep compatibility with loop oriented paparazzi architecture, read is not blocking
981 //struct SerialInit *init_struct = (struct SerialInit*)(p->init_struct);
982 //chSemWait (init_struct->rx_sem);
983 struct SerialInit *init_struct = (struct SerialInit *)(p->init_struct);
984 chMtxLock(init_struct->rx_mtx);
985 uint8_t ret = p->rx_buf[p->rx_extract_idx];
986 p->rx_extract_idx = (p->rx_extract_idx + 1) % UART_RX_BUFFER_SIZE;
987 chMtxUnlock(init_struct->rx_mtx);
988 return ret;
989}
990
994void uart_periph_set_baudrate(struct uart_periph *p, uint32_t baud)
995{
996 struct SerialInit *init_struct = (struct SerialInit *)(p->init_struct);
997 SerialConfig *conf = init_struct->conf;
998 // set new baudrate
999 conf->speed = baud;
1000 p->baudrate = baud;
1001 // restart periph
1002 sdStop((SerialDriver *)(p->reg_addr));
1003 sdStart((SerialDriver *)(p->reg_addr), conf);
1004}
1005
1009void uart_periph_set_mode(struct uart_periph *p __attribute__((unused)), bool tx_enabled __attribute__((unused)),
1010 bool rx_enabled __attribute__((unused)), bool hw_flow_control __attribute__((unused))) {}
1011#if defined(STM32H7XX)
1012#define __USART_CR1_M USART_CR1_M0
1013#elif defined(STM32F7XX)
1014#define __USART_CR1_M USART_CR1_M_0
1015#elif defined(STM32F1XX) || defined (STM32F3XX) || defined(STM32F4XX)
1016#define __USART_CR1_M USART_CR1_M
1017#else
1018#error Unsupported board
1019#endif
1020
1024void uart_periph_set_bits_stop_parity(struct uart_periph *p,
1025 uint8_t bits, uint8_t stop, uint8_t parity)
1026{
1027 struct SerialInit *init_struct = (struct SerialInit *)(p->init_struct);
1028 SerialConfig *conf = init_struct->conf;
1029
1030 /* Configure USART parity and data bits */
1031 if (parity == UPARITY_EVEN) {
1032 conf->cr1 |= USART_CR1_PCE; // set parity control bit
1033 conf->cr1 &= ~USART_CR1_PS; // clear parity selection bit
1034 if (bits == UBITS_7) {
1035 conf->cr1 &= ~__USART_CR1_M; // clear word length bit
1036 } else { // 8 data bits by default
1037 conf->cr1 |= __USART_CR1_M; // set word length bit
1038 }
1039 } else if (parity == UPARITY_ODD) {
1040 conf->cr1 |= USART_CR1_PCE; // set parity control bit
1041 conf->cr1 |= USART_CR1_PS; // set parity selection bit
1042 if (bits == UBITS_7) {
1043 conf->cr1 &= ~__USART_CR1_M; // clear word length bit
1044 } else { // 8 data bits by default
1045 conf->cr1 |= __USART_CR1_M; // set word length bit
1046 }
1047 } else { // 8 data bist, NO_PARITY by default
1048 conf->cr1 &= ~USART_CR1_PCE; // clear parity control bit
1049 conf->cr1 &= ~__USART_CR1_M; // clear word length bit
1050 }
1051 /* Configure USART stop bits */
1052 conf->cr2 &= ~USART_CR2_STOP; // clear stop bits
1053 if (stop == USTOP_2) {
1054 conf-> cr2 |= USART_CR2_STOP2_BITS; // set bits for 2 stops
1055 } else { // 1 stop bit by default
1056 conf-> cr2 |= USART_CR2_STOP1_BITS; // set bits for 1 stop
1057 }
1058
1059 sdStop((SerialDriver *)(p->reg_addr));
1060 sdStart((SerialDriver *)(p->reg_addr), conf);
1061}
1062
1063#if defined(STM32F7XX) || defined(STM32H7XX)
1067void uart_periph_invert_data_logic(struct uart_periph *p, bool invert_rx, bool invert_tx)
1068{
1069 struct SerialInit *init_struct = (struct SerialInit *)(p->init_struct);
1070 SerialConfig *conf = init_struct->conf;
1071 if (invert_rx) {
1072 conf->cr2 |= USART_CR2_RXINV; // set rxinv bit
1073 } else {
1074 conf->cr2 &= ~USART_CR2_RXINV; // clear rxinv bit
1075 }
1076 if (invert_tx) {
1077 conf->cr2 |= USART_CR2_TXINV; // set txinv bit
1078 } else {
1079 conf->cr2 &= ~USART_CR2_TXINV; // clear txinv bit
1080 }
1081 sdStop((SerialDriver *)(p->reg_addr));
1082 sdStart((SerialDriver *)(p->reg_addr), conf);
1083}
1084#endif
1085
1086// Check free space and set a positive value for fd if valid
1087// and lock driver with mutex
1088int uart_check_free_space(struct uart_periph *p, long *fd, uint16_t len)
1089{
1090 struct SerialInit *init_struct = (struct SerialInit *)(p->init_struct);
1091 int space = p->tx_extract_idx - p->tx_insert_idx - 1;
1092 if (space < 0) {
1093 space += UART_TX_BUFFER_SIZE;
1094 }
1095 if (space >= len) {
1096 *fd = 1;
1097 chMtxLock(init_struct->tx_mtx);
1098 return space;
1099 }
1100 return 0;
1101}
1102
1106void uart_put_byte(struct uart_periph *p, long fd, uint8_t data)
1107{
1108 struct SerialInit *init_struct = (struct SerialInit *)(p->init_struct);
1109 if (fd == 0) {
1110 // if fd is zero, assume the driver is not already locked
1111 chMtxLock(init_struct->tx_mtx);
1112 uint16_t temp = (p->tx_insert_idx + 1) % UART_TX_BUFFER_SIZE;
1113 if (temp == p->tx_extract_idx) {
1114 chMtxUnlock(init_struct->tx_mtx);
1115 return; // no room
1116 }
1117 p->tx_buf[p->tx_insert_idx] = data;
1118 p->tx_insert_idx = temp;
1119
1120 chMtxUnlock(init_struct->tx_mtx);
1121 // send signal to start transmission
1122 chSemSignal(init_struct->tx_sem);
1123 } else {
1124 // assume driver is locked and available space have been checked
1125 p->tx_buf[p->tx_insert_idx] = data;
1126 p->tx_insert_idx = (p->tx_insert_idx + 1) % UART_TX_BUFFER_SIZE;
1127 }
1128}
1129
1133void uart_put_buffer(struct uart_periph *p, long fd, const uint8_t *data, uint16_t len)
1134{
1135 struct SerialInit *init_struct = (struct SerialInit *)(p->init_struct);
1136 if (fd == 0) {
1137 // if fd is zero, assume the driver is not already locked
1138 // and available space should be checked
1139 chMtxLock(init_struct->tx_mtx);
1140 int16_t space = p->tx_extract_idx - p->tx_insert_idx;
1141 if (space <= 0) {
1142 space += UART_TX_BUFFER_SIZE;
1143 }
1144 if ((uint16_t)(space - 1) < len) {
1145 chMtxUnlock(init_struct->tx_mtx);
1146 return; // no room
1147 }
1148 }
1149 // insert data into buffer
1150 int i;
1151 for (i = 0; i < len; i++) {
1152 p->tx_buf[p->tx_insert_idx] = data[i];
1153 p->tx_insert_idx = (p->tx_insert_idx + 1) % UART_TX_BUFFER_SIZE;
1154 }
1155 // unlock if needed
1156 if (fd == 0) {
1157 chMtxUnlock(init_struct->tx_mtx);
1158 // send signal to start transmission
1159 chSemSignal(init_struct->tx_sem);
1160 }
1161}
1162
1163void uart_send_message(struct uart_periph *p, long fd)
1164{
1165 struct SerialInit *init_struct = (struct SerialInit *)(p->init_struct);
1166 // unlock driver in case it is not done (fd > 0)
1167 if (fd != 0) {
1168 chMtxUnlock(init_struct->tx_mtx);
1169 }
1170 // send signal to start transmission
1171 chSemSignal(init_struct->tx_sem);
1172}
1173
1174#endif // HAL_USE_SERIAL
1175
UART6_GPIO_RX
#define UART6_GPIO_RX
Definition apogee_1.0.h:131
UART1_GPIO_TX
#define UART1_GPIO_TX
Definition apogee_1.0.h:116
UART4_GPIO_PORT_RX
#define UART4_GPIO_PORT_RX
Definition apogee_1.0.h:124
UART1_GPIO_PORT_TX
#define UART1_GPIO_PORT_TX
Definition apogee_1.0.h:115
UART4_GPIO_RX
#define UART4_GPIO_RX
Definition apogee_1.0.h:125
UART6_GPIO_PORT_RX
#define UART6_GPIO_PORT_RX
Definition apogee_1.0.h:130
UART2_GPIO_PORT_RX
#define UART2_GPIO_PORT_RX
Definition apogee_1.0.h:119
UART6_GPIO_TX
#define UART6_GPIO_TX
Definition apogee_1.0.h:133
UART1_GPIO_PORT_RX
#define UART1_GPIO_PORT_RX
Definition apogee_1.0.h:113
UART6_GPIO_PORT_TX
#define UART6_GPIO_PORT_TX
Definition apogee_1.0.h:132
UART4_GPIO_TX
#define UART4_GPIO_TX
Definition apogee_1.0.h:127
UART1_GPIO_RX
#define UART1_GPIO_RX
Definition apogee_1.0.h:114
UART2_GPIO_RX
#define UART2_GPIO_RX
Definition apogee_1.0.h:120
UART4_GPIO_PORT_TX
#define UART4_GPIO_PORT_TX
Definition apogee_1.0.h:126
UNUSED
#define UNUSED(x)
Definition cc2500_frsky_x.c:12
UART3_GPIO_TX
#define UART3_GPIO_TX
Definition cc3d.h:52
UART3_GPIO_PORT_TX
#define UART3_GPIO_PORT_TX
Definition cc3d.h:51
UART3_GPIO_RX
#define UART3_GPIO_RX
Definition cc3d.h:50
UART3_GPIO_PORT_RX
#define UART3_GPIO_PORT_RX
Definition cc3d.h:49
gpio_setup_pin_af
void gpio_setup_pin_af(ioportid_t port, uint16_t pin, uint8_t af, bool is_output)
Setup a gpio for input or output with alternate function.
Definition gpio_arch.c:65
gpio_get
static uint8_t gpio_get(ioportid_t port, uint16_t pin)
Get level of a gpio.
Definition gpio_arch.h:94
THD_WORKING_AREA
static THD_WORKING_AREA(wa_thd_spi1, SPI_THREAD_STACK_SIZE)
MUTEX_DECL
static MUTEX_DECL(sys_time_mtx)
UART8_GPIO_PORT_RX
#define UART8_GPIO_PORT_RX
Definition chimera.h:391
UART7_GPIO_RX
#define UART7_GPIO_RX
Definition chimera.h:413
UART2_GPIO_TX
#define UART2_GPIO_TX
Definition chimera.h:364
UART7_GPIO_PORT_RX
#define UART7_GPIO_PORT_RX
Definition chimera.h:412
UART8_GPIO_PORT_TX
#define UART8_GPIO_PORT_TX
Definition chimera.h:389
UART8_GPIO_TX
#define UART8_GPIO_TX
Definition chimera.h:390
UART2_GPIO_PORT_TX
#define UART2_GPIO_PORT_TX
UART2 (with optional flow control activated by default)
Definition chimera.h:363
UART8_GPIO_RX
#define UART8_GPIO_RX
Definition chimera.h:392
UART3_GPIO_AF
#define UART3_GPIO_AF
Definition common_board.h:448
UART2_GPIO_AF
#define UART2_GPIO_AF
Definition common_board.h:432
UART7_GPIO_AF
#define UART7_GPIO_AF
Definition common_board.h:512
UART6_GPIO_AF
#define UART6_GPIO_AF
Definition common_board.h:496
UART1_GPIO_AF
#define UART1_GPIO_AF
UART defines.
Definition common_board.h:416
UART5_GPIO_AF
#define UART5_GPIO_AF
Definition common_board.h:480
UART8_GPIO_AF
#define UART8_GPIO_AF
Definition common_board.h:528
UART4_GPIO_AF
#define UART4_GPIO_AF
Definition common_board.h:464
UART6_GPIO_PORT_CTS
#define UART6_GPIO_PORT_CTS
Definition crazyflie.h:184
UART6_GPIO_CTS
#define UART6_GPIO_CTS
Definition crazyflie.h:185
UART5_GPIO_TX
#define UART5_GPIO_TX
Definition elle0_common.h:115
UART5_GPIO_PORT_TX
#define UART5_GPIO_PORT_TX
Definition elle0_common.h:114
UART5_GPIO_RX
#define UART5_GPIO_RX
Definition elle0_common.h:113
UART5_GPIO_PORT_RX
#define UART5_GPIO_PORT_RX
Definition elle0_common.h:112
gpio.h
Some architecture independent helper functions for GPIOs.
p
static float p[2][2]
Definition ins_alt_float.c:273
uart_put_byte
void uart_put_byte(struct uart_periph *periph, long fd, uint8_t data)
Definition uart_arch.c:306
uart_periph_set_bits_stop_parity
void uart_periph_set_bits_stop_parity(struct uart_periph *periph, uint8_t bits, uint8_t stop, uint8_t parity)
Definition uart_arch.c:296
uart_getch
uint8_t uart_getch(struct uart_periph *p)
Definition uart_arch.c:348
uart_periph_set_baudrate
void uart_periph_set_baudrate(struct uart_periph *periph, uint32_t baud)
Definition uart_arch.c:280
UART_TX_BUFFER_SIZE
#define UART_TX_BUFFER_SIZE
Definition uart_arch.h:34
UART_RX_BUFFER_SIZE
#define UART_RX_BUFFER_SIZE
Definition uart_arch.h:31
foo
uint16_t foo
Definition main_demo5.c:58
UART7_GPIO_PORT_TX
#define UART7_GPIO_PORT_TX
UART7 (Modem with optional flow control disabled by default)
Definition matekF765-WING.h:350
UART7_GPIO_TX
#define UART7_GPIO_TX
Definition matekF765-WING.h:351
fd
int fd
Definition serial.c:26
UBITS_7
#define UBITS_7
Definition serial_port.c:49
UPARITY_ODD
#define UPARITY_ODD
Definition serial_port.c:56
USTOP_2
#define USTOP_2
Definition serial_port.c:53
UPARITY_EVEN
#define UPARITY_EVEN
Definition serial_port.c:57
TRUE
#define TRUE
Definition std.h:4
FALSE
#define FALSE
Definition std.h:5
uart_periph_set_mode
void uart_periph_set_mode(struct uart_periph *p, bool tx_enabled, bool rx_enabled, bool hw_flow_control)
Definition uart_arch.c:92
uart_send_message
void WEAK uart_send_message(struct uart_periph *p, long fd)
Definition uart.c:170
uart_periph_init
void uart_periph_init(struct uart_periph *p)
Definition uart.c:126
uart_put_buffer
void WEAK uart_put_buffer(struct uart_periph *p, long fd, const uint8_t *data, uint16_t len)
Definition uart.c:161
uart_periph_invert_data_logic
void WEAK uart_periph_invert_data_logic(struct uart_periph *p, bool invert_rx, bool invert_tx)
Definition uart.c:194
uart_check_free_space
int WEAK uart_check_free_space(struct uart_periph *p, long *fd, uint16_t len)
Definition uart.c:151
uart_periph
UART peripheral.
Definition uart.h:72
uint16_t
unsigned short uint16_t
Typedef defining 16 bit unsigned short type.
Definition vl53l1_types.h:88
uint32_t
unsigned int uint32_t
Typedef defining 32 bit unsigned int type.
Definition vl53l1_types.h:78
int16_t
short int16_t
Typedef defining 16 bit short type.
Definition vl53l1_types.h:93
uint8_t
unsigned char uint8_t
Typedef defining 8 bit unsigned char type.
Definition vl53l1_types.h:98
SEMAPHORE_DECL
static SEMAPHORE_DECL(we_ukf_sem, 0)