Paparazzi UAS  v5.15_devel-88-gb3ad7fe
Paparazzi is a free software Unmanned Aircraft System.
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mcu_arch.c
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1 /*
2  * Copyright (C) 2013 AggieAir, A Remote Sensing Unmanned Aerial System for Scientific Applications
3  * Utah State University, http://aggieair.usu.edu/
4  *
5  * Michal Podhradsky (michal.podhradsky@aggiemail.usu.edu)
6  * Calvin Coopmans (c.r.coopmans@ieee.org)
7  *
8  * 2016 Gautier Hattenberger <gautier.hattenberger@enac.fr>
9  * 2016 Alexandre Bustico <alexandre.bustico@enac.fr>
10  *
11  * This file is part of paparazzi.
12  *
13  * paparazzi is free software; you can redistribute it and/or modify
14  * it under the terms of the GNU General Public License as published by
15  * the Free Software Foundation; either version 2, or (at your option)
16  * any later version.
17  *
18  * paparazzi is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with paparazzi; see the file COPYING. If not, write to
25  * the Free Software Foundation, 59 Temple Place - Suite 330,
26  * Boston, MA 02111-1307, USA.
27  */
36 /* ChibiOS includes */
37 #include "ch.h"
38 #include "hal.h"
39 /* Paparazzi includes */
40 #include "mcu.h"
41 
42 #if USE_HARD_FAULT_RECOVERY
43 
44 #if defined STM32F4 || defined STM32F7
45 #define BCKP_SECTION ".ram5"
46 #define IN_BCKP_SECTION(var) var __attribute__ ((section(BCKP_SECTION), aligned(8)))
47 #else
48 #error "No backup ram available"
49 #endif
50 IN_BCKP_SECTION(volatile bool hard_fault);
51 
52 /*
53  * Set hard fault handlers to trigger a soft reset
54  * This will set a flag that can be tested at startup
55  */
56 
57 CH_IRQ_HANDLER(HardFault_Handler)
58 {
59  hard_fault = true;
60  NVIC_SystemReset();
61 }
62 
63 CH_IRQ_HANDLER(NMI_Handler)
64 {
65  hard_fault = true;
66  NVIC_SystemReset();
67 }
68 
69 CH_IRQ_HANDLER(MemManage_Handler)
70 {
71  hard_fault = true;
72  NVIC_SystemReset();
73 }
74 
75 CH_IRQ_HANDLER(BusFault_Handler)
76 {
77  hard_fault = true;
78  NVIC_SystemReset();
79 }
80 
81 CH_IRQ_HANDLER(UsageFault_Handler)
82 {
83  hard_fault = true;
84  NVIC_SystemReset();
85 }
86 
87 bool recovering_from_hard_fault;
88 
89 // select correct register
90 #if defined STM32F4
91 #define __PWR_CSR PWR->CSR
92 #define __PWR_CSR_BRE PWR_CSR_BRE
93 #define __PWR_CSR_BRR PWR_CSR_BRR
94 #elif defined STM32F7
95 #define __PWR_CSR PWR->CSR1
96 #define __PWR_CSR_BRE PWR_CSR1_BRE
97 #define __PWR_CSR_BRR PWR_CSR1_BRR
98 #else
99 #error Hard fault recovery not supported
100 #endif
101 
102 #endif
103 
104 
105 /*
106  * SCB_VTOR has to be relocated if Luftboot is used
107  * The new SCB_VTOR location is defined in the board makefile
108  */
109 void mcu_arch_init(void)
110 {
111 #if LUFTBOOT
112  PRINT_CONFIG_MSG("We are running luftboot, the interrupt vector is being relocated.")
113  SCB->VTOR = CORTEX_VTOR_INIT;
114 #endif
115 
116  /*
117  * System initializations.
118  * - HAL initialization, this also initializes the configured device drivers
119  * and performs the board-specific initializations.
120  * - Kernel initialization, the main() function becomes a thread and the
121  * RTOS is active.
122  */
123  halInit();
124  chSysInit();
125 
126 #if USE_HARD_FAULT_RECOVERY
127  /* Backup domain SRAM enable, and with it, the regulator */
128 #if defined STM32F4 || defined STM32F7
129  RCC->AHB1ENR |= RCC_AHB1ENR_BKPSRAMEN;
130  __PWR_CSR |= __PWR_CSR_BRE;
131  while ((__PWR_CSR & __PWR_CSR_BRR) == 0) ; /* Waits until the regulator is stable */
132 #endif /* STM32F4 | STM32F7*/
133 
134  // test if last reset was a 'real' hard fault
135  recovering_from_hard_fault = false;
136  if (!(RCC->CSR & RCC_CSR_SFTRSTF)) {
137  // not coming from soft reset
138  hard_fault = false;
139  } else if ((RCC->CSR & RCC_CSR_SFTRSTF) && !hard_fault) {
140  // this is a soft reset, probably from a debug probe, so let's start in normal mode
141  hard_fault = false;
142  } else {
143  // else real hard fault
144  recovering_from_hard_fault = true;
145  hard_fault = false;
146  }
147  // *MANDATORY* clear of rcc bits
148  RCC->CSR = RCC_CSR_RMVF;
149  // end of reset bit probing
150 #endif /* USE_HARD_FAULT_RECOVERY */
151 
152 }
153 
void mcu_arch_init(void)
Definition: mcu_arch.c:109
#define SCB
Definition: LPC21xx.h:394
#define CORTEX_VTOR_INIT
Definition: chconf.h:636
PRINT_CONFIG_MSG("USE_INS_NAV_INIT defaulting to TRUE")
Arch independent mcu ( Micro Controller Unit ) utilities.