Paparazzi UAS  v5.15_devel-99-g2ff7410
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mt9v117.c
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1 /*
2  * Copyright (C) 2016 Freek van Tienen <freek.v.tienen@gmail.com>
3  *
4  * This file is part of Paparazzi.
5  *
6  * Paparazzi is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2, or (at your option)
9  * any later version.
10  *
11  * Paparazzi is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with paparazzi; see the file COPYING. If not, see
18  * <http://www.gnu.org/licenses/>.
19  *
20  */
21 
27 #include "std.h"
28 #include "mt9v117.h"
29 #include "mt9v117_regs.h"
31 
32 #include <stdio.h>
33 #include <unistd.h>
34 #include <fcntl.h>
35 #include <sys/ioctl.h>
36 #include <linux/i2c-dev.h>
37 #include <linux/videodev2.h>
38 #include <linux/v4l2-mediabus.h>
39 
40 /* Camera structure */
42  .output_size = {
43  .w = 240,
44  .h = 240
45  },
46  .sensor_size = {
47  .w = 320,
48  .h = 240,
49  },
50  .crop = {
51  .x = 40,
52  .y = 0,
53  .w = 240,
54  .h = 240
55  },
56  .dev_name = "/dev/video0",
57  .subdev_name = "/dev/v4l-subdev0",
58  .format = V4L2_PIX_FMT_UYVY,
59  .subdev_format = V4L2_MBUS_FMT_UYVY8_2X8,
60  .buf_cnt = 5,
61  .filters = 0,
62  .cv_listener = NULL,
63  .fps = MT9V117_TARGET_FPS,
64  .camera_intrinsics = {
65  .focal_x = MT9V117_FOCAL_X,
66  .focal_y = MT9V117_FOCAL_Y,
67  .center_x = MT9V117_CENTER_X,
68  .center_y = MT9V117_CENTER_Y,
69  .Dhane_k = MT9V117_DHANE_K
70  }
71 };
72 
73 struct mt9v117_t mt9v117 = {
74  .i2c_periph = &i2c0
75 };
76 
77 /* Patch lines */
78 //I2C_BUF_LEN must be higher then size of these patch lines
79 #define MT9V117_PATCH_LINE_NUM 13
80 static uint8_t patch_line1[] = {
81  0xf0, 0x00, 0x72, 0xcf, 0xff, 0x00, 0x3e, 0xd0, 0x92, 0x00,
82  0x71, 0xcf, 0xff, 0xff, 0xf2, 0x18, 0xb1, 0x10, 0x92, 0x05,
83  0xb1, 0x11, 0x92, 0x04, 0xb1, 0x12, 0x70, 0xcf, 0xff, 0x00,
84  0x30, 0xc0, 0x90, 0x00, 0x7f, 0xe0, 0xb1, 0x13, 0x70, 0xcf,
85  0xff, 0xff, 0xe7, 0x1c, 0x88, 0x36, 0x09, 0x0f, 0x00, 0xb3
86 };
87 
88 static uint8_t patch_line2[] = {
89  0xf0, 0x30, 0x69, 0x13, 0xe1, 0x80, 0xd8, 0x08, 0x20, 0xca,
90  0x03, 0x22, 0x71, 0xcf, 0xff, 0xff, 0xe5, 0x68, 0x91, 0x35,
91  0x22, 0x0a, 0x1f, 0x80, 0xff, 0xff, 0xf2, 0x18, 0x29, 0x05,
92  0x00, 0x3e, 0x12, 0x22, 0x11, 0x01, 0x21, 0x04, 0x0f, 0x81,
93  0x00, 0x00, 0xff, 0xf0, 0x21, 0x8c, 0xf0, 0x10, 0x1a, 0x22
94 };
95 
96 static uint8_t patch_line3[] = {
97  0xf0, 0x60, 0x10, 0x44, 0x12, 0x20, 0x11, 0x02, 0xf7, 0x87,
98  0x22, 0x4f, 0x03, 0x83, 0x1a, 0x20, 0x10, 0xc4, 0xf0, 0x09,
99  0xba, 0xae, 0x7b, 0x50, 0x1a, 0x20, 0x10, 0x84, 0x21, 0x45,
100  0x01, 0xc1, 0x1a, 0x22, 0x10, 0x44, 0x70, 0xcf, 0xff, 0x00,
101  0x3e, 0xd0, 0xb0, 0x60, 0xb0, 0x25, 0x7e, 0xe0, 0x78, 0xe0
102 };
103 
104 static uint8_t patch_line4[] = {
105  0xf0, 0x90, 0x71, 0xcf, 0xff, 0xff, 0xf2, 0x18, 0x91, 0x12,
106  0x72, 0xcf, 0xff, 0xff, 0xe7, 0x1c, 0x8a, 0x57, 0x20, 0x04,
107  0x0f, 0x80, 0x00, 0x00, 0xff, 0xf0, 0xe2, 0x80, 0x20, 0xc5,
108  0x01, 0x61, 0x20, 0xc5, 0x03, 0x22, 0xb1, 0x12, 0x71, 0xcf,
109  0xff, 0x00, 0x3e, 0xd0, 0xb1, 0x04, 0x7e, 0xe0, 0x78, 0xe0
110 };
111 
112 static uint8_t patch_line5[] = {
113  0xf0, 0xc0, 0x70, 0xcf, 0xff, 0xff, 0xe7, 0x1c, 0x88, 0x57,
114  0x71, 0xcf, 0xff, 0xff, 0xf2, 0x18, 0x91, 0x13, 0xea, 0x84,
115  0xb8, 0xa9, 0x78, 0x10, 0xf0, 0x03, 0xb8, 0x89, 0xb8, 0x8c,
116  0xb1, 0x13, 0x71, 0xcf, 0xff, 0x00, 0x30, 0xc0, 0xb1, 0x00,
117  0x7e, 0xe0, 0xc0, 0xf1, 0x09, 0x1e, 0x03, 0xc0, 0xc1, 0xa1
118 };
119 
120 static uint8_t patch_line6[] = {
121  0xf0, 0xf0, 0x75, 0x08, 0x76, 0x28, 0x77, 0x48, 0xc2, 0x40,
122  0xd8, 0x20, 0x71, 0xcf, 0x00, 0x03, 0x20, 0x67, 0xda, 0x02,
123  0x08, 0xae, 0x03, 0xa0, 0x73, 0xc9, 0x0e, 0x25, 0x13, 0xc0,
124  0x0b, 0x5e, 0x01, 0x60, 0xd8, 0x06, 0xff, 0xbc, 0x0c, 0xce,
125  0x01, 0x00, 0xd8, 0x00, 0xb8, 0x9e, 0x0e, 0x5a, 0x03, 0x20
126 };
127 
128 static uint8_t patch_line7[] = {
129  0xf1, 0x20, 0xd9, 0x01, 0xd8, 0x00, 0xb8, 0x9e, 0x0e, 0xb6,
130  0x03, 0x20, 0xd9, 0x01, 0x8d, 0x14, 0x08, 0x17, 0x01, 0x91,
131  0x8d, 0x16, 0xe8, 0x07, 0x0b, 0x36, 0x01, 0x60, 0xd8, 0x07,
132  0x0b, 0x52, 0x01, 0x60, 0xd8, 0x11, 0x8d, 0x14, 0xe0, 0x87,
133  0xd8, 0x00, 0x20, 0xca, 0x02, 0x62, 0x00, 0xc9, 0x03, 0xe0
134 };
135 
136 static uint8_t patch_line8[] = {
137  0xf1, 0x50, 0xc0, 0xa1, 0x78, 0xe0, 0xc0, 0xf1, 0x08, 0xb2,
138  0x03, 0xc0, 0x76, 0xcf, 0xff, 0xff, 0xe5, 0x40, 0x75, 0xcf,
139  0xff, 0xff, 0xe5, 0x68, 0x95, 0x17, 0x96, 0x40, 0x77, 0xcf,
140  0xff, 0xff, 0xe5, 0x42, 0x95, 0x38, 0x0a, 0x0d, 0x00, 0x01,
141  0x97, 0x40, 0x0a, 0x11, 0x00, 0x40, 0x0b, 0x0a, 0x01, 0x00
142 };
143 
144 static uint8_t patch_line9[] = {
145  0xf1, 0x80, 0x95, 0x17, 0xb6, 0x00, 0x95, 0x18, 0xb7, 0x00,
146  0x76, 0xcf, 0xff, 0xff, 0xe5, 0x44, 0x96, 0x20, 0x95, 0x15,
147  0x08, 0x13, 0x00, 0x40, 0x0e, 0x1e, 0x01, 0x20, 0xd9, 0x00,
148  0x95, 0x15, 0xb6, 0x00, 0xff, 0xa1, 0x75, 0xcf, 0xff, 0xff,
149  0xe7, 0x1c, 0x77, 0xcf, 0xff, 0xff, 0xe5, 0x46, 0x97, 0x40
150 };
151 
152 static uint8_t patch_line10[] = {
153  0xf1, 0xb0, 0x8d, 0x16, 0x76, 0xcf, 0xff, 0xff, 0xe5, 0x48,
154  0x8d, 0x37, 0x08, 0x0d, 0x00, 0x81, 0x96, 0x40, 0x09, 0x15,
155  0x00, 0x80, 0x0f, 0xd6, 0x01, 0x00, 0x8d, 0x16, 0xb7, 0x00,
156  0x8d, 0x17, 0xb6, 0x00, 0xff, 0xb0, 0xff, 0xbc, 0x00, 0x41,
157  0x03, 0xc0, 0xc0, 0xf1, 0x0d, 0x9e, 0x01, 0x00, 0xe8, 0x04
158 };
159 
160 static uint8_t patch_line11[] = {
161  0xf1, 0xe0, 0xff, 0x88, 0xf0, 0x0a, 0x0d, 0x6a, 0x01, 0x00,
162  0x0d, 0x8e, 0x01, 0x00, 0xe8, 0x7e, 0xff, 0x85, 0x0d, 0x72,
163  0x01, 0x00, 0xff, 0x8c, 0xff, 0xa7, 0xff, 0xb2, 0xd8, 0x00,
164  0x73, 0xcf, 0xff, 0xff, 0xf2, 0x40, 0x23, 0x15, 0x00, 0x01,
165  0x81, 0x41, 0xe0, 0x02, 0x81, 0x20, 0x08, 0xf7, 0x81, 0x34
166 };
167 
168 static uint8_t patch_line12[] = {
169  0xf2, 0x10, 0xa1, 0x40, 0xd8, 0x00, 0xc0, 0xd1, 0x7e, 0xe0,
170  0x53, 0x51, 0x30, 0x34, 0x20, 0x6f, 0x6e, 0x5f, 0x73, 0x74,
171  0x61, 0x72, 0x74, 0x5f, 0x73, 0x74, 0x72, 0x65, 0x61, 0x6d,
172  0x69, 0x6e, 0x67, 0x20, 0x25, 0x64, 0x20, 0x25, 0x64, 0x0a,
173  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
174 };
175 
176 static uint8_t patch_line13[] = {
177  0xf2, 0x40, 0xff, 0xff, 0xe8, 0x28, 0xff, 0xff, 0xf0, 0xe8,
178  0xff, 0xff, 0xe8, 0x08, 0xff, 0xff, 0xf1, 0x54
179 };
180 
181 /* Patch lines structure */
185 };
186 
188  {patch_line1, sizeof(patch_line1)},
189  {patch_line2, sizeof(patch_line2)},
190  {patch_line3, sizeof(patch_line3)},
191  {patch_line4, sizeof(patch_line4)},
192  {patch_line5, sizeof(patch_line5)},
193  {patch_line6, sizeof(patch_line6)},
194  {patch_line7, sizeof(patch_line7)},
195  {patch_line8, sizeof(patch_line8)},
196  {patch_line9, sizeof(patch_line9)},
197  {patch_line10, sizeof(patch_line10)},
198  {patch_line11, sizeof(patch_line11)},
199  {patch_line12, sizeof(patch_line12)},
200  {patch_line13, sizeof(patch_line13)}
201 };
202 
206 static void write_reg(struct mt9v117_t *mt, uint16_t addr, uint32_t val, uint16_t len)
207 {
208  mt->i2c_trans.buf[0] = addr >> 8;
209  mt->i2c_trans.buf[1] = addr & 0xFF;
210 
211  // Fix sigdness based on length
212  if (len == 1) {
213  mt->i2c_trans.buf[2] = val & 0xFF;
214  } else if (len == 2) {
215  mt->i2c_trans.buf[2] = (val >> 8) & 0xFF;
216  mt->i2c_trans.buf[3] = val & 0xFF;
217  } else if (len == 4) {
218  mt->i2c_trans.buf[2] = (val >> 24) & 0xFF;
219  mt->i2c_trans.buf[3] = (val >> 16) & 0xFF;
220  mt->i2c_trans.buf[4] = (val >> 8) & 0xFF;
221  mt->i2c_trans.buf[5] = val & 0xFF;
222  } else {
223  printf("[MT9V117] write_reg with incorrect length %d\r\n", len);
224  }
225 
226  // Transmit the buffer
228 }
229 
233 static uint32_t read_reg(struct mt9v117_t *mt, uint16_t addr, uint16_t len)
234 {
235  uint32_t ret = 0;
236  mt->i2c_trans.buf[0] = addr >> 8;
237  mt->i2c_trans.buf[1] = addr & 0xFF;
238 
239  // Transmit the buffer and receive back
241 
242  /* Fix sigdness */
243  for (uint8_t i = 0; i < len; i++) {
244  ret |= mt->i2c_trans.buf[len - i - 1] << (8 * i);
245  }
246  return ret;
247 }
248 
249 /* Write a byte to a var */
251 {
252  uint16_t addr = 0x8000 | (var << 10) | offset;
253  write_reg(mt, addr, val, len);
254 }
255 
256 /* Read a byte from a var */
258 {
259  uint16_t addr = 0x8000 | (var << 10) | offset;
260  return read_reg(mt, addr, len);
261 }
262 
263 static inline void mt9v117_write_patch(struct mt9v117_t *mt)
264 {
265  /* Errata item 2 */
266  write_reg(mt, 0x301a, 0x10d0, 2);
267  write_reg(mt, 0x31c0, 0x1404, 2);
268  write_reg(mt, 0x3ed8, 0x879c, 2);
269  write_reg(mt, 0x3042, 0x20e1, 2);
270  write_reg(mt, 0x30d4, 0x8020, 2);
271  write_reg(mt, 0x30c0, 0x0026, 2);
272  write_reg(mt, 0x301a, 0x10d4, 2);
273 
274  /* Errata item 6 */
275  write_var(mt, MT9V117_AE_TRACK_VAR, 0x0002, 0x00d3, 2);
276  write_var(mt, MT9V117_CAM_CTRL_VAR, 0x0078, 0x00a0, 2);
277  write_var(mt, MT9V117_CAM_CTRL_VAR, 0x0076, 0x0140, 2);
278 
279  /* Errata item 8 */
280  write_var(mt, MT9V117_LOW_LIGHT_VAR, 0x0004, 0x00fc, 2);
281  write_var(mt, MT9V117_LOW_LIGHT_VAR, 0x0038, 0x007f, 2);
282  write_var(mt, MT9V117_LOW_LIGHT_VAR, 0x003a, 0x007f, 2);
283  write_var(mt, MT9V117_LOW_LIGHT_VAR, 0x003c, 0x007f, 2);
284  write_var(mt, MT9V117_LOW_LIGHT_VAR, 0x0004, 0x00f4, 2);
285 
286  /* Patch 0403; Critical; Sensor optimization */
287  write_reg(mt, MT9V117_ACCESS_CTL_STAT, 0x0001, 2);
289 
290  /* Write patch */
291  for (uint8_t i = 0; i < MT9V117_PATCH_LINE_NUM; ++i) {
292  // Copy buffer
293  for (uint8_t j = 0; j < mt9v117_patch_lines[i].len; ++j) {
294  mt->i2c_trans.buf[j] = mt9v117_patch_lines[i].data[j];
295  }
296 
297  // Transmit the buffer
298  i2c_blocking_transmit(mt->i2c_periph, &mt->i2c_trans, mt->i2c_trans.slave_addr, mt9v117_patch_lines[i].len);
299  }
300 
306 
307  /* Wait for command OK */
308  for (uint8_t retries = 100; retries > 0; retries--) {
309  /* Wait 10ms */
310  usleep(10000);
311 
312  /* Check the command */
313  uint16_t cmd = read_reg(mt, MT9V117_COMMAND, 2);
314  if ((cmd & MT9V117_COMMAND_APPLY_PATCH) == 0) {
315  if ((cmd & MT9V117_COMMAND_OK) == 0) {
316  printf("[MT9V117] Applying patch failed (No OK)\r\n");
317  }
318  return;
319  }
320  }
321 
322  printf("[MT9V117] Applying patch failed after 10 retries\r\n");
323 }
324 
325 /* Configure the sensor */
326 static inline void mt9v117_config(struct mt9v117_t *mt)
327 {
338 
341 
344 
345  /* Set gain metric for 111.2 fps
346  * The final fps depends on the input clock
347  * (89.2fps on bebop) so a modification may be needed here */
350 
351  /* set crop window */
357 
358  /* Enable auto-stats mode */
367 }
368 
373 void mt9v117_init(struct mt9v117_t *mt)
374 {
375  /* bytes written to gpios/pwm */
376  int wc = 0;
377  /* Reset the device */
378  int gpio129 = open("/sys/class/gpio/gpio129/value", O_WRONLY | O_CREAT | O_TRUNC, 0666);
379  wc += write(gpio129, "0", 1);
380  wc += write(gpio129, "1", 1);
381  close(gpio129);
382 
383  if (wc != 2) {
384  printf("[MT9V117] Couldn't write to GPIO 129\n");
385  }
386 
387  /* Start PWM 9 (Which probably is the clock of the MT9V117) */
388  //#define BEBOP_CAMV_PWM_FREQ 43333333
389  int pwm9 = open("/sys/class/pwm/pwm_9/run", O_WRONLY | O_CREAT | O_TRUNC, 0666);
390  wc = 0;
391  wc += write(pwm9, "0", 1);
392  wc += write(pwm9, "1", 1);
393  close(pwm9);
394 
395  if (wc != 2) {
396  printf("[MT9V117] Couldn't write to PWM\n");
397  }
398 
399  //TODO: Make PWM and GPIO generic
400 
401  /* Wait 50ms */
402  usleep(50000);
403 
404  /* Setup i2c transaction */
406 
407  /* See if the device is there and correct */
408  uint16_t chip_id = read_reg(mt, MT9V117_CHIP_ID, 2);
409  if (chip_id != MT9V117_CHIP_ID_RESP) {
410  printf("[MT9V117] Didn't get correct response from CHIP_ID (expected: 0x%04X, got: 0x%04X)\r\n", MT9V117_CHIP_ID_RESP,
411  chip_id);
412  return;
413  }
414 
415  /* Reset the device with software */
418 
419  /* Wait 50ms */
420  usleep(50000);
421 
422  /* Apply MT9V117 software patch */
424 
425  /* Set basic settings */
428 
429  /* Set pixclk pad slew to 6 and data out pad slew to 1 */
430  write_reg(mt, MT9V117_PAD_SLEW, read_reg(mt, MT9V117_PAD_SLEW, 2) | 0x0600 | 0x0001, 2);
431 
432  /* Configure the MT9V117 sensor */
433  mt9v117_config(mt);
434 
435  /* Enable ITU656 */
439 
440  /* Set autoexposure luma */
442 
443  /* Apply the configuration */
446 
447  /* Wait for command OK */
448  for (uint8_t retries = 100; retries > 0; retries--) {
449  /* Wait 10ms */
450  usleep(10000);
451 
452  /* Check the command */
453  uint16_t cmd = read_reg(mt, MT9V117_COMMAND, 2);
454  if ((cmd & MT9V117_COMMAND_SET_STATE) == 0) {
455  if ((cmd & MT9V117_COMMAND_OK) == 0) {
456  printf("[MT9V117] Switching config failed (No OK)\r\n");
457  }
458 
459  // Successfully configured!
460  //printf("[MT9V117] Switching config OK\r\n");
461  return;
462  }
463  }
464 
465  printf("[MT9V117] Could not switch to new config\r\n");
466 }
struct video_config_t bottom_camera
Definition: mt9v117.c:41
#define MT9V117_CAM_SENSOR_CFG_X_ADDR_END_OFFSET
Definition: mt9v117_regs.h:38
unsigned short uint16_t
Definition: types.h:16
static uint8_t patch_line11[]
Definition: mt9v117.c:160
static uint8_t patch_line7[]
Definition: mt9v117.c:128
#define MT9V117_CAM_STAT_AWB_HG_WINDOW_XSTART_OFFSET
Definition: mt9v117_regs.h:74
#define MT9V117_CAM_SENSOR_CFG_X_ADDR_START_OFFSET
Definition: mt9v117_regs.h:36
#define MT9V117_CAM_STAT_AE_INITIAL_WINDOW_XEND_OFFSET
Definition: mt9v117_regs.h:80
#define MT9V117_CAM_STAT_AE_INITIAL_WINDOW_YEND_OFFSET
Definition: mt9v117_regs.h:81
#define MT9V117_AE_RULE_ALGO_OFFSET
Definition: mt9v117_regs.h:27
#define MT9V117_LOGICAL_ADDRESS_ACCESS
Definition: mt9v117_regs.h:20
#define MT9V117_ADDRESS
The i2c address of the chip.
Definition: mt9v117_regs.h:4
#define MT9V117_CAM_LL_START_GAIN_METRIC_OFFSET
Definition: mt9v117_regs.h:82
volatile uint8_t buf[I2C_BUF_LEN]
Transaction buffer With I2C_BUF_LEN number of bytes.
Definition: i2c.h:122
#define MT9V117_TARGET_FPS
Definition: mt9v117.h:35
#define MT9V117_CAM_OUTPUT_FORMAT_BT656_ENABLE
Definition: mt9v117_regs.h:70
#define MT9V117_CAM_STAT_AE_INITIAL_WINDOW_XSTART_OFFSET
Definition: mt9v117_regs.h:78
#define MT9V117_CAM_LL_STOP_GAIN_METRIC_OFFSET
Definition: mt9v117_regs.h:83
struct img_size_t output_size
Output image size.
Definition: video_device.h:56
#define MT9V117_AWB_VAR
Definition: mt9v117_regs.h:31
static void mt9v117_write_patch(struct mt9v117_t *mt)
Definition: mt9v117.c:263
#define MT9V117_AE_LUMA
Definition: mt9v117_regs.h:23
#define MT9V117_FOCAL_Y
Definition: mt9v117.h:43
Initialization and configuration of the MT9V117 CMOS Chip.
#define MT9V117_SYSMGR_NEXT_STATE_OFFSET
Definition: mt9v117_regs.h:85
#define MT9V117_COMMAND
Definition: mt9v117_regs.h:12
#define MT9V117_COMMAND_SET_STATE
Definition: mt9v117_regs.h:16
#define MT9V117_CAM_STAT_AWB_HG_WINDOW_XEND_OFFSET
Definition: mt9v117_regs.h:76
#define MT9V117_CAM_OUTPUT_FORMAT_OFFSET
Definition: mt9v117_regs.h:61
#define MT9V117_CAM_AET_SKIP_FRAMES
Definition: mt9v117_regs.h:22
#define MT9V117_PHYSICAL_ADDRESS_ACCESS
Definition: mt9v117_regs.h:19
#define MT9V117_PATCHLDR_LOADER_ADDRESS_OFFSET
Definition: mt9v117_regs.h:95
#define MT9V117_COMMAND_OK
Definition: mt9v117_regs.h:13
uint16_t len
Definition: mt9v117.c:184
static uint32_t read_reg(struct mt9v117_t *mt, uint16_t addr, uint16_t len)
Read multiple bytes from a register.
Definition: mt9v117.c:233
#define MT9V117_COMMAND_APPLY_PATCH
Definition: mt9v117_regs.h:17
static const struct mt9v117_patch_t mt9v117_patch_lines[MT9V117_PATCH_LINE_NUM]
Definition: mt9v117.c:187
static uint8_t patch_line3[]
Definition: mt9v117.c:96
#define MT9V117_CHIP_ID_RESP
Should be the response to CHIP_ID.
Definition: mt9v117_regs.h:8
#define MT9V117_CAM_SENSOR_CFG_Y_ADDR_END_OFFSET
Definition: mt9v117_regs.h:37
static void write_var(struct mt9v117_t *mt, uint16_t var, uint16_t offset, uint32_t val, uint16_t len)
Definition: mt9v117.c:250
struct mt9v117_t mt9v117
Definition: mt9v117.c:73
#define MT9V117_SYS_STATE_ENTER_CONFIG_CHANGE
Definition: mt9v117_regs.h:86
static uint8_t patch_line1[]
Definition: mt9v117.c:80
static void write_reg(struct mt9v117_t *mt, uint16_t addr, uint32_t val, uint16_t len)
Write multiple bytes to a single register.
Definition: mt9v117.c:206
#define MT9V117_CHIP_ID
Request the chip ID.
Definition: mt9v117_regs.h:7
#define MT9V117_AE_RULE_ALGO_AVERAGE
Definition: mt9v117_regs.h:28
bool i2c_blocking_transceive(struct i2c_periph *p, struct i2c_transaction *t, uint8_t s_addr, uint8_t len_w, uint16_t len_r)
Submit a write/read transaction and wait for it to complete.
Definition: i2c.c:385
#define MT9V117_ACCESS_CTL_STAT
Definition: mt9v117_regs.h:18
static uint8_t patch_line9[]
Definition: mt9v117.c:144
#define MT9V117_LOW_LIGHT_VAR
Definition: mt9v117_regs.h:33
#define MT9V117_AE_RULE_VAR
Definition: mt9v117_regs.h:26
static const float offset[]
#define MT9V117_CAM_SENSOR_CFG_Y_ADDR_START_OFFSET
Definition: mt9v117_regs.h:35
#define MT9V117_TARGET_LUMA
Definition: mt9v117.h:55
transaction set to done by user level
Definition: i2c.h:59
#define MT9V117_PATCHLDR_FIRMWARE_ID_OFFSET
Definition: mt9v117_regs.h:97
uint16_t val[TCOUPLE_NB]
#define MT9V117_CAM_SENSOR_CONTROL_Y_SKIP_EN
Definition: mt9v117_regs.h:48
#define MT9V117_CAM_OUTPUT_WIDTH_OFFSET
Definition: mt9v117_regs.h:59
#define MT9V117_PATCHLDR_VAR
Definition: mt9v117_regs.h:94
unsigned long uint32_t
Definition: types.h:18
#define MT9V117_SYSMGR_VAR
Definition: mt9v117_regs.h:84
#define MT9V117_RESET_MISC_CTRL
Definition: mt9v117_regs.h:9
#define MT9V117_DHANE_K
Definition: mt9v117.h:52
static uint8_t patch_line6[]
Definition: mt9v117.c:120
#define MT9V117_CAM_CROP_WINDOW_XOFFSET_OFFSET
Definition: mt9v117_regs.h:54
static uint8_t patch_line8[]
Definition: mt9v117.c:136
#define MT9V117_PAD_SLEW
Definition: mt9v117_regs.h:11
#define MT9V117_CAM_OUTPUT_HEIGHT_OFFSET
Definition: mt9v117_regs.h:60
void mt9v117_init(struct mt9v117_t *mt)
Initialisation of the Aptina MT9V117 CMOS sensor (1/6 inch VGA, bottom camera)
Definition: mt9v117.c:373
#define MT9V117_CAM_CROP_WINDOW_WIDTH_OFFSET
Definition: mt9v117_regs.h:56
enum I2CTransactionStatus status
Transaction status.
Definition: i2c.h:126
static uint8_t patch_line4[]
Definition: mt9v117.c:104
#define MT9V117_PATCH_LINE_NUM
Definition: mt9v117.c:79
#define MT9V117_CAM_STAT_AE_INITIAL_WINDOW_YSTART_OFFSET
Definition: mt9v117_regs.h:79
#define MT9V117_CAM_CROP_WINDOW_YOFFSET_OFFSET
Definition: mt9v117_regs.h:55
static uint8_t patch_line12[]
Definition: mt9v117.c:168
uint8_t slave_addr
Slave address.
Definition: i2c.h:104
#define MT9V117_FOCAL_X
Definition: mt9v117.h:40
static uint8_t patch_line2[]
Definition: mt9v117.c:88
#define MT9V117_CAM_SENSOR_CFG_CPIPE_LAST_ROW_OFFSET
Definition: mt9v117_regs.h:40
unsigned char uint8_t
Definition: types.h:14
#define MT9V117_CAM_STAT_AWB_HG_WINDOW_YSTART_OFFSET
Definition: mt9v117_regs.h:75
static uint8_t patch_line13[]
Definition: mt9v117.c:176
static uint8_t patch_line10[]
Definition: mt9v117.c:152
#define MT9V117_CAM_CROP_MODE_OFFSET
Definition: mt9v117_regs.h:58
#define MT9V117_CENTER_Y
Definition: mt9v117.h:49
static uint8_t patch_line5[]
Definition: mt9v117.c:112
#define MT9V117_AE_TRACK_JUMP_DIVISOR
Definition: mt9v117_regs.h:21
#define MT9V117_CAM_SENSOR_CFG_MAX_FDZONE_60_OFFSET
Definition: mt9v117_regs.h:43
#define MT9V117_AE_TRACK_VAR
Definition: mt9v117_regs.h:30
#define MT9V117_CAM_SENSOR_CONTROL_READ_MODE_OFFSET
Definition: mt9v117_regs.h:47
#define MT9V117_CAM_SENSOR_CFG_FRAME_LENGTH_LINES_OFFSET
Definition: mt9v117_regs.h:39
#define MT9V117_CAM_CROP_WINDOW_HEIGHT_OFFSET
Definition: mt9v117_regs.h:57
#define MT9V117_CAM_STAT_AWB_HG_WINDOW_YEND_OFFSET
Definition: mt9v117_regs.h:77
#define MT9V117_CAM_SENSOR_CFG_TARGET_FDZONE_60_OFFSET
Definition: mt9v117_regs.h:45
struct i2c_periph * i2c_periph
I2C peripheral used to communicate over.
Definition: mt9v117.h:59
uint16_t w
The width.
Definition: image.h:75
static uint32_t read_var(struct mt9v117_t *mt, uint16_t var, uint16_t offset, uint16_t len)
Definition: mt9v117.c:257
uint8_t * data
Definition: mt9v117.c:183
#define MT9V117_AWB_PIXEL_THRESHOLD_COUNT_OFFSET
Definition: mt9v117_regs.h:32
static void mt9v117_config(struct mt9v117_t *mt)
Definition: mt9v117.c:326
#define MT9V117_RESET_SOC_I2C
Definition: mt9v117_regs.h:10
#define MT9V117_CAM_CTRL_VAR
Definition: mt9v117_regs.h:34
V4L2 device settings.
Definition: video_device.h:55
bool i2c_blocking_transmit(struct i2c_periph *p, struct i2c_transaction *t, uint8_t s_addr, uint8_t len)
Submit a write only transaction and wait for it to complete.
Definition: i2c.c:343
#define MT9V117_CENTER_X
Definition: mt9v117.h:46
#define MT9V117_PATCHLDR_PATCH_ID_OFFSET
Definition: mt9v117_regs.h:96
struct i2c_transaction i2c_trans
I2C transaction for comminication with CMOS chip.
Definition: mt9v117.h:60