13 tdcp->
DMA_regs.CR &= ~STM32_DMA_CR_EN;
14 tdcp->
TIM_regs.CR1 &= ~STM32_TIM_CR1_CEN;
21 memcpy((
void *) &toTim->CR2, (
void *) &tdcp->
TIM_regs.CR2,
sizeof(tdcp->
TIM_regs) - 4U);
28 if (timer == STM32_TIM1) {
34 else if (timer == STM32_TIM2) {
40 else if (timer == STM32_TIM3) {
46 else if (timer == STM32_TIM4) {
52 else if (timer == STM32_TIM5) {
58 else if (timer == STM32_TIM8) {
64 else if (timer == STM32_TIM9) {
70 else if (timer == STM32_TIM10) {
76 else if (timer == STM32_TIM11) {
82 else if (timer == STM32_TIM12) {
88 else if (timer == STM32_TIM13) {
94 else if (timer == STM32_TIM14) {
100 else if (timer == STM32_TIM15) {
101 rccEnableTIM15(
true);
106 else if (timer == STM32_TIM16) {
107 rccEnableTIM16(
true);
112 else if (timer == STM32_TIM17) {
113 rccEnableTIM17(
true);
118 else if (timer == STM32_TIM18) {
119 rccEnableTIM18(
true);
124 else if (timer == STM32_TIM19) {
125 rccEnableTIM19(
true);
130 chSysHalt(
"not a valid timer");
const stm32_dma_stream_t * dmastream
DMA stream associated with peripheral or memory.
Structure representing a DMA driver.
void timerDmaCache_restore(const TimerDmaCache *tdcp, DMADriver *toDma, stm32_tim_t *toTim)
void timerDmaCache_cache(TimerDmaCache *tdcp, const DMADriver *fromDma, const stm32_tim_t *fromTim)
static void rccEnableAndReset(const stm32_tim_t *const timer)
DMA_Stream_TypeDef DMA_regs