22 osalDbgCheck((configp != NULL) && (timicp != NULL));
23 osalDbgAssert((configp->
prescaler >= 1) &&
25 "prescaler must be 1 .. 65536");
29 chMtxObjectInit(&timicp->
mut);
44 #if defined (STM32G0XX) || defined (STM32G4XX)|| defined (STM32H7XX)
46 TIM_TypeDef *cmsisTimer = (TIM_TypeDef *) timer;
47 cmsisTimer->CCMR3 = cmsisTimer->AF1 = cmsisTimer->AF2 =
48 cmsisTimer->TISEL = 0;
52 timer->ARR = configp->
arr ? configp->
arr : 0xffffffff;
53 timer->DCR = configp->
dcr;
55 chDbgAssert(__builtin_popcount(timicp->
channel) == 1,
"In pwm mode, only one channel must be set");
57 "In pwm mode, callback are not implemented, use PWMDriver instead");
60 timer->CCMR1 = (0b01 << TIM_CCMR1_CC1S_Pos) | (0b10 << TIM_CCMR1_CC2S_Pos);
62 timer->CCER = TIM_CCER_CC2P;
63 timer->SMCR = (0b101 << TIM_SMCR_TS_Pos) | (0b100 << TIM_SMCR_SMS_Pos);
64 timer->CCER |= (TIM_CCER_CC1E | TIM_CCER_CC2E);
67 timer->CCMR1 = (0b10 << TIM_CCMR1_CC1S_Pos) | (0b01 << TIM_CCMR1_CC2S_Pos);
69 timer->CCER = TIM_CCER_CC1P;
70 timer->SMCR = (0b110 << TIM_SMCR_TS_Pos) | (0b100 << TIM_SMCR_SMS_Pos);
71 timer->CCER |= (TIM_CCER_CC1E | TIM_CCER_CC2E);
74 timer->CCMR2 = (0b01 << TIM_CCMR2_CC3S_Pos) | (0b10 << TIM_CCMR2_CC4S_Pos);
76 timer->CCER = TIM_CCER_CC4P;
77 timer->SMCR = (0b101 << TIM_SMCR_TS_Pos) | (0b100 << TIM_SMCR_SMS_Pos);
78 timer->CCER |= (TIM_CCER_CC3E | TIM_CCER_CC4E);
81 timer->CCMR2 = (0b10 << TIM_CCMR2_CC3S_Pos) | (0b01 << TIM_CCMR2_CC4S_Pos);
83 timer->CCER = TIM_CCER_CC3P;
84 timer->SMCR = (0b110 << TIM_SMCR_TS_Pos) | (0b100 << TIM_SMCR_SMS_Pos);
85 timer->CCER |= (TIM_CCER_CC3E | TIM_CCER_CC4E);
88 chSysHalt(
"channel must be TIMIC_CH1 .. TIMIC_CH4");
121 timer->CCER |= TIM_CCER_CC1P;
124 timer->CCER |= (TIM_CCER_CC1P | TIM_CCER_CC1NP);
127 chSysHalt(
"No configuration given for CH1");
129 timer->CCMR1 |= (0b01 << TIM_CCMR1_CC1S_Pos);
130 timer->CCER |= TIM_CCER_CC1E;
131 timicp->
dier |= STM32_TIM_DIER_CC1IE;
139 timer->CCER |= TIM_CCER_CC2P;
142 timer->CCER |= (TIM_CCER_CC2P | TIM_CCER_CC2NP);
145 chSysHalt(
"No configuration given for CH2");
147 timer->CCMR1 |= (0b01 << TIM_CCMR1_CC2S_Pos);
148 timer->CCER |= TIM_CCER_CC2E;
149 timicp->
dier |= STM32_TIM_DIER_CC2IE;
157 timer->CCER |= TIM_CCER_CC3P;
160 timer->CCER |= (TIM_CCER_CC3P | TIM_CCER_CC3NP);
163 chSysHalt(
"No configuration given for CH3");
165 timer->CCMR2 |= (0b01 << TIM_CCMR2_CC3S_Pos);
166 timer->CCER |= TIM_CCER_CC3E;
167 timicp->
dier |= STM32_TIM_DIER_CC3IE;
175 timer->CCER |= TIM_CCER_CC4P;
178 timer->CCER |= (TIM_CCER_CC4P | TIM_CCER_CC4NP);
181 chSysHalt(
"No configuration given for CH4");
183 timer->CCMR2 |= (0b01 << TIM_CCMR2_CC4S_Pos);
184 timer->CCER |= TIM_CCER_CC4E;
185 timicp->
dier |= STM32_TIM_DIER_CC4IE;
188 chSysHalt(
"invalid mode");
194 timicp->
dier |= STM32_TIM_DIER_UIE;
202 osalDbgCheck(timicp != NULL);
205 osalDbgCheck(timer != NULL);
206 timer->CR1 = STM32_TIM_CR1_URS;
207 timer->EGR |= STM32_TIM_EGR_UG;
209 timer->DIER = timicp->
dier;
210 timer->CR1 = STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN;
216 osalDbgCheck(timicp != NULL);
219 osalDbgCheck(timer != NULL);
220 timer->CR1 &= ~TIM_CR1_CEN;
228 chMtxLock(&timicp->
mut);
231 chMtxUnlock(&timicp->
mut);
241 const stm32_tim_t *
const timer = timicp->
config->
timer;
244 if (timer == STM32_TIM1) {
249 #ifdef STM32_TIM1_UP_TIM10_NUMBER
252 #ifdef STM32_TIM1_CC_NUMBER
259 else if (timer == STM32_TIM2) {
269 else if (timer == STM32_TIM3) {
279 else if (timer == STM32_TIM4) {
289 else if (timer == STM32_TIM5) {
299 else if (timer == STM32_TIM8) {
304 #ifdef STM32_TIM8_UP_TIM13_NUMBER
307 #ifdef STM32_TIM8_CC_NUMBER
314 else if (timer == STM32_TIM9) {
320 else if (timer == STM32_TIM10) {
321 rccEnableTIM10(
true);
326 else if (timer == STM32_TIM11) {
327 rccEnableTIM11(
true);
332 else if (timer == STM32_TIM12) {
333 rccEnableTIM12(
true);
338 else if (timer == STM32_TIM13) {
339 rccEnableTIM13(
true);
344 else if (timer == STM32_TIM14) {
345 rccEnableTIM14(
true);
350 else if (timer == STM32_TIM15) {
351 rccEnableTIM15(
true);
356 else if (timer == STM32_TIM16) {
357 rccEnableTIM16(
true);
362 else if (timer == STM32_TIM17) {
363 rccEnableTIM17(
true);
368 else if (timer == STM32_TIM18) {
369 rccEnableTIM18(
true);
374 else if (timer == STM32_TIM19) {
375 rccEnableTIM19(
true);
380 chSysHalt(
"not a valid timer");
386 const stm32_tim_t *
const timer = timicp->
config->
timer;
388 if (timer == STM32_TIM1) {
394 else if (timer == STM32_TIM2) {
400 else if (timer == STM32_TIM3) {
406 else if (timer == STM32_TIM4) {
412 else if (timer == STM32_TIM5) {
418 else if (timer == STM32_TIM8) {
424 else if (timer == STM32_TIM9) {
430 else if (timer == STM32_TIM10) {
436 else if (timer == STM32_TIM11) {
442 else if (timer == STM32_TIM12) {
448 else if (timer == STM32_TIM13) {
454 else if (timer == STM32_TIM14) {
460 else if (timer == STM32_TIM15) {
466 else if (timer == STM32_TIM16) {
472 else if (timer == STM32_TIM17) {
478 else if (timer == STM32_TIM18) {
484 else if (timer == STM32_TIM19) {
490 chSysHalt(
"not a valid timer");
498 #ifndef STM32_INPUT_CAPTURE_USE_TIM1
499 #define STM32_INPUT_CAPTURE_USE_TIM1 false
502 #ifndef STM32_INPUT_CAPTURE_USE_TIM2
503 #define STM32_INPUT_CAPTURE_USE_TIM2 false
506 #ifndef STM32_INPUT_CAPTURE_USE_TIM3
507 #define STM32_INPUT_CAPTURE_USE_TIM3 false
510 #ifndef STM32_INPUT_CAPTURE_USE_TIM4
511 #define STM32_INPUT_CAPTURE_USE_TIM4 false
514 #ifndef STM32_INPUT_CAPTURE_USE_TIM5
515 #define STM32_INPUT_CAPTURE_USE_TIM5 false
518 #ifndef STM32_INPUT_CAPTURE_USE_TIM8
519 #define STM32_INPUT_CAPTURE_USE_TIM8 false
522 #ifndef STM32_INPUT_CAPTURE_SHARE_TIM1
523 #define STM32_INPUT_CAPTURE_SHARE_TIM1 false
526 #ifndef STM32_INPUT_CAPTURE_SHARE_TIM2
527 #define STM32_INPUT_CAPTURE_SHARE_TIM2 false
530 #ifndef STM32_INPUT_CAPTURE_SHARE_TIM3
531 #define STM32_INPUT_CAPTURE_SHARE_TIM3 false
534 #ifndef STM32_INPUT_CAPTURE_SHARE_TIM4
535 #define STM32_INPUT_CAPTURE_SHARE_TIM4 false
538 #ifndef STM32_INPUT_CAPTURE_SHARE_TIM5
539 #define STM32_INPUT_CAPTURE_SHARE_TIM5 false
542 #ifndef STM32_INPUT_CAPTURE_SHARE_TIM8
543 #define STM32_INPUT_CAPTURE_SHARE_TIM8 false
546 #ifndef STM32_INPUT_CAPTURE_ENABLE_TIM1_ISR
547 #define STM32_INPUT_CAPTURE_ENABLE_TIM1_ISR false
550 #ifndef STM32_INPUT_CAPTURE_ENABLE_TIM2_ISR
551 #define STM32_INPUT_CAPTURE_ENABLE_TIM2_ISR false
555 #ifndef STM32_INPUT_CAPTURE_ENABLE_TIM3_ISR
556 #define STM32_INPUT_CAPTURE_ENABLE_TIM3_ISR false
560 #ifndef STM32_INPUT_CAPTURE_ENABLE_TIM4_ISR
561 #define STM32_INPUT_CAPTURE_ENABLE_TIM4_ISR false
565 #ifndef STM32_INPUT_CAPTURE_ENABLE_TIM5_ISR
566 #define STM32_INPUT_CAPTURE_ENABLE_TIM5_ISR false
570 #ifndef STM32_INPUT_CAPTURE_ENABLE_TIM8_ISR
571 #define STM32_INPUT_CAPTURE_ENABLE_TIM8_ISR false
576 #if STM32_INPUT_CAPTURE_USE_TIM1 && (!STM32_INPUT_CAPTURE_SHARE_TIM1) && \
577 (STM32_GPT_USE_TIM1 || STM32_ICU_USE_TIM1 || STM32_PWM_USE_TIM1)
578 #error "STM32 INPUT_CAPTURE USE TIM1 but already used by GPT or ICU or PWM"
581 #if STM32_INPUT_CAPTURE_USE_TIM2 && (!STM32_INPUT_CAPTURE_SHARE_TIM2) && \
582 (STM32_GPT_USE_TIM2 || STM32_ICU_USE_TIM2 || STM32_PWM_USE_TIM2)
583 #error "STM32 INPUT_CAPTURE USE TIM2 but already used by GPT or ICU or PWM"
586 #if STM32_INPUT_CAPTURE_USE_TIM3 && (!STM32_INPUT_CAPTURE_SHARE_TIM3) && \
587 (STM32_GPT_USE_TIM3 || STM32_ICU_USE_TIM3 || STM32_PWM_USE_TIM3)
588 #error "STM32 INPUT_CAPTURE USE TIM3 but already used by GPT or ICU or PWM"
591 #if STM32_INPUT_CAPTURE_USE_TIM4 && (!STM32_INPUT_CAPTURE_SHARE_TIM4) && \
592 (STM32_GPT_USE_TIM4 || STM32_ICU_USE_TIM4 || STM32_PWM_USE_TIM4)
593 #error "STM32 INPUT_CAPTURE USE TIM4 but already used by GPT or ICU or PWM"
596 #if STM32_INPUT_CAPTURE_USE_TIM5 && (!STM32_INPUT_CAPTURE_SHARE_TIM5) && \
597 (STM32_GPT_USE_TIM5 || STM32_ICU_USE_TIM5 || STM32_PWM_USE_TIM5)
598 #error "STM32 INPUT_CAPTURE USE TIM5 but already used by GPT or ICU or PWM"
601 #if STM32_INPUT_CAPTURE_USE_TIM8 && (!STM32_INPUT_CAPTURE_SHARE_TIM8) && \
602 (STM32_GPT_USE_TIM8 || STM32_ICU_USE_TIM8 || STM32_PWM_USE_TIM8)
603 #error "STM32 INPUT_CAPTURE USE TIM8 but already used by GPT or ICU or PWM"
607 #if STM32_INPUT_CAPTURE_USE_TIM1 || defined(__DOXYGEN__)
608 #if STM32_INPUT_CAPTURE_ENABLE_TIM1_ISR
609 #if defined(STM32_TIM1_UP_TIM10_HANDLER)
615 OSAL_IRQ_HANDLER(STM32_TIM1_UP_TIM10_HANDLER) {
623 #elif defined(STM32_TIM1_UP_HANDLER)
624 OSAL_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
633 #error "no handler defined for TIM1"
636 #if !defined(STM32_TIM1_CC_HANDLER)
637 #error "STM32_TIM1_CC_HANDLER not defined"
644 OSAL_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) {
655 #if STM32_INPUT_CAPTURE_USE_TIM2 || defined(__DOXYGEN__)
656 #if STM32_INPUT_CAPTURE_ENABLE_TIM2_ISR
657 #if !defined(STM32_TIM2_HANDLER)
658 #error "STM32_TIM2_HANDLER not defined"
665 OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) {
676 #if STM32_INPUT_CAPTURE_USE_TIM3 || defined(__DOXYGEN__)
677 #if STM32_INPUT_CAPTURE_ENABLE_TIM3_ISR
678 #if !defined(STM32_TIM3_HANDLER)
679 #error "STM32_TIM3_HANDLER not defined"
686 OSAL_IRQ_HANDLER(STM32_TIM3_HANDLER) {
697 #if STM32_INPUT_CAPTURE_USE_TIM4 || defined(__DOXYGEN__)
698 #if STM32_INPUT_CAPTURE_ENABLE_TIM4_ISR
699 #if !defined(STM32_TIM4_HANDLER)
700 #error "STM32_TIM4_HANDLER not defined"
707 OSAL_IRQ_HANDLER(STM32_TIM4_HANDLER) {
718 #if STM32_INPUT_CAPTURE_USE_TIM5 || defined(__DOXYGEN__)
719 #if STM32_INPUT_CAPTURE_ENABLE_TIM5_ISR
720 #if !defined(STM32_TIM5_HANDLER)
721 #error "STM32_TIM5_HANDLER not defined"
728 OSAL_IRQ_HANDLER(STM32_TIM5_HANDLER) {
739 #if STM32_INPUT_CAPTURE_USE_TIM8 || defined(__DOXYGEN__)
740 #if STM32_INPUT_CAPTURE_ENABLE_TIM8_ISR
741 #if defined(STM32_TIM8_UP_TIM13_HANDLER)
747 OSAL_IRQ_HANDLER(STM32_TIM8_UP_TIM13_HANDLER) {
757 #if !defined(STM32_TIM8_CC_HANDLER)
758 #error "STM32_TIM8_CC_HANDLER not defined"
765 OSAL_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) {
782 sr &= (timer->DIER & STM32_TIM_DIER_IRQ_MASK);
786 if ((sr & STM32_TIM_SR_CC1IF) != 0)
790 if ((sr & STM32_TIM_SR_CC2IF) != 0)
794 if ((sr & STM32_TIM_SR_CC3IF) != 0)
798 if ((sr & STM32_TIM_SR_CC4IF) != 0)
802 if ((sr & STM32_TIM_SR_UIF) != 0)
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY
#define STM32_IRQ_TIM5_PRIORITY
#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY
#define STM32_IRQ_TIM2_PRIORITY
#define STM32_IRQ_TIM4_PRIORITY
#define STM32_IRQ_TIM3_PRIORITY
#define STM32_IRQ_TIM1_CC_PRIORITY
#define STM32_IRQ_TIM8_CC_PRIORITY
unsigned int uint32_t
Typedef defining 32 bit unsigned int type.