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max7456_regs.h
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2  * Copyright (C) 2013 Chris
3  *
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22 
30 #ifndef MAX7456_REGS_H
31 #define MAX7456_REGS_H
32 
33 //OSD REGISTER ADDRESSES
34 #define OSD_VM0_REG 0x00
35 #define OSD_VM1_REG 0x01
36 #define OSD_DMM_REG 0x04
37 #define OSD_DMAH_REG 0x05
38 #define OSD_DMAL_REG 0x06
39 #define OSD_DMDI_REG 0x07
40 #define OSD_OSDBL_REG 0x6C
41 #define OSD_OSDBL_REG_R 0xEC
42 #define OSD_STAT_REG 0xA0
43 
44 //OSD BIT POSITIONS
45 #define OSD_VIDEO_MODE_PAL (1<<6) // Default = NTSC
46 #define OSD_SYNC_INTERNAL ((1<<5)|(1<<4)) // Default = AUTO
47 #define OSD_SYNC_EXTERNAL ((1<<5) // Default = AUTO
48 #define OSD_IMAGE_ENABLE (1<<3) // Default = OSD OFF
49 #define OSD_REFRESH_ON_NEXT_VSYNC (1<<2) // Default = immediately refresh video
50 #define OSD_RESET (1<<1) // VM0 reg, hardware set to 0 after reset
51 #define OSD_VOUT_DISABLE (1<<0) // default= VIDEO OUT ENABLED
52 #define OSD_8BIT_MODE (1<<6) // default= 16 BIT MODE
53 #define OSD_BLINK_CHAR (1<<4) // default= No BLINKING
54 #define OSD_INVERT_PIXELS (1<<3) // default= No INVERSION
55 #define OSD_CLEAR_DISPLAY_MEMORY (1<<2) // DMM reg, default = 0
56 #define OSD_AUTO_INCREMENT_MODE (1<<0) // default = NO AUTO INCREMENT
57 
58 // MAX7456 VIDEO_MODE_0 register
59 #define VIDEO_MODE_0_WRITE 0x00
60 #define VIDEO_MODE_0_READ 0x80
61 #define VIDEO_MODE_0_40_PAL 0x40
62 #define VIDEO_MODE_0_20_NoAutoSync 0x20
63 #define VIDEO_MODE_0_10_SyncInt 0x10
64 #define VIDEO_MODE_0_08_EnOSD 0x08
65 #define VIDEO_MODE_0_04_UpdateVsync 0x04
66 #define VIDEO_MODE_0_02_Reset 0x02
67 #define VIDEO_MODE_0_01_EnVideo 0x01
68 // VIDEO MODE 0 bitmap
69 #define NTSC 0x00
70 #define PAL 0x40
71 #define AUTO_SYNC 0x00
72 #define EXT_SYNC 0x20
73 #define INT_SYNC 0x30
74 #define OSD_EN 0x08
75 #define VERT_SYNC_IMM 0x00
76 #define VERT_SYNC_VSYNC 0x04
77 #define SW_RESET 0x02
78 #define BUF_EN 0x00
79 #define BUF_DI 0x01
80 
81 // MAX7456 VIDEO_MODE_1 register
82 #define VIDEO_MODE_1_WRITE 0x01
83 #define VIDEO_MODE_1_READ 0x81
84 
85 // MAX7456 DM_MODE register
86 #define DM_MODE_WRITE 0x04
87 #define DM_MODE_READ 0x84
88 
89 // MAX7456 DM_ADDRH register
90 #define DM_ADDRH_WRITE 0x05
91 #define DM_ADDRH_READ 0x85
92 
93 // MAX7456 DM_ADDRL register
94 #define DM_ADDRL_WRITE 0x06
95 #define DM_ADDRL_READ 0x87
96 
97 // MAX7456 DM_CODE_IN register
98 #define DM_CODE_IN_WRITE 0x07
99 #define DM_CODE_IN_READ 0x87
100 
101 // MAX7456 DM_CODE_OUT register
102 #define DM_CODE_OUT_READ 0xB0
103 
104 // MAX7456 FM_MODE register
105 #define FM_MODE_WRITE 0x08
106 #define FM_MODE_READ 0x88
107 
108 // MAX7456 FM_ADDRH register
109 #define FM_ADDRH_WRITE 0x09
110 #define FM_ADDRH_READ 0x89
111 
112 // MAX7456 FM_ADDRL register
113 #define FM_ADDRL_WRITE 0x0A
114 #define FM_ADDRL_READ 0x8A
115 
116 // MAX7456 FM_DATA_IN register
117 #define FM_DATA_IN_WRITE 0x0B
118 #define FM_DATA_IN_READ 0x8B
119 
120 // MAX7456 FM_DATA_OUT register
121 #define FM_DATA_OUT_READ 0xC0
122 
123 // MAX7456 STATUS register
124 #define STATUS_READ 0xA0
125 #define STATUS_40_RESET_BUSY 0x40
126 #define STATUS_20_NVRAM_BUSY 0x20
127 #define STATUS_04_LOSS_OF_SYNC 0x04
128 #define STATUS_02_PAL_DETECTED 0x02
129 #define STATUS_01_NTSC_DETECTED 0x01
130 
131 // MAX7456 requires clearing OSD Black Level register bit 0x10 after reset
132 #define OSDBL_WR 0x6C
133 #define OSDBL_RD 0xEC
134 #define OSDBL_10_DisableAutoBlackLevel 0x10
135 
136 #endif //MAX7456_REGS_H