Paparazzi UAS
v7.0_unstable
Paparazzi is a free software Unmanned Aircraft System.
invensense2_regs.h
Go to the documentation of this file.
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/*
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* Copyright (C) 2022 Freek van Tienen <freek.v.tienen@gmail.com>
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*
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* This file is part of paparazzi.
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*
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* paparazzi is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* paparazzi is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with paparazzi; see the file COPYING. If not, write to
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* the Free Software Foundation, 59 Temple Place - Suite 330,
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* Boston, MA 02111-1307, USA.
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*/
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#ifndef INVENSENSE2_REGS_H
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#define INVENSENSE2_REGS_H
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#define INV2_BANK0 0x00U
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#define INV2_BANK1 0x01U
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#define INV2_BANK2 0x02U
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#define INV2_BANK3 0x03U
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#define INV2REG(b, r) ((((uint16_t)b) << 8)|(r))
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#define INV2_READ_FLAG 0x80
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//Register Map
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#define INV2REG_WHO_AM_I INV2REG(INV2_BANK0,0x00U)
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#define INV2REG_USER_CTRL INV2REG(INV2_BANK0,0x03U)
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# define BIT_USER_CTRL_I2C_MST_RESET 0x02
// reset I2C Master (only applicable if I2C_MST_EN bit is set)
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# define BIT_USER_CTRL_SRAM_RESET 0x04
// Reset (i.e. clear) FIFO buffer
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# define BIT_USER_CTRL_DMP_RESET 0x08
// Reset DMP
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# define BIT_USER_CTRL_I2C_IF_DIS 0x10
// Disable primary I2C interface and enable hal.spi->interface
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# define BIT_USER_CTRL_I2C_MST_EN 0x20
// Enable MPU to act as the I2C Master to external slave sensors
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# define BIT_USER_CTRL_FIFO_EN 0x40
// Enable FIFO operations
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# define BIT_USER_CTRL_DMP_EN 0x80
// Enable DMP operations
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#define INV2REG_LP_CONFIG INV2REG(INV2_BANK0,0x05U)
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#define INV2REG_PWR_MGMT_1 INV2REG(INV2_BANK0,0x06U)
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# define BIT_PWR_MGMT_1_CLK_INTERNAL 0x00
// clock set to internal 8Mhz oscillator
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# define BIT_PWR_MGMT_1_CLK_AUTO 0x01
// PLL with X axis gyroscope reference
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# define BIT_PWR_MGMT_1_CLK_STOP 0x07
// Stops the clock and keeps the timing generator in reset
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# define BIT_PWR_MGMT_1_TEMP_DIS 0x08
// disable temperature sensor
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# define BIT_PWR_MGMT_1_SLEEP 0x40
// put sensor into low power sleep mode
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# define BIT_PWR_MGMT_1_DEVICE_RESET 0x80
// reset entire device
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#define INV2REG_PWR_MGMT_2 INV2REG(INV2_BANK0,0x07U)
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#define INV2REG_INT_PIN_CFG INV2REG(INV2_BANK0,0x0FU)
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# define BIT_BYPASS_EN 0x02
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# define BIT_INT_RD_CLEAR 0x10
// clear the interrupt when any read occurs
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# define BIT_LATCH_INT_EN 0x20
// latch data ready pin
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#define INV2REG_INT_ENABLE INV2REG(INV2_BANK0,0x10U)
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# define BIT_PLL_RDY_EN 0x04
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#define INV2REG_INT_ENABLE_1 INV2REG(INV2_BANK0,0x11U)
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#define INV2REG_INT_ENABLE_2 INV2REG(INV2_BANK0,0x12U)
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#define INV2REG_INT_ENABLE_3 INV2REG(INV2_BANK0,0x13U)
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#define INV2REG_I2C_MST_STATUS INV2REG(INV2_BANK0,0x17U)
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#define INV2REG_INT_STATUS INV2REG(INV2_BANK0,0x19U)
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#define INV2REG_INT_STATUS_1 INV2REG(INV2_BANK0,0x1AU)
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#define INV2REG_INT_STATUS_2 INV2REG(INV2_BANK0,0x1BU)
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#define INV2REG_INT_STATUS_3 INV2REG(INV2_BANK0,0x1CU)
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#define INV2REG_DELAY_TIMEH INV2REG(INV2_BANK0,0x28U)
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#define INV2REG_DELAY_TIMEL INV2REG(INV2_BANK0,0x29U)
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#define INV2REG_ACCEL_XOUT_H INV2REG(INV2_BANK0,0x2DU)
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#define INV2REG_ACCEL_XOUT_L INV2REG(INV2_BANK0,0x2EU)
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#define INV2REG_ACCEL_YOUT_H INV2REG(INV2_BANK0,0x2FU)
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#define INV2REG_ACCEL_YOUT_L INV2REG(INV2_BANK0,0x30U)
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#define INV2REG_ACCEL_ZOUT_H INV2REG(INV2_BANK0,0x31U)
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#define INV2REG_ACCEL_ZOUT_L INV2REG(INV2_BANK0,0x32U)
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#define INV2REG_GYRO_XOUT_H INV2REG(INV2_BANK0,0x33U)
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#define INV2REG_GYRO_XOUT_L INV2REG(INV2_BANK0,0x34U)
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#define INV2REG_GYRO_YOUT_H INV2REG(INV2_BANK0,0x35U)
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#define INV2REG_GYRO_YOUT_L INV2REG(INV2_BANK0,0x36U)
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#define INV2REG_GYRO_ZOUT_H INV2REG(INV2_BANK0,0x37U)
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#define INV2REG_GYRO_ZOUT_L INV2REG(INV2_BANK0,0x38U)
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#define INV2REG_TEMP_OUT_H INV2REG(INV2_BANK0,0x39U)
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#define INV2REG_TEMP_OUT_L INV2REG(INV2_BANK0,0x3AU)
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#define INV2REG_EXT_SLV_SENS_DATA_00 INV2REG(INV2_BANK0,0x3BU)
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#define INV2REG_EXT_SLV_SENS_DATA_01 INV2REG(INV2_BANK0,0x3CU)
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#define INV2REG_EXT_SLV_SENS_DATA_02 INV2REG(INV2_BANK0,0x3DU)
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#define INV2REG_EXT_SLV_SENS_DATA_03 INV2REG(INV2_BANK0,0x3EU)
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#define INV2REG_EXT_SLV_SENS_DATA_04 INV2REG(INV2_BANK0,0x3FU)
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#define INV2REG_EXT_SLV_SENS_DATA_05 INV2REG(INV2_BANK0,0x40U)
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#define INV2REG_EXT_SLV_SENS_DATA_06 INV2REG(INV2_BANK0,0x41U)
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#define INV2REG_EXT_SLV_SENS_DATA_07 INV2REG(INV2_BANK0,0x42U)
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#define INV2REG_EXT_SLV_SENS_DATA_08 INV2REG(INV2_BANK0,0x43U)
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#define INV2REG_EXT_SLV_SENS_DATA_09 INV2REG(INV2_BANK0,0x44U)
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#define INV2REG_EXT_SLV_SENS_DATA_10 INV2REG(INV2_BANK0,0x45U)
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#define INV2REG_EXT_SLV_SENS_DATA_11 INV2REG(INV2_BANK0,0x46U)
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#define INV2REG_EXT_SLV_SENS_DATA_12 INV2REG(INV2_BANK0,0x47U)
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#define INV2REG_EXT_SLV_SENS_DATA_13 INV2REG(INV2_BANK0,0x48U)
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#define INV2REG_EXT_SLV_SENS_DATA_14 INV2REG(INV2_BANK0,0x49U)
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#define INV2REG_EXT_SLV_SENS_DATA_15 INV2REG(INV2_BANK0,0x4AU)
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#define INV2REG_EXT_SLV_SENS_DATA_16 INV2REG(INV2_BANK0,0x4BU)
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#define INV2REG_EXT_SLV_SENS_DATA_17 INV2REG(INV2_BANK0,0x4CU)
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#define INV2REG_EXT_SLV_SENS_DATA_18 INV2REG(INV2_BANK0,0x4DU)
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#define INV2REG_EXT_SLV_SENS_DATA_19 INV2REG(INV2_BANK0,0x4EU)
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#define INV2REG_EXT_SLV_SENS_DATA_20 INV2REG(INV2_BANK0,0x4FU)
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#define INV2REG_EXT_SLV_SENS_DATA_21 INV2REG(INV2_BANK0,0x50U)
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#define INV2REG_EXT_SLV_SENS_DATA_22 INV2REG(INV2_BANK0,0x51U)
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#define INV2REG_EXT_SLV_SENS_DATA_23 INV2REG(INV2_BANK0,0x52U)
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#define INV2REG_FIFO_EN_1 INV2REG(INV2_BANK0,0x66U)
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# define BIT_SLV3_FIFO_EN 0x08
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# define BIT_SLV2_FIFO_EN 0x04
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# define BIT_SLV1_FIFO_EN 0x02
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# define BIT_SLV0_FIFI_EN0 0x01
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#define INV2REG_FIFO_EN_2 INV2REG(INV2_BANK0,0x67U)
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# define BIT_ACCEL_FIFO_EN 0x10
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# define BIT_ZG_FIFO_EN 0x08
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# define BIT_YG_FIFO_EN 0x04
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# define BIT_XG_FIFO_EN 0x02
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# define BIT_TEMP_FIFO_EN 0x01
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#define INV2REG_FIFO_RST INV2REG(INV2_BANK0,0x68U)
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#define INV2REG_FIFO_MODE INV2REG(INV2_BANK0,0x69U)
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#define INV2REG_FIFO_COUNTH INV2REG(INV2_BANK0,0x70U)
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#define INV2REG_FIFO_COUNTL INV2REG(INV2_BANK0,0x71U)
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#define INV2REG_FIFO_R_W INV2REG(INV2_BANK0,0x72U)
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#define INV2REG_DATA_RDY_STATUS INV2REG(INV2_BANK0,0x74U)
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#define INV2REG_FIFO_CFG INV2REG(INV2_BANK0,0x76U)
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#define INV2REG_SELF_TEST_X_GYRO INV2REG(INV2_BANK1,0x02U)
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#define INV2REG_SELF_TEST_Y_GYRO INV2REG(INV2_BANK1,0x03U)
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#define INV2REG_SELF_TEST_Z_GYRO INV2REG(INV2_BANK1,0x04U)
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#define INV2REG_SELF_TEST_X_ACCEL INV2REG(INV2_BANK1,0x0EU)
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#define INV2REG_SELF_TEST_Y_ACCEL INV2REG(INV2_BANK1,0x0FU)
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#define INV2REG_SELF_TEST_Z_ACCEL INV2REG(INV2_BANK1,0x10U)
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#define INV2REG_XA_OFFS_H INV2REG(INV2_BANK1,0x14U)
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#define INV2REG_XA_OFFS_L INV2REG(INV2_BANK1,0x15U)
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#define INV2REG_YA_OFFS_H INV2REG(INV2_BANK1,0x17U)
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#define INV2REG_YA_OFFS_L INV2REG(INV2_BANK1,0x18U)
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#define INV2REG_ZA_OFFS_H INV2REG(INV2_BANK1,0x1AU)
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#define INV2REG_ZA_OFFS_L INV2REG(INV2_BANK1,0x1BU)
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#define INV2REG_TIMEBASE_CORRECTIO INV2REG(INV2_BANK1,0x28U)
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#define INV2REG_GYRO_SMPLRT_DIV INV2REG(INV2_BANK2,0x00U)
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#define INV2REG_GYRO_CONFIG_1 INV2REG(INV2_BANK2,0x01U)
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# define BIT_GYRO_NODLPF_9KHZ 0x00
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# define BIT_GYRO_DLPF_ENABLE 0x01
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# define GYRO_DLPF_CFG_229HZ 0x00
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# define GYRO_DLPF_CFG_188HZ 0x01
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# define GYRO_DLPF_CFG_154HZ 0x02
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# define GYRO_DLPF_CFG_73HZ 0x03
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# define GYRO_DLPF_CFG_35HZ 0x04
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# define GYRO_DLPF_CFG_17HZ 0x05
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# define GYRO_DLPF_CFG_9HZ 0x06
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# define GYRO_DLPF_CFG_377HZ 0x07
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# define GYRO_DLPF_CFG_SHIFT 0x03
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# define GYRO_FS_SEL_250DPS 0x00
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# define GYRO_FS_SEL_500DPS 0x01
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# define GYRO_FS_SEL_1000DPS 0x02
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# define GYRO_FS_SEL_2000DPS 0x03
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# define GYRO_FS_SEL_SHIFT 0x01
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#define INV2REG_GYRO_CONFIG_2 INV2REG(INV2_BANK2,0x02U)
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#define INV2REG_XG_OFFS_USRH INV2REG(INV2_BANK2,0x03U)
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#define INV2REG_XG_OFFS_USRL INV2REG(INV2_BANK2,0x04U)
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#define INV2REG_YG_OFFS_USRH INV2REG(INV2_BANK2,0x05U)
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#define INV2REG_YG_OFFS_USRL INV2REG(INV2_BANK2,0x06U)
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#define INV2REG_ZG_OFFS_USRH INV2REG(INV2_BANK2,0x07U)
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#define INV2REG_ZG_OFFS_USRL INV2REG(INV2_BANK2,0x08U)
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#define INV2REG_ODR_ALIGN_EN INV2REG(INV2_BANK2,0x09U)
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#define INV2REG_ACCEL_SMPLRT_DIV_1 INV2REG(INV2_BANK2,0x10U)
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#define INV2REG_ACCEL_SMPLRT_DIV_2 INV2REG(INV2_BANK2,0x11U)
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#define INV2REG_ACCEL_INTEL_CTRL INV2REG(INV2_BANK2,0x12U)
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#define INV2REG_ACCEL_WOM_THR INV2REG(INV2_BANK2,0x13U)
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#define INV2REG_ACCEL_CONFIG INV2REG(INV2_BANK2,0x14U)
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# define BIT_ACCEL_NODLPF_4_5KHZ 0x00
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# define BIT_ACCEL_DLPF_ENABLE 0x01
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# define ACCEL_DLPF_CFG_265HZ 0x00
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# define ACCEL_DLPF_CFG_136HZ 0x02
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# define ACCEL_DLPF_CFG_69HZ 0x03
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# define ACCEL_DLPF_CFG_34HZ 0x04
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# define ACCEL_DLPF_CFG_17HZ 0x05
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# define ACCEL_DLPF_CFG_8HZ 0x06
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# define ACCEL_DLPF_CFG_499HZ 0x07
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# define ACCEL_DLPF_CFG_SHIFT 0x03
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# define ACCEL_FS_SEL_2G 0x00
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# define ACCEL_FS_SEL_4G 0x01
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# define ACCEL_FS_SEL_8G 0x02
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# define ACCEL_FS_SEL_16G 0x03
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# define ACCEL_FS_SEL_SHIFT 0x01
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#define INV2REG_FSYNC_CONFIG INV2REG(INV2_BANK2,0x52U)
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# define FSYNC_CONFIG_EXT_SYNC_TEMP 0x01
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# define FSYNC_CONFIG_EXT_SYNC_GX 0x02
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# define FSYNC_CONFIG_EXT_SYNC_GY 0x03
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# define FSYNC_CONFIG_EXT_SYNC_GZ 0x04
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# define FSYNC_CONFIG_EXT_SYNC_AX 0x05
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# define FSYNC_CONFIG_EXT_SYNC_AY 0x06
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# define FSYNC_CONFIG_EXT_SYNC_AZ 0x07
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#define INV2REG_TEMP_CONFIG INV2REG(INV2_BANK2,0x53U)
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#define INV2REG_MOD_CTRL_USR INV2REG(INV2_BANK2,0x54U)
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#define INV2REG_I2C_MST_ODR_CONFIG INV2REG(INV2_BANK3,0x00U)
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#define INV2REG_I2C_MST_CTRL INV2REG(INV2_BANK3,0x01U)
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# define BIT_I2C_MST_P_NSR 0x10
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# define BIT_I2C_MST_CLK_400KHZ 0x0D
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#define INV2REG_I2C_MST_DELAY_CTRL INV2REG(INV2_BANK3,0x02U)
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# define BIT_I2C_SLV0_DLY_EN 0x01
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# define BIT_I2C_SLV1_DLY_EN 0x02
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# define BIT_I2C_SLV2_DLY_EN 0x04
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# define BIT_I2C_SLV3_DLY_EN 0x08
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#define INV2REG_I2C_SLV0_ADDR INV2REG(INV2_BANK3,0x03U)
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#define INV2REG_I2C_SLV0_REG INV2REG(INV2_BANK3,0x04U)
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#define INV2REG_I2C_SLV0_CTRL INV2REG(INV2_BANK3,0x05U)
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#define INV2REG_I2C_SLV0_DO INV2REG(INV2_BANK3,0x06U)
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#define INV2REG_I2C_SLV1_ADDR INV2REG(INV2_BANK3,0x07U)
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#define INV2REG_I2C_SLV1_REG INV2REG(INV2_BANK3,0x08U)
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#define INV2REG_I2C_SLV1_CTRL INV2REG(INV2_BANK3,0x09U)
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#define INV2REG_I2C_SLV1_DO INV2REG(INV2_BANK3,0x0AU)
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#define INV2REG_I2C_SLV2_ADDR INV2REG(INV2_BANK3,0x0BU)
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#define INV2REG_I2C_SLV2_REG INV2REG(INV2_BANK3,0x0CU)
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#define INV2REG_I2C_SLV2_CTRL INV2REG(INV2_BANK3,0x0DU)
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#define INV2REG_I2C_SLV2_DO INV2REG(INV2_BANK3,0x0EU)
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#define INV2REG_I2C_SLV3_ADDR INV2REG(INV2_BANK3,0x0FU)
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#define INV2REG_I2C_SLV3_REG INV2REG(INV2_BANK3,0x10U)
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#define INV2REG_I2C_SLV3_CTRL INV2REG(INV2_BANK3,0x11U)
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#define INV2REG_I2C_SLV3_DO INV2REG(INV2_BANK3,0x12U)
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#define INV2REG_I2C_SLV4_ADDR INV2REG(INV2_BANK3,0x13U)
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#define INV2REG_I2C_SLV4_REG INV2REG(INV2_BANK3,0x14U)
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#define INV2REG_I2C_SLV4_CTRL INV2REG(INV2_BANK3,0x15U)
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#define INV2REG_I2C_SLV4_DO INV2REG(INV2_BANK3,0x16U)
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#define INV2REG_I2C_SLV4_DI INV2REG(INV2_BANK3,0x17U)
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#define INV2REG_BANK_SEL 0x7F
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// WHOAMI values
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#define INV2_WHOAMI_ICM20648 0xe0
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#define INV2_WHOAMI_ICM20948 0xea
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#define INV2_WHOAMI_ICM20649 0xe1
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#endif
/* INVENSENSE2_REGS_H */
sw
airborne
peripherals
invensense2_regs.h
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