Paparazzi UAS  v7.0_unstable
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invensense2_regs.h File Reference

Register and address definitions for the Invensense V2 from ardupilot. More...

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Macros

#define INV2_BANK0   0x00U
 
#define INV2_BANK1   0x01U
 
#define INV2_BANK2   0x02U
 
#define INV2_BANK3   0x03U
 
#define INV2REG(b, r)   ((((uint16_t)b) << 8)|(r))
 
#define INV2_READ_FLAG   0x80
 
#define INV2REG_WHO_AM_I   INV2REG(INV2_BANK0,0x00U)
 
#define INV2REG_USER_CTRL   INV2REG(INV2_BANK0,0x03U)
 
#define BIT_USER_CTRL_I2C_MST_RESET   0x02
 
#define BIT_USER_CTRL_SRAM_RESET   0x04
 
#define BIT_USER_CTRL_DMP_RESET   0x08
 
#define BIT_USER_CTRL_I2C_IF_DIS   0x10
 
#define BIT_USER_CTRL_I2C_MST_EN   0x20
 
#define BIT_USER_CTRL_FIFO_EN   0x40
 
#define BIT_USER_CTRL_DMP_EN   0x80
 
#define INV2REG_LP_CONFIG   INV2REG(INV2_BANK0,0x05U)
 
#define INV2REG_PWR_MGMT_1   INV2REG(INV2_BANK0,0x06U)
 
#define BIT_PWR_MGMT_1_CLK_INTERNAL   0x00
 
#define BIT_PWR_MGMT_1_CLK_AUTO   0x01
 
#define BIT_PWR_MGMT_1_CLK_STOP   0x07
 
#define BIT_PWR_MGMT_1_TEMP_DIS   0x08
 
#define BIT_PWR_MGMT_1_SLEEP   0x40
 
#define BIT_PWR_MGMT_1_DEVICE_RESET   0x80
 
#define INV2REG_PWR_MGMT_2   INV2REG(INV2_BANK0,0x07U)
 
#define INV2REG_INT_PIN_CFG   INV2REG(INV2_BANK0,0x0FU)
 
#define BIT_BYPASS_EN   0x02
 
#define BIT_INT_RD_CLEAR   0x10
 
#define BIT_LATCH_INT_EN   0x20
 
#define INV2REG_INT_ENABLE   INV2REG(INV2_BANK0,0x10U)
 
#define BIT_PLL_RDY_EN   0x04
 
#define INV2REG_INT_ENABLE_1   INV2REG(INV2_BANK0,0x11U)
 
#define INV2REG_INT_ENABLE_2   INV2REG(INV2_BANK0,0x12U)
 
#define INV2REG_INT_ENABLE_3   INV2REG(INV2_BANK0,0x13U)
 
#define INV2REG_I2C_MST_STATUS   INV2REG(INV2_BANK0,0x17U)
 
#define INV2REG_INT_STATUS   INV2REG(INV2_BANK0,0x19U)
 
#define INV2REG_INT_STATUS_1   INV2REG(INV2_BANK0,0x1AU)
 
#define INV2REG_INT_STATUS_2   INV2REG(INV2_BANK0,0x1BU)
 
#define INV2REG_INT_STATUS_3   INV2REG(INV2_BANK0,0x1CU)
 
#define INV2REG_DELAY_TIMEH   INV2REG(INV2_BANK0,0x28U)
 
#define INV2REG_DELAY_TIMEL   INV2REG(INV2_BANK0,0x29U)
 
#define INV2REG_ACCEL_XOUT_H   INV2REG(INV2_BANK0,0x2DU)
 
#define INV2REG_ACCEL_XOUT_L   INV2REG(INV2_BANK0,0x2EU)
 
#define INV2REG_ACCEL_YOUT_H   INV2REG(INV2_BANK0,0x2FU)
 
#define INV2REG_ACCEL_YOUT_L   INV2REG(INV2_BANK0,0x30U)
 
#define INV2REG_ACCEL_ZOUT_H   INV2REG(INV2_BANK0,0x31U)
 
#define INV2REG_ACCEL_ZOUT_L   INV2REG(INV2_BANK0,0x32U)
 
#define INV2REG_GYRO_XOUT_H   INV2REG(INV2_BANK0,0x33U)
 
#define INV2REG_GYRO_XOUT_L   INV2REG(INV2_BANK0,0x34U)
 
#define INV2REG_GYRO_YOUT_H   INV2REG(INV2_BANK0,0x35U)
 
#define INV2REG_GYRO_YOUT_L   INV2REG(INV2_BANK0,0x36U)
 
#define INV2REG_GYRO_ZOUT_H   INV2REG(INV2_BANK0,0x37U)
 
#define INV2REG_GYRO_ZOUT_L   INV2REG(INV2_BANK0,0x38U)
 
#define INV2REG_TEMP_OUT_H   INV2REG(INV2_BANK0,0x39U)
 
#define INV2REG_TEMP_OUT_L   INV2REG(INV2_BANK0,0x3AU)
 
#define INV2REG_EXT_SLV_SENS_DATA_00   INV2REG(INV2_BANK0,0x3BU)
 
#define INV2REG_EXT_SLV_SENS_DATA_01   INV2REG(INV2_BANK0,0x3CU)
 
#define INV2REG_EXT_SLV_SENS_DATA_02   INV2REG(INV2_BANK0,0x3DU)
 
#define INV2REG_EXT_SLV_SENS_DATA_03   INV2REG(INV2_BANK0,0x3EU)
 
#define INV2REG_EXT_SLV_SENS_DATA_04   INV2REG(INV2_BANK0,0x3FU)
 
#define INV2REG_EXT_SLV_SENS_DATA_05   INV2REG(INV2_BANK0,0x40U)
 
#define INV2REG_EXT_SLV_SENS_DATA_06   INV2REG(INV2_BANK0,0x41U)
 
#define INV2REG_EXT_SLV_SENS_DATA_07   INV2REG(INV2_BANK0,0x42U)
 
#define INV2REG_EXT_SLV_SENS_DATA_08   INV2REG(INV2_BANK0,0x43U)
 
#define INV2REG_EXT_SLV_SENS_DATA_09   INV2REG(INV2_BANK0,0x44U)
 
#define INV2REG_EXT_SLV_SENS_DATA_10   INV2REG(INV2_BANK0,0x45U)
 
#define INV2REG_EXT_SLV_SENS_DATA_11   INV2REG(INV2_BANK0,0x46U)
 
#define INV2REG_EXT_SLV_SENS_DATA_12   INV2REG(INV2_BANK0,0x47U)
 
#define INV2REG_EXT_SLV_SENS_DATA_13   INV2REG(INV2_BANK0,0x48U)
 
#define INV2REG_EXT_SLV_SENS_DATA_14   INV2REG(INV2_BANK0,0x49U)
 
#define INV2REG_EXT_SLV_SENS_DATA_15   INV2REG(INV2_BANK0,0x4AU)
 
#define INV2REG_EXT_SLV_SENS_DATA_16   INV2REG(INV2_BANK0,0x4BU)
 
#define INV2REG_EXT_SLV_SENS_DATA_17   INV2REG(INV2_BANK0,0x4CU)
 
#define INV2REG_EXT_SLV_SENS_DATA_18   INV2REG(INV2_BANK0,0x4DU)
 
#define INV2REG_EXT_SLV_SENS_DATA_19   INV2REG(INV2_BANK0,0x4EU)
 
#define INV2REG_EXT_SLV_SENS_DATA_20   INV2REG(INV2_BANK0,0x4FU)
 
#define INV2REG_EXT_SLV_SENS_DATA_21   INV2REG(INV2_BANK0,0x50U)
 
#define INV2REG_EXT_SLV_SENS_DATA_22   INV2REG(INV2_BANK0,0x51U)
 
#define INV2REG_EXT_SLV_SENS_DATA_23   INV2REG(INV2_BANK0,0x52U)
 
#define INV2REG_FIFO_EN_1   INV2REG(INV2_BANK0,0x66U)
 
#define BIT_SLV3_FIFO_EN   0x08
 
#define BIT_SLV2_FIFO_EN   0x04
 
#define BIT_SLV1_FIFO_EN   0x02
 
#define BIT_SLV0_FIFI_EN0   0x01
 
#define INV2REG_FIFO_EN_2   INV2REG(INV2_BANK0,0x67U)
 
#define BIT_ACCEL_FIFO_EN   0x10
 
#define BIT_ZG_FIFO_EN   0x08
 
#define BIT_YG_FIFO_EN   0x04
 
#define BIT_XG_FIFO_EN   0x02
 
#define BIT_TEMP_FIFO_EN   0x01
 
#define INV2REG_FIFO_RST   INV2REG(INV2_BANK0,0x68U)
 
#define INV2REG_FIFO_MODE   INV2REG(INV2_BANK0,0x69U)
 
#define INV2REG_FIFO_COUNTH   INV2REG(INV2_BANK0,0x70U)
 
#define INV2REG_FIFO_COUNTL   INV2REG(INV2_BANK0,0x71U)
 
#define INV2REG_FIFO_R_W   INV2REG(INV2_BANK0,0x72U)
 
#define INV2REG_DATA_RDY_STATUS   INV2REG(INV2_BANK0,0x74U)
 
#define INV2REG_FIFO_CFG   INV2REG(INV2_BANK0,0x76U)
 
#define INV2REG_SELF_TEST_X_GYRO   INV2REG(INV2_BANK1,0x02U)
 
#define INV2REG_SELF_TEST_Y_GYRO   INV2REG(INV2_BANK1,0x03U)
 
#define INV2REG_SELF_TEST_Z_GYRO   INV2REG(INV2_BANK1,0x04U)
 
#define INV2REG_SELF_TEST_X_ACCEL   INV2REG(INV2_BANK1,0x0EU)
 
#define INV2REG_SELF_TEST_Y_ACCEL   INV2REG(INV2_BANK1,0x0FU)
 
#define INV2REG_SELF_TEST_Z_ACCEL   INV2REG(INV2_BANK1,0x10U)
 
#define INV2REG_XA_OFFS_H   INV2REG(INV2_BANK1,0x14U)
 
#define INV2REG_XA_OFFS_L   INV2REG(INV2_BANK1,0x15U)
 
#define INV2REG_YA_OFFS_H   INV2REG(INV2_BANK1,0x17U)
 
#define INV2REG_YA_OFFS_L   INV2REG(INV2_BANK1,0x18U)
 
#define INV2REG_ZA_OFFS_H   INV2REG(INV2_BANK1,0x1AU)
 
#define INV2REG_ZA_OFFS_L   INV2REG(INV2_BANK1,0x1BU)
 
#define INV2REG_TIMEBASE_CORRECTIO   INV2REG(INV2_BANK1,0x28U)
 
#define INV2REG_GYRO_SMPLRT_DIV   INV2REG(INV2_BANK2,0x00U)
 
#define INV2REG_GYRO_CONFIG_1   INV2REG(INV2_BANK2,0x01U)
 
#define BIT_GYRO_NODLPF_9KHZ   0x00
 
#define BIT_GYRO_DLPF_ENABLE   0x01
 
#define GYRO_DLPF_CFG_229HZ   0x00
 
#define GYRO_DLPF_CFG_188HZ   0x01
 
#define GYRO_DLPF_CFG_154HZ   0x02
 
#define GYRO_DLPF_CFG_73HZ   0x03
 
#define GYRO_DLPF_CFG_35HZ   0x04
 
#define GYRO_DLPF_CFG_17HZ   0x05
 
#define GYRO_DLPF_CFG_9HZ   0x06
 
#define GYRO_DLPF_CFG_377HZ   0x07
 
#define GYRO_DLPF_CFG_SHIFT   0x03
 
#define GYRO_FS_SEL_250DPS   0x00
 
#define GYRO_FS_SEL_500DPS   0x01
 
#define GYRO_FS_SEL_1000DPS   0x02
 
#define GYRO_FS_SEL_2000DPS   0x03
 
#define GYRO_FS_SEL_SHIFT   0x01
 
#define INV2REG_GYRO_CONFIG_2   INV2REG(INV2_BANK2,0x02U)
 
#define INV2REG_XG_OFFS_USRH   INV2REG(INV2_BANK2,0x03U)
 
#define INV2REG_XG_OFFS_USRL   INV2REG(INV2_BANK2,0x04U)
 
#define INV2REG_YG_OFFS_USRH   INV2REG(INV2_BANK2,0x05U)
 
#define INV2REG_YG_OFFS_USRL   INV2REG(INV2_BANK2,0x06U)
 
#define INV2REG_ZG_OFFS_USRH   INV2REG(INV2_BANK2,0x07U)
 
#define INV2REG_ZG_OFFS_USRL   INV2REG(INV2_BANK2,0x08U)
 
#define INV2REG_ODR_ALIGN_EN   INV2REG(INV2_BANK2,0x09U)
 
#define INV2REG_ACCEL_SMPLRT_DIV_1   INV2REG(INV2_BANK2,0x10U)
 
#define INV2REG_ACCEL_SMPLRT_DIV_2   INV2REG(INV2_BANK2,0x11U)
 
#define INV2REG_ACCEL_INTEL_CTRL   INV2REG(INV2_BANK2,0x12U)
 
#define INV2REG_ACCEL_WOM_THR   INV2REG(INV2_BANK2,0x13U)
 
#define INV2REG_ACCEL_CONFIG   INV2REG(INV2_BANK2,0x14U)
 
#define BIT_ACCEL_NODLPF_4_5KHZ   0x00
 
#define BIT_ACCEL_DLPF_ENABLE   0x01
 
#define ACCEL_DLPF_CFG_265HZ   0x00
 
#define ACCEL_DLPF_CFG_136HZ   0x02
 
#define ACCEL_DLPF_CFG_69HZ   0x03
 
#define ACCEL_DLPF_CFG_34HZ   0x04
 
#define ACCEL_DLPF_CFG_17HZ   0x05
 
#define ACCEL_DLPF_CFG_8HZ   0x06
 
#define ACCEL_DLPF_CFG_499HZ   0x07
 
#define ACCEL_DLPF_CFG_SHIFT   0x03
 
#define ACCEL_FS_SEL_2G   0x00
 
#define ACCEL_FS_SEL_4G   0x01
 
#define ACCEL_FS_SEL_8G   0x02
 
#define ACCEL_FS_SEL_16G   0x03
 
#define ACCEL_FS_SEL_SHIFT   0x01
 
#define INV2REG_FSYNC_CONFIG   INV2REG(INV2_BANK2,0x52U)
 
#define FSYNC_CONFIG_EXT_SYNC_TEMP   0x01
 
#define FSYNC_CONFIG_EXT_SYNC_GX   0x02
 
#define FSYNC_CONFIG_EXT_SYNC_GY   0x03
 
#define FSYNC_CONFIG_EXT_SYNC_GZ   0x04
 
#define FSYNC_CONFIG_EXT_SYNC_AX   0x05
 
#define FSYNC_CONFIG_EXT_SYNC_AY   0x06
 
#define FSYNC_CONFIG_EXT_SYNC_AZ   0x07
 
#define INV2REG_TEMP_CONFIG   INV2REG(INV2_BANK2,0x53U)
 
#define INV2REG_MOD_CTRL_USR   INV2REG(INV2_BANK2,0x54U)
 
#define INV2REG_I2C_MST_ODR_CONFIG   INV2REG(INV2_BANK3,0x00U)
 
#define INV2REG_I2C_MST_CTRL   INV2REG(INV2_BANK3,0x01U)
 
#define BIT_I2C_MST_P_NSR   0x10
 
#define BIT_I2C_MST_CLK_400KHZ   0x0D
 
#define INV2REG_I2C_MST_DELAY_CTRL   INV2REG(INV2_BANK3,0x02U)
 
#define BIT_I2C_SLV0_DLY_EN   0x01
 
#define BIT_I2C_SLV1_DLY_EN   0x02
 
#define BIT_I2C_SLV2_DLY_EN   0x04
 
#define BIT_I2C_SLV3_DLY_EN   0x08
 
#define INV2REG_I2C_SLV0_ADDR   INV2REG(INV2_BANK3,0x03U)
 
#define INV2REG_I2C_SLV0_REG   INV2REG(INV2_BANK3,0x04U)
 
#define INV2REG_I2C_SLV0_CTRL   INV2REG(INV2_BANK3,0x05U)
 
#define INV2REG_I2C_SLV0_DO   INV2REG(INV2_BANK3,0x06U)
 
#define INV2REG_I2C_SLV1_ADDR   INV2REG(INV2_BANK3,0x07U)
 
#define INV2REG_I2C_SLV1_REG   INV2REG(INV2_BANK3,0x08U)
 
#define INV2REG_I2C_SLV1_CTRL   INV2REG(INV2_BANK3,0x09U)
 
#define INV2REG_I2C_SLV1_DO   INV2REG(INV2_BANK3,0x0AU)
 
#define INV2REG_I2C_SLV2_ADDR   INV2REG(INV2_BANK3,0x0BU)
 
#define INV2REG_I2C_SLV2_REG   INV2REG(INV2_BANK3,0x0CU)
 
#define INV2REG_I2C_SLV2_CTRL   INV2REG(INV2_BANK3,0x0DU)
 
#define INV2REG_I2C_SLV2_DO   INV2REG(INV2_BANK3,0x0EU)
 
#define INV2REG_I2C_SLV3_ADDR   INV2REG(INV2_BANK3,0x0FU)
 
#define INV2REG_I2C_SLV3_REG   INV2REG(INV2_BANK3,0x10U)
 
#define INV2REG_I2C_SLV3_CTRL   INV2REG(INV2_BANK3,0x11U)
 
#define INV2REG_I2C_SLV3_DO   INV2REG(INV2_BANK3,0x12U)
 
#define INV2REG_I2C_SLV4_ADDR   INV2REG(INV2_BANK3,0x13U)
 
#define INV2REG_I2C_SLV4_REG   INV2REG(INV2_BANK3,0x14U)
 
#define INV2REG_I2C_SLV4_CTRL   INV2REG(INV2_BANK3,0x15U)
 
#define INV2REG_I2C_SLV4_DO   INV2REG(INV2_BANK3,0x16U)
 
#define INV2REG_I2C_SLV4_DI   INV2REG(INV2_BANK3,0x17U)
 
#define INV2REG_BANK_SEL   0x7F
 
#define INV2_WHOAMI_ICM20648   0xe0
 
#define INV2_WHOAMI_ICM20948   0xea
 
#define INV2_WHOAMI_ICM20649   0xe1
 

Detailed Description

Register and address definitions for the Invensense V2 from ardupilot.

Definition in file invensense2_regs.h.

Macro Definition Documentation

◆ ACCEL_DLPF_CFG_136HZ

#define ACCEL_DLPF_CFG_136HZ   0x02

Definition at line 181 of file invensense2_regs.h.

◆ ACCEL_DLPF_CFG_17HZ

#define ACCEL_DLPF_CFG_17HZ   0x05

Definition at line 184 of file invensense2_regs.h.

◆ ACCEL_DLPF_CFG_265HZ

#define ACCEL_DLPF_CFG_265HZ   0x00

Definition at line 180 of file invensense2_regs.h.

◆ ACCEL_DLPF_CFG_34HZ

#define ACCEL_DLPF_CFG_34HZ   0x04

Definition at line 183 of file invensense2_regs.h.

◆ ACCEL_DLPF_CFG_499HZ

#define ACCEL_DLPF_CFG_499HZ   0x07

Definition at line 186 of file invensense2_regs.h.

◆ ACCEL_DLPF_CFG_69HZ

#define ACCEL_DLPF_CFG_69HZ   0x03

Definition at line 182 of file invensense2_regs.h.

◆ ACCEL_DLPF_CFG_8HZ

#define ACCEL_DLPF_CFG_8HZ   0x06

Definition at line 185 of file invensense2_regs.h.

◆ ACCEL_DLPF_CFG_SHIFT

#define ACCEL_DLPF_CFG_SHIFT   0x03

Definition at line 187 of file invensense2_regs.h.

◆ ACCEL_FS_SEL_16G

#define ACCEL_FS_SEL_16G   0x03

Definition at line 191 of file invensense2_regs.h.

◆ ACCEL_FS_SEL_2G

#define ACCEL_FS_SEL_2G   0x00

Definition at line 188 of file invensense2_regs.h.

◆ ACCEL_FS_SEL_4G

#define ACCEL_FS_SEL_4G   0x01

Definition at line 189 of file invensense2_regs.h.

◆ ACCEL_FS_SEL_8G

#define ACCEL_FS_SEL_8G   0x02

Definition at line 190 of file invensense2_regs.h.

◆ ACCEL_FS_SEL_SHIFT

#define ACCEL_FS_SEL_SHIFT   0x01

Definition at line 192 of file invensense2_regs.h.

◆ BIT_ACCEL_DLPF_ENABLE

#define BIT_ACCEL_DLPF_ENABLE   0x01

Definition at line 179 of file invensense2_regs.h.

◆ BIT_ACCEL_FIFO_EN

#define BIT_ACCEL_FIFO_EN   0x10

Definition at line 120 of file invensense2_regs.h.

◆ BIT_ACCEL_NODLPF_4_5KHZ

#define BIT_ACCEL_NODLPF_4_5KHZ   0x00

Definition at line 178 of file invensense2_regs.h.

◆ BIT_BYPASS_EN

#define BIT_BYPASS_EN   0x02

Definition at line 60 of file invensense2_regs.h.

◆ BIT_GYRO_DLPF_ENABLE

#define BIT_GYRO_DLPF_ENABLE   0x01

Definition at line 150 of file invensense2_regs.h.

◆ BIT_GYRO_NODLPF_9KHZ

#define BIT_GYRO_NODLPF_9KHZ   0x00

Definition at line 149 of file invensense2_regs.h.

◆ BIT_I2C_MST_CLK_400KHZ

#define BIT_I2C_MST_CLK_400KHZ   0x0D

Definition at line 207 of file invensense2_regs.h.

◆ BIT_I2C_MST_P_NSR

#define BIT_I2C_MST_P_NSR   0x10

Definition at line 206 of file invensense2_regs.h.

◆ BIT_I2C_SLV0_DLY_EN

#define BIT_I2C_SLV0_DLY_EN   0x01

Definition at line 209 of file invensense2_regs.h.

◆ BIT_I2C_SLV1_DLY_EN

#define BIT_I2C_SLV1_DLY_EN   0x02

Definition at line 210 of file invensense2_regs.h.

◆ BIT_I2C_SLV2_DLY_EN

#define BIT_I2C_SLV2_DLY_EN   0x04

Definition at line 211 of file invensense2_regs.h.

◆ BIT_I2C_SLV3_DLY_EN

#define BIT_I2C_SLV3_DLY_EN   0x08

Definition at line 212 of file invensense2_regs.h.

◆ BIT_INT_RD_CLEAR

#define BIT_INT_RD_CLEAR   0x10

Definition at line 61 of file invensense2_regs.h.

◆ BIT_LATCH_INT_EN

#define BIT_LATCH_INT_EN   0x20

Definition at line 62 of file invensense2_regs.h.

◆ BIT_PLL_RDY_EN

#define BIT_PLL_RDY_EN   0x04

Definition at line 64 of file invensense2_regs.h.

◆ BIT_PWR_MGMT_1_CLK_AUTO

#define BIT_PWR_MGMT_1_CLK_AUTO   0x01

Definition at line 53 of file invensense2_regs.h.

◆ BIT_PWR_MGMT_1_CLK_INTERNAL

#define BIT_PWR_MGMT_1_CLK_INTERNAL   0x00

Definition at line 52 of file invensense2_regs.h.

◆ BIT_PWR_MGMT_1_CLK_STOP

#define BIT_PWR_MGMT_1_CLK_STOP   0x07

Definition at line 54 of file invensense2_regs.h.

◆ BIT_PWR_MGMT_1_DEVICE_RESET

#define BIT_PWR_MGMT_1_DEVICE_RESET   0x80

Definition at line 57 of file invensense2_regs.h.

◆ BIT_PWR_MGMT_1_SLEEP

#define BIT_PWR_MGMT_1_SLEEP   0x40

Definition at line 56 of file invensense2_regs.h.

◆ BIT_PWR_MGMT_1_TEMP_DIS

#define BIT_PWR_MGMT_1_TEMP_DIS   0x08

Definition at line 55 of file invensense2_regs.h.

◆ BIT_SLV0_FIFI_EN0

#define BIT_SLV0_FIFI_EN0   0x01

Definition at line 118 of file invensense2_regs.h.

◆ BIT_SLV1_FIFO_EN

#define BIT_SLV1_FIFO_EN   0x02

Definition at line 117 of file invensense2_regs.h.

◆ BIT_SLV2_FIFO_EN

#define BIT_SLV2_FIFO_EN   0x04

Definition at line 116 of file invensense2_regs.h.

◆ BIT_SLV3_FIFO_EN

#define BIT_SLV3_FIFO_EN   0x08

Definition at line 115 of file invensense2_regs.h.

◆ BIT_TEMP_FIFO_EN

#define BIT_TEMP_FIFO_EN   0x01

Definition at line 124 of file invensense2_regs.h.

◆ BIT_USER_CTRL_DMP_EN

#define BIT_USER_CTRL_DMP_EN   0x80

Definition at line 49 of file invensense2_regs.h.

◆ BIT_USER_CTRL_DMP_RESET

#define BIT_USER_CTRL_DMP_RESET   0x08

Definition at line 45 of file invensense2_regs.h.

◆ BIT_USER_CTRL_FIFO_EN

#define BIT_USER_CTRL_FIFO_EN   0x40

Definition at line 48 of file invensense2_regs.h.

◆ BIT_USER_CTRL_I2C_IF_DIS

#define BIT_USER_CTRL_I2C_IF_DIS   0x10

Definition at line 46 of file invensense2_regs.h.

◆ BIT_USER_CTRL_I2C_MST_EN

#define BIT_USER_CTRL_I2C_MST_EN   0x20

Definition at line 47 of file invensense2_regs.h.

◆ BIT_USER_CTRL_I2C_MST_RESET

#define BIT_USER_CTRL_I2C_MST_RESET   0x02

Definition at line 43 of file invensense2_regs.h.

◆ BIT_USER_CTRL_SRAM_RESET

#define BIT_USER_CTRL_SRAM_RESET   0x04

Definition at line 44 of file invensense2_regs.h.

◆ BIT_XG_FIFO_EN

#define BIT_XG_FIFO_EN   0x02

Definition at line 123 of file invensense2_regs.h.

◆ BIT_YG_FIFO_EN

#define BIT_YG_FIFO_EN   0x04

Definition at line 122 of file invensense2_regs.h.

◆ BIT_ZG_FIFO_EN

#define BIT_ZG_FIFO_EN   0x08

Definition at line 121 of file invensense2_regs.h.

◆ FSYNC_CONFIG_EXT_SYNC_AX

#define FSYNC_CONFIG_EXT_SYNC_AX   0x05

Definition at line 198 of file invensense2_regs.h.

◆ FSYNC_CONFIG_EXT_SYNC_AY

#define FSYNC_CONFIG_EXT_SYNC_AY   0x06

Definition at line 199 of file invensense2_regs.h.

◆ FSYNC_CONFIG_EXT_SYNC_AZ

#define FSYNC_CONFIG_EXT_SYNC_AZ   0x07

Definition at line 200 of file invensense2_regs.h.

◆ FSYNC_CONFIG_EXT_SYNC_GX

#define FSYNC_CONFIG_EXT_SYNC_GX   0x02

Definition at line 195 of file invensense2_regs.h.

◆ FSYNC_CONFIG_EXT_SYNC_GY

#define FSYNC_CONFIG_EXT_SYNC_GY   0x03

Definition at line 196 of file invensense2_regs.h.

◆ FSYNC_CONFIG_EXT_SYNC_GZ

#define FSYNC_CONFIG_EXT_SYNC_GZ   0x04

Definition at line 197 of file invensense2_regs.h.

◆ FSYNC_CONFIG_EXT_SYNC_TEMP

#define FSYNC_CONFIG_EXT_SYNC_TEMP   0x01

Definition at line 194 of file invensense2_regs.h.

◆ GYRO_DLPF_CFG_154HZ

#define GYRO_DLPF_CFG_154HZ   0x02

Definition at line 153 of file invensense2_regs.h.

◆ GYRO_DLPF_CFG_17HZ

#define GYRO_DLPF_CFG_17HZ   0x05

Definition at line 156 of file invensense2_regs.h.

◆ GYRO_DLPF_CFG_188HZ

#define GYRO_DLPF_CFG_188HZ   0x01

Definition at line 152 of file invensense2_regs.h.

◆ GYRO_DLPF_CFG_229HZ

#define GYRO_DLPF_CFG_229HZ   0x00

Definition at line 151 of file invensense2_regs.h.

◆ GYRO_DLPF_CFG_35HZ

#define GYRO_DLPF_CFG_35HZ   0x04

Definition at line 155 of file invensense2_regs.h.

◆ GYRO_DLPF_CFG_377HZ

#define GYRO_DLPF_CFG_377HZ   0x07

Definition at line 158 of file invensense2_regs.h.

◆ GYRO_DLPF_CFG_73HZ

#define GYRO_DLPF_CFG_73HZ   0x03

Definition at line 154 of file invensense2_regs.h.

◆ GYRO_DLPF_CFG_9HZ

#define GYRO_DLPF_CFG_9HZ   0x06

Definition at line 157 of file invensense2_regs.h.

◆ GYRO_DLPF_CFG_SHIFT

#define GYRO_DLPF_CFG_SHIFT   0x03

Definition at line 159 of file invensense2_regs.h.

◆ GYRO_FS_SEL_1000DPS

#define GYRO_FS_SEL_1000DPS   0x02

Definition at line 162 of file invensense2_regs.h.

◆ GYRO_FS_SEL_2000DPS

#define GYRO_FS_SEL_2000DPS   0x03

Definition at line 163 of file invensense2_regs.h.

◆ GYRO_FS_SEL_250DPS

#define GYRO_FS_SEL_250DPS   0x00

Definition at line 160 of file invensense2_regs.h.

◆ GYRO_FS_SEL_500DPS

#define GYRO_FS_SEL_500DPS   0x01

Definition at line 161 of file invensense2_regs.h.

◆ GYRO_FS_SEL_SHIFT

#define GYRO_FS_SEL_SHIFT   0x01

Definition at line 164 of file invensense2_regs.h.

◆ INV2_BANK0

#define INV2_BANK0   0x00U

Definition at line 31 of file invensense2_regs.h.

◆ INV2_BANK1

#define INV2_BANK1   0x01U

Definition at line 32 of file invensense2_regs.h.

◆ INV2_BANK2

#define INV2_BANK2   0x02U

Definition at line 33 of file invensense2_regs.h.

◆ INV2_BANK3

#define INV2_BANK3   0x03U

Definition at line 34 of file invensense2_regs.h.

◆ INV2_READ_FLAG

#define INV2_READ_FLAG   0x80

Definition at line 38 of file invensense2_regs.h.

◆ INV2_WHOAMI_ICM20648

#define INV2_WHOAMI_ICM20648   0xe0

Definition at line 238 of file invensense2_regs.h.

◆ INV2_WHOAMI_ICM20649

#define INV2_WHOAMI_ICM20649   0xe1

Definition at line 240 of file invensense2_regs.h.

◆ INV2_WHOAMI_ICM20948

#define INV2_WHOAMI_ICM20948   0xea

Definition at line 239 of file invensense2_regs.h.

◆ INV2REG

#define INV2REG (   b,
 
)    ((((uint16_t)b) << 8)|(r))

Definition at line 37 of file invensense2_regs.h.

◆ INV2REG_ACCEL_CONFIG

#define INV2REG_ACCEL_CONFIG   INV2REG(INV2_BANK2,0x14U)

Definition at line 177 of file invensense2_regs.h.

◆ INV2REG_ACCEL_INTEL_CTRL

#define INV2REG_ACCEL_INTEL_CTRL   INV2REG(INV2_BANK2,0x12U)

Definition at line 175 of file invensense2_regs.h.

◆ INV2REG_ACCEL_SMPLRT_DIV_1

#define INV2REG_ACCEL_SMPLRT_DIV_1   INV2REG(INV2_BANK2,0x10U)

Definition at line 173 of file invensense2_regs.h.

◆ INV2REG_ACCEL_SMPLRT_DIV_2

#define INV2REG_ACCEL_SMPLRT_DIV_2   INV2REG(INV2_BANK2,0x11U)

Definition at line 174 of file invensense2_regs.h.

◆ INV2REG_ACCEL_WOM_THR

#define INV2REG_ACCEL_WOM_THR   INV2REG(INV2_BANK2,0x13U)

Definition at line 176 of file invensense2_regs.h.

◆ INV2REG_ACCEL_XOUT_H

#define INV2REG_ACCEL_XOUT_H   INV2REG(INV2_BANK0,0x2DU)

Definition at line 76 of file invensense2_regs.h.

◆ INV2REG_ACCEL_XOUT_L

#define INV2REG_ACCEL_XOUT_L   INV2REG(INV2_BANK0,0x2EU)

Definition at line 77 of file invensense2_regs.h.

◆ INV2REG_ACCEL_YOUT_H

#define INV2REG_ACCEL_YOUT_H   INV2REG(INV2_BANK0,0x2FU)

Definition at line 78 of file invensense2_regs.h.

◆ INV2REG_ACCEL_YOUT_L

#define INV2REG_ACCEL_YOUT_L   INV2REG(INV2_BANK0,0x30U)

Definition at line 79 of file invensense2_regs.h.

◆ INV2REG_ACCEL_ZOUT_H

#define INV2REG_ACCEL_ZOUT_H   INV2REG(INV2_BANK0,0x31U)

Definition at line 80 of file invensense2_regs.h.

◆ INV2REG_ACCEL_ZOUT_L

#define INV2REG_ACCEL_ZOUT_L   INV2REG(INV2_BANK0,0x32U)

Definition at line 81 of file invensense2_regs.h.

◆ INV2REG_BANK_SEL

#define INV2REG_BANK_SEL   0x7F

Definition at line 235 of file invensense2_regs.h.

◆ INV2REG_DATA_RDY_STATUS

#define INV2REG_DATA_RDY_STATUS   INV2REG(INV2_BANK0,0x74U)

Definition at line 130 of file invensense2_regs.h.

◆ INV2REG_DELAY_TIMEH

#define INV2REG_DELAY_TIMEH   INV2REG(INV2_BANK0,0x28U)

Definition at line 74 of file invensense2_regs.h.

◆ INV2REG_DELAY_TIMEL

#define INV2REG_DELAY_TIMEL   INV2REG(INV2_BANK0,0x29U)

Definition at line 75 of file invensense2_regs.h.

◆ INV2REG_EXT_SLV_SENS_DATA_00

#define INV2REG_EXT_SLV_SENS_DATA_00   INV2REG(INV2_BANK0,0x3BU)

Definition at line 90 of file invensense2_regs.h.

◆ INV2REG_EXT_SLV_SENS_DATA_01

#define INV2REG_EXT_SLV_SENS_DATA_01   INV2REG(INV2_BANK0,0x3CU)

Definition at line 91 of file invensense2_regs.h.

◆ INV2REG_EXT_SLV_SENS_DATA_02

#define INV2REG_EXT_SLV_SENS_DATA_02   INV2REG(INV2_BANK0,0x3DU)

Definition at line 92 of file invensense2_regs.h.

◆ INV2REG_EXT_SLV_SENS_DATA_03

#define INV2REG_EXT_SLV_SENS_DATA_03   INV2REG(INV2_BANK0,0x3EU)

Definition at line 93 of file invensense2_regs.h.

◆ INV2REG_EXT_SLV_SENS_DATA_04

#define INV2REG_EXT_SLV_SENS_DATA_04   INV2REG(INV2_BANK0,0x3FU)

Definition at line 94 of file invensense2_regs.h.

◆ INV2REG_EXT_SLV_SENS_DATA_05

#define INV2REG_EXT_SLV_SENS_DATA_05   INV2REG(INV2_BANK0,0x40U)

Definition at line 95 of file invensense2_regs.h.

◆ INV2REG_EXT_SLV_SENS_DATA_06

#define INV2REG_EXT_SLV_SENS_DATA_06   INV2REG(INV2_BANK0,0x41U)

Definition at line 96 of file invensense2_regs.h.

◆ INV2REG_EXT_SLV_SENS_DATA_07

#define INV2REG_EXT_SLV_SENS_DATA_07   INV2REG(INV2_BANK0,0x42U)

Definition at line 97 of file invensense2_regs.h.

◆ INV2REG_EXT_SLV_SENS_DATA_08

#define INV2REG_EXT_SLV_SENS_DATA_08   INV2REG(INV2_BANK0,0x43U)

Definition at line 98 of file invensense2_regs.h.

◆ INV2REG_EXT_SLV_SENS_DATA_09

#define INV2REG_EXT_SLV_SENS_DATA_09   INV2REG(INV2_BANK0,0x44U)

Definition at line 99 of file invensense2_regs.h.

◆ INV2REG_EXT_SLV_SENS_DATA_10

#define INV2REG_EXT_SLV_SENS_DATA_10   INV2REG(INV2_BANK0,0x45U)

Definition at line 100 of file invensense2_regs.h.

◆ INV2REG_EXT_SLV_SENS_DATA_11

#define INV2REG_EXT_SLV_SENS_DATA_11   INV2REG(INV2_BANK0,0x46U)

Definition at line 101 of file invensense2_regs.h.

◆ INV2REG_EXT_SLV_SENS_DATA_12

#define INV2REG_EXT_SLV_SENS_DATA_12   INV2REG(INV2_BANK0,0x47U)

Definition at line 102 of file invensense2_regs.h.

◆ INV2REG_EXT_SLV_SENS_DATA_13

#define INV2REG_EXT_SLV_SENS_DATA_13   INV2REG(INV2_BANK0,0x48U)

Definition at line 103 of file invensense2_regs.h.

◆ INV2REG_EXT_SLV_SENS_DATA_14

#define INV2REG_EXT_SLV_SENS_DATA_14   INV2REG(INV2_BANK0,0x49U)

Definition at line 104 of file invensense2_regs.h.

◆ INV2REG_EXT_SLV_SENS_DATA_15

#define INV2REG_EXT_SLV_SENS_DATA_15   INV2REG(INV2_BANK0,0x4AU)

Definition at line 105 of file invensense2_regs.h.

◆ INV2REG_EXT_SLV_SENS_DATA_16

#define INV2REG_EXT_SLV_SENS_DATA_16   INV2REG(INV2_BANK0,0x4BU)

Definition at line 106 of file invensense2_regs.h.

◆ INV2REG_EXT_SLV_SENS_DATA_17

#define INV2REG_EXT_SLV_SENS_DATA_17   INV2REG(INV2_BANK0,0x4CU)

Definition at line 107 of file invensense2_regs.h.

◆ INV2REG_EXT_SLV_SENS_DATA_18

#define INV2REG_EXT_SLV_SENS_DATA_18   INV2REG(INV2_BANK0,0x4DU)

Definition at line 108 of file invensense2_regs.h.

◆ INV2REG_EXT_SLV_SENS_DATA_19

#define INV2REG_EXT_SLV_SENS_DATA_19   INV2REG(INV2_BANK0,0x4EU)

Definition at line 109 of file invensense2_regs.h.

◆ INV2REG_EXT_SLV_SENS_DATA_20

#define INV2REG_EXT_SLV_SENS_DATA_20   INV2REG(INV2_BANK0,0x4FU)

Definition at line 110 of file invensense2_regs.h.

◆ INV2REG_EXT_SLV_SENS_DATA_21

#define INV2REG_EXT_SLV_SENS_DATA_21   INV2REG(INV2_BANK0,0x50U)

Definition at line 111 of file invensense2_regs.h.

◆ INV2REG_EXT_SLV_SENS_DATA_22

#define INV2REG_EXT_SLV_SENS_DATA_22   INV2REG(INV2_BANK0,0x51U)

Definition at line 112 of file invensense2_regs.h.

◆ INV2REG_EXT_SLV_SENS_DATA_23

#define INV2REG_EXT_SLV_SENS_DATA_23   INV2REG(INV2_BANK0,0x52U)

Definition at line 113 of file invensense2_regs.h.

◆ INV2REG_FIFO_CFG

#define INV2REG_FIFO_CFG   INV2REG(INV2_BANK0,0x76U)

Definition at line 131 of file invensense2_regs.h.

◆ INV2REG_FIFO_COUNTH

#define INV2REG_FIFO_COUNTH   INV2REG(INV2_BANK0,0x70U)

Definition at line 127 of file invensense2_regs.h.

◆ INV2REG_FIFO_COUNTL

#define INV2REG_FIFO_COUNTL   INV2REG(INV2_BANK0,0x71U)

Definition at line 128 of file invensense2_regs.h.

◆ INV2REG_FIFO_EN_1

#define INV2REG_FIFO_EN_1   INV2REG(INV2_BANK0,0x66U)

Definition at line 114 of file invensense2_regs.h.

◆ INV2REG_FIFO_EN_2

#define INV2REG_FIFO_EN_2   INV2REG(INV2_BANK0,0x67U)

Definition at line 119 of file invensense2_regs.h.

◆ INV2REG_FIFO_MODE

#define INV2REG_FIFO_MODE   INV2REG(INV2_BANK0,0x69U)

Definition at line 126 of file invensense2_regs.h.

◆ INV2REG_FIFO_R_W

#define INV2REG_FIFO_R_W   INV2REG(INV2_BANK0,0x72U)

Definition at line 129 of file invensense2_regs.h.

◆ INV2REG_FIFO_RST

#define INV2REG_FIFO_RST   INV2REG(INV2_BANK0,0x68U)

Definition at line 125 of file invensense2_regs.h.

◆ INV2REG_FSYNC_CONFIG

#define INV2REG_FSYNC_CONFIG   INV2REG(INV2_BANK2,0x52U)

Definition at line 193 of file invensense2_regs.h.

◆ INV2REG_GYRO_CONFIG_1

#define INV2REG_GYRO_CONFIG_1   INV2REG(INV2_BANK2,0x01U)

Definition at line 148 of file invensense2_regs.h.

◆ INV2REG_GYRO_CONFIG_2

#define INV2REG_GYRO_CONFIG_2   INV2REG(INV2_BANK2,0x02U)

Definition at line 165 of file invensense2_regs.h.

◆ INV2REG_GYRO_SMPLRT_DIV

#define INV2REG_GYRO_SMPLRT_DIV   INV2REG(INV2_BANK2,0x00U)

Definition at line 147 of file invensense2_regs.h.

◆ INV2REG_GYRO_XOUT_H

#define INV2REG_GYRO_XOUT_H   INV2REG(INV2_BANK0,0x33U)

Definition at line 82 of file invensense2_regs.h.

◆ INV2REG_GYRO_XOUT_L

#define INV2REG_GYRO_XOUT_L   INV2REG(INV2_BANK0,0x34U)

Definition at line 83 of file invensense2_regs.h.

◆ INV2REG_GYRO_YOUT_H

#define INV2REG_GYRO_YOUT_H   INV2REG(INV2_BANK0,0x35U)

Definition at line 84 of file invensense2_regs.h.

◆ INV2REG_GYRO_YOUT_L

#define INV2REG_GYRO_YOUT_L   INV2REG(INV2_BANK0,0x36U)

Definition at line 85 of file invensense2_regs.h.

◆ INV2REG_GYRO_ZOUT_H

#define INV2REG_GYRO_ZOUT_H   INV2REG(INV2_BANK0,0x37U)

Definition at line 86 of file invensense2_regs.h.

◆ INV2REG_GYRO_ZOUT_L

#define INV2REG_GYRO_ZOUT_L   INV2REG(INV2_BANK0,0x38U)

Definition at line 87 of file invensense2_regs.h.

◆ INV2REG_I2C_MST_CTRL

#define INV2REG_I2C_MST_CTRL   INV2REG(INV2_BANK3,0x01U)

Definition at line 205 of file invensense2_regs.h.

◆ INV2REG_I2C_MST_DELAY_CTRL

#define INV2REG_I2C_MST_DELAY_CTRL   INV2REG(INV2_BANK3,0x02U)

Definition at line 208 of file invensense2_regs.h.

◆ INV2REG_I2C_MST_ODR_CONFIG

#define INV2REG_I2C_MST_ODR_CONFIG   INV2REG(INV2_BANK3,0x00U)

Definition at line 204 of file invensense2_regs.h.

◆ INV2REG_I2C_MST_STATUS

#define INV2REG_I2C_MST_STATUS   INV2REG(INV2_BANK0,0x17U)

Definition at line 68 of file invensense2_regs.h.

◆ INV2REG_I2C_SLV0_ADDR

#define INV2REG_I2C_SLV0_ADDR   INV2REG(INV2_BANK3,0x03U)

Definition at line 213 of file invensense2_regs.h.

◆ INV2REG_I2C_SLV0_CTRL

#define INV2REG_I2C_SLV0_CTRL   INV2REG(INV2_BANK3,0x05U)

Definition at line 215 of file invensense2_regs.h.

◆ INV2REG_I2C_SLV0_DO

#define INV2REG_I2C_SLV0_DO   INV2REG(INV2_BANK3,0x06U)

Definition at line 216 of file invensense2_regs.h.

◆ INV2REG_I2C_SLV0_REG

#define INV2REG_I2C_SLV0_REG   INV2REG(INV2_BANK3,0x04U)

Definition at line 214 of file invensense2_regs.h.

◆ INV2REG_I2C_SLV1_ADDR

#define INV2REG_I2C_SLV1_ADDR   INV2REG(INV2_BANK3,0x07U)

Definition at line 217 of file invensense2_regs.h.

◆ INV2REG_I2C_SLV1_CTRL

#define INV2REG_I2C_SLV1_CTRL   INV2REG(INV2_BANK3,0x09U)

Definition at line 219 of file invensense2_regs.h.

◆ INV2REG_I2C_SLV1_DO

#define INV2REG_I2C_SLV1_DO   INV2REG(INV2_BANK3,0x0AU)

Definition at line 220 of file invensense2_regs.h.

◆ INV2REG_I2C_SLV1_REG

#define INV2REG_I2C_SLV1_REG   INV2REG(INV2_BANK3,0x08U)

Definition at line 218 of file invensense2_regs.h.

◆ INV2REG_I2C_SLV2_ADDR

#define INV2REG_I2C_SLV2_ADDR   INV2REG(INV2_BANK3,0x0BU)

Definition at line 221 of file invensense2_regs.h.

◆ INV2REG_I2C_SLV2_CTRL

#define INV2REG_I2C_SLV2_CTRL   INV2REG(INV2_BANK3,0x0DU)

Definition at line 223 of file invensense2_regs.h.

◆ INV2REG_I2C_SLV2_DO

#define INV2REG_I2C_SLV2_DO   INV2REG(INV2_BANK3,0x0EU)

Definition at line 224 of file invensense2_regs.h.

◆ INV2REG_I2C_SLV2_REG

#define INV2REG_I2C_SLV2_REG   INV2REG(INV2_BANK3,0x0CU)

Definition at line 222 of file invensense2_regs.h.

◆ INV2REG_I2C_SLV3_ADDR

#define INV2REG_I2C_SLV3_ADDR   INV2REG(INV2_BANK3,0x0FU)

Definition at line 225 of file invensense2_regs.h.

◆ INV2REG_I2C_SLV3_CTRL

#define INV2REG_I2C_SLV3_CTRL   INV2REG(INV2_BANK3,0x11U)

Definition at line 227 of file invensense2_regs.h.

◆ INV2REG_I2C_SLV3_DO

#define INV2REG_I2C_SLV3_DO   INV2REG(INV2_BANK3,0x12U)

Definition at line 228 of file invensense2_regs.h.

◆ INV2REG_I2C_SLV3_REG

#define INV2REG_I2C_SLV3_REG   INV2REG(INV2_BANK3,0x10U)

Definition at line 226 of file invensense2_regs.h.

◆ INV2REG_I2C_SLV4_ADDR

#define INV2REG_I2C_SLV4_ADDR   INV2REG(INV2_BANK3,0x13U)

Definition at line 229 of file invensense2_regs.h.

◆ INV2REG_I2C_SLV4_CTRL

#define INV2REG_I2C_SLV4_CTRL   INV2REG(INV2_BANK3,0x15U)

Definition at line 231 of file invensense2_regs.h.

◆ INV2REG_I2C_SLV4_DI

#define INV2REG_I2C_SLV4_DI   INV2REG(INV2_BANK3,0x17U)

Definition at line 233 of file invensense2_regs.h.

◆ INV2REG_I2C_SLV4_DO

#define INV2REG_I2C_SLV4_DO   INV2REG(INV2_BANK3,0x16U)

Definition at line 232 of file invensense2_regs.h.

◆ INV2REG_I2C_SLV4_REG

#define INV2REG_I2C_SLV4_REG   INV2REG(INV2_BANK3,0x14U)

Definition at line 230 of file invensense2_regs.h.

◆ INV2REG_INT_ENABLE

#define INV2REG_INT_ENABLE   INV2REG(INV2_BANK0,0x10U)

Definition at line 63 of file invensense2_regs.h.

◆ INV2REG_INT_ENABLE_1

#define INV2REG_INT_ENABLE_1   INV2REG(INV2_BANK0,0x11U)

Definition at line 65 of file invensense2_regs.h.

◆ INV2REG_INT_ENABLE_2

#define INV2REG_INT_ENABLE_2   INV2REG(INV2_BANK0,0x12U)

Definition at line 66 of file invensense2_regs.h.

◆ INV2REG_INT_ENABLE_3

#define INV2REG_INT_ENABLE_3   INV2REG(INV2_BANK0,0x13U)

Definition at line 67 of file invensense2_regs.h.

◆ INV2REG_INT_PIN_CFG

#define INV2REG_INT_PIN_CFG   INV2REG(INV2_BANK0,0x0FU)

Definition at line 59 of file invensense2_regs.h.

◆ INV2REG_INT_STATUS

#define INV2REG_INT_STATUS   INV2REG(INV2_BANK0,0x19U)

Definition at line 69 of file invensense2_regs.h.

◆ INV2REG_INT_STATUS_1

#define INV2REG_INT_STATUS_1   INV2REG(INV2_BANK0,0x1AU)

Definition at line 71 of file invensense2_regs.h.

◆ INV2REG_INT_STATUS_2

#define INV2REG_INT_STATUS_2   INV2REG(INV2_BANK0,0x1BU)

Definition at line 72 of file invensense2_regs.h.

◆ INV2REG_INT_STATUS_3

#define INV2REG_INT_STATUS_3   INV2REG(INV2_BANK0,0x1CU)

Definition at line 73 of file invensense2_regs.h.

◆ INV2REG_LP_CONFIG

#define INV2REG_LP_CONFIG   INV2REG(INV2_BANK0,0x05U)

Definition at line 50 of file invensense2_regs.h.

◆ INV2REG_MOD_CTRL_USR

#define INV2REG_MOD_CTRL_USR   INV2REG(INV2_BANK2,0x54U)

Definition at line 202 of file invensense2_regs.h.

◆ INV2REG_ODR_ALIGN_EN

#define INV2REG_ODR_ALIGN_EN   INV2REG(INV2_BANK2,0x09U)

Definition at line 172 of file invensense2_regs.h.

◆ INV2REG_PWR_MGMT_1

#define INV2REG_PWR_MGMT_1   INV2REG(INV2_BANK0,0x06U)

Definition at line 51 of file invensense2_regs.h.

◆ INV2REG_PWR_MGMT_2

#define INV2REG_PWR_MGMT_2   INV2REG(INV2_BANK0,0x07U)

Definition at line 58 of file invensense2_regs.h.

◆ INV2REG_SELF_TEST_X_ACCEL

#define INV2REG_SELF_TEST_X_ACCEL   INV2REG(INV2_BANK1,0x0EU)

Definition at line 136 of file invensense2_regs.h.

◆ INV2REG_SELF_TEST_X_GYRO

#define INV2REG_SELF_TEST_X_GYRO   INV2REG(INV2_BANK1,0x02U)

Definition at line 133 of file invensense2_regs.h.

◆ INV2REG_SELF_TEST_Y_ACCEL

#define INV2REG_SELF_TEST_Y_ACCEL   INV2REG(INV2_BANK1,0x0FU)

Definition at line 137 of file invensense2_regs.h.

◆ INV2REG_SELF_TEST_Y_GYRO

#define INV2REG_SELF_TEST_Y_GYRO   INV2REG(INV2_BANK1,0x03U)

Definition at line 134 of file invensense2_regs.h.

◆ INV2REG_SELF_TEST_Z_ACCEL

#define INV2REG_SELF_TEST_Z_ACCEL   INV2REG(INV2_BANK1,0x10U)

Definition at line 138 of file invensense2_regs.h.

◆ INV2REG_SELF_TEST_Z_GYRO

#define INV2REG_SELF_TEST_Z_GYRO   INV2REG(INV2_BANK1,0x04U)

Definition at line 135 of file invensense2_regs.h.

◆ INV2REG_TEMP_CONFIG

#define INV2REG_TEMP_CONFIG   INV2REG(INV2_BANK2,0x53U)

Definition at line 201 of file invensense2_regs.h.

◆ INV2REG_TEMP_OUT_H

#define INV2REG_TEMP_OUT_H   INV2REG(INV2_BANK0,0x39U)

Definition at line 88 of file invensense2_regs.h.

◆ INV2REG_TEMP_OUT_L

#define INV2REG_TEMP_OUT_L   INV2REG(INV2_BANK0,0x3AU)

Definition at line 89 of file invensense2_regs.h.

◆ INV2REG_TIMEBASE_CORRECTIO

#define INV2REG_TIMEBASE_CORRECTIO   INV2REG(INV2_BANK1,0x28U)

Definition at line 145 of file invensense2_regs.h.

◆ INV2REG_USER_CTRL

#define INV2REG_USER_CTRL   INV2REG(INV2_BANK0,0x03U)

Definition at line 42 of file invensense2_regs.h.

◆ INV2REG_WHO_AM_I

#define INV2REG_WHO_AM_I   INV2REG(INV2_BANK0,0x00U)

Definition at line 41 of file invensense2_regs.h.

◆ INV2REG_XA_OFFS_H

#define INV2REG_XA_OFFS_H   INV2REG(INV2_BANK1,0x14U)

Definition at line 139 of file invensense2_regs.h.

◆ INV2REG_XA_OFFS_L

#define INV2REG_XA_OFFS_L   INV2REG(INV2_BANK1,0x15U)

Definition at line 140 of file invensense2_regs.h.

◆ INV2REG_XG_OFFS_USRH

#define INV2REG_XG_OFFS_USRH   INV2REG(INV2_BANK2,0x03U)

Definition at line 166 of file invensense2_regs.h.

◆ INV2REG_XG_OFFS_USRL

#define INV2REG_XG_OFFS_USRL   INV2REG(INV2_BANK2,0x04U)

Definition at line 167 of file invensense2_regs.h.

◆ INV2REG_YA_OFFS_H

#define INV2REG_YA_OFFS_H   INV2REG(INV2_BANK1,0x17U)

Definition at line 141 of file invensense2_regs.h.

◆ INV2REG_YA_OFFS_L

#define INV2REG_YA_OFFS_L   INV2REG(INV2_BANK1,0x18U)

Definition at line 142 of file invensense2_regs.h.

◆ INV2REG_YG_OFFS_USRH

#define INV2REG_YG_OFFS_USRH   INV2REG(INV2_BANK2,0x05U)

Definition at line 168 of file invensense2_regs.h.

◆ INV2REG_YG_OFFS_USRL

#define INV2REG_YG_OFFS_USRL   INV2REG(INV2_BANK2,0x06U)

Definition at line 169 of file invensense2_regs.h.

◆ INV2REG_ZA_OFFS_H

#define INV2REG_ZA_OFFS_H   INV2REG(INV2_BANK1,0x1AU)

Definition at line 143 of file invensense2_regs.h.

◆ INV2REG_ZA_OFFS_L

#define INV2REG_ZA_OFFS_L   INV2REG(INV2_BANK1,0x1BU)

Definition at line 144 of file invensense2_regs.h.

◆ INV2REG_ZG_OFFS_USRH

#define INV2REG_ZG_OFFS_USRH   INV2REG(INV2_BANK2,0x07U)

Definition at line 170 of file invensense2_regs.h.

◆ INV2REG_ZG_OFFS_USRL

#define INV2REG_ZG_OFFS_USRL   INV2REG(INV2_BANK2,0x08U)

Definition at line 171 of file invensense2_regs.h.