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w5100.c
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1 /*
2  * Copyright (C) 2012 Gerard Toonstra
3  *
4  * This file is part of paparazzi.
5  *
6  * paparazzi is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2, or (at your option)
9  * any later version.
10  *
11  * paparazzi is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with paparazzi; see the file COPYING. If not, write to
18  * the Free Software Foundation, 59 Temple Place - Suite 330,
19  * Boston, MA 02111-1307, USA.
20  *
21  */
22 
28 #include "mcu_periph/sys_time.h"
30 #include "mcu_periph/spi.h"
31 #include "mcu_periph/gpio.h"
32 
33 #define TXBUF_BASE 0x4000
34 #define RXBUF_BASE 0x6000
35 #define SOCKETS 4
36 
37 #define CMD_SOCKET 1
38 #define TELEM_SOCKET 0
39 
40 #define SOCK_OPEN 0x01
41 #define SOCK_CLOSE 0x10
42 #define SOCK_SEND 0x20
43 #define SOCK_RECV 0x40
44 #define SNMR_UDP 0x02
45 #define SNMR_MULTI 0x80
46 #define SNIR_SEND_OK 0x10
47 #define SNIR_TIMEOUT 0x08
48 #define CH_BASE 0x0400
49 #define CH_SIZE 0x0100
50 #define SMASK 0x07FF // Tx buffer MASK
51 #define RMASK 0x07FF // Tx buffer MASK
52 
53 #define REG_MR 0x0000
54 #define REG_RX_MEM 0x001A
55 #define REG_TX_MEM 0x001B
56 
57 #define REG_GAR 0x0001
58 #define REG_SUBR 0x0005
59 #define REG_SHAR 0x0009
60 #define REG_SIPR 0x000F
61 
62 #define SOCK_MR 0x0000
63 #define SOCK_CR 0x0001
64 #define SOCK_IR 0x0002
65 #define SOCK_PORT 0x0004
66 #define SOCK_DHAR 0x0006
67 #define SOCK_DIPR 0x000C
68 #define SOCK_DPORT 0x0010
69 #define SOCK_TX_WR 0x0024
70 #define SOCK_RSR 0x0026
71 #define SOCK_RXRD 0x0028
72 
73 #ifndef W5100_SPI_DEV
74 #define W5100_SPI_DEV spi1
75 #endif
76 
77 #ifndef W5100_SLAVE_IDX
78 #define W5100_SLAVE_IDX SPI_SLAVE1
79 #endif
80 
81 #ifndef W5100_DRDY_GPIO
82 #define W5100_DRDY_GPIO GPIOB
83 #endif
84 
85 #ifndef W5100_DRDY_GPIO_PIN
86 #define W5100_DRDY_GPIO_PIN GPIO1
87 #endif
88 
92 
93 // the media access control (ethernet hardware) address for the shield.
94 static uint8_t mac[] = { 0xDE, 0xAD, 0xBE, 0xEF, 0xFE, 0xED };
95 
96 //the IP address for the shield:
97 static uint8_t ip[] = { W5100_IP };
98 static uint8_t dest[] = { W5100_MULTICAST_IP };
99 static uint8_t subnet[] = { W5100_SUBNET };
100 static uint16_t dport = W5100_MULTICAST_PORT;
101 
102 static const uint8_t RST = 7; // Reset BIT
103 
104 uint16_t SBASE[SOCKETS]; // Tx buffer base address
105 uint16_t RBASE[SOCKETS]; // Rx buffer base address
106 static const uint16_t SSIZE = 2048; // Max Tx buffer size
107 static const uint16_t RSIZE = 2048; // Max Rx buffer size
108 
110 
111 static void w5100_close_socket(uint8_t _s);
112 static void configure_socket(uint8_t _s, uint8_t _flag, uint16_t _lport, uint16_t _dport, uint8_t *_dest);
113 static void w5100_read_data(uint8_t s, volatile uint8_t *src, volatile uint8_t *dst, uint16_t len);
114 static uint16_t w5100_read(uint16_t _addr, uint8_t *_buf, uint16_t _len);
115 
116 static inline void w5100_set(uint16_t _reg, uint8_t _val)
117 {
118  w5100_spi.output_buf[0] = 0xF0;
119  w5100_spi.output_buf[1] = _reg >> 8;
120  w5100_spi.output_buf[2] = _reg & 0xFF;
121  w5100_spi.output_buf[3] = _val;
122 
124 
125  // FIXME: no busy waiting! if really needed add a timeout!!!!
126  while (w5100_spi.status != SPITransSuccess);
127 }
128 
129 static inline uint8_t w5100_get(uint16_t _reg)
130 {
131  w5100_spi.output_buf[0] = 0x0F;
132  w5100_spi.output_buf[1] = _reg >> 8;
133  w5100_spi.output_buf[2] = _reg & 0xFF;
134 
136 
137  // FIXME: no busy waiting! if really needed add a timeout!!!!
138  while (w5100_spi.status != SPITransSuccess);
139 
140  return w5100_spi.input_buf[3];
141 }
142 
143 static inline void w5100_set_buffer(uint16_t _reg, volatile uint8_t *_buf, uint16_t _len)
144 {
145  for (int i = 0; i < _len; i++) {
146  w5100_set(_reg, _buf[ i ]);
147  _reg++;
148  }
149 }
150 
151 static inline void w5100_sock_set(uint8_t _sock, uint16_t _reg, uint8_t _val)
152 {
153  w5100_set(CH_BASE + _sock * CH_SIZE + _reg, _val);
154 }
155 
156 static inline uint8_t w5100_sock_get(uint8_t _sock, uint16_t _reg)
157 {
158  return w5100_get(CH_BASE + _sock * CH_SIZE + _reg);
159 }
160 
161 static inline uint16_t w5100_sock_get16(uint8_t _sock, uint16_t _reg)
162 {
163  uint16_t res = w5100_sock_get(_sock, _reg);
164  uint16_t res2 = w5100_sock_get(_sock, _reg + 1);
165  res = res << 8;
166  res2 = res2 & 0xFF;
167  res = res | res2;
168  return res;
169 }
170 
171 // Functions for the generic device API
172 static int true_function(struct w5100_periph *p __attribute__((unused)), uint8_t len __attribute__((unused))) { return TRUE; }
173 static void dev_transmit(struct w5100_periph *p __attribute__((unused)), uint8_t byte) { w5100_transmit(byte); }
174 static void dev_send(struct w5100_periph *p __attribute__((unused))) { w5100_send(); }
175 static int dev_char_available(struct w5100_periph *p __attribute__((unused))) { return w5100_ch_available; }
176 static uint8_t dev_getch(struct w5100_periph *p __attribute__((unused)))
177 {
178  uint8_t c = 0;
179  w5100_receive(&c, 1);
180  return c;
181 }
182 
183 void w5100_init(void)
184 {
185 
186  // configure the SPI bus.
196 
198  chip0.curbuf = 0;
201 
202  // wait one second for proper initialization (chip getting powered up).
203  sys_time_usleep(1000000);
204 
205  // set DRDY pin
208  sys_time_usleep(200);
210 
211  // allow some time for the chip to wake up.
212  sys_time_usleep(20000);
213 
214  // write reset bit into mode register
215  w5100_set(REG_MR, 1 << RST);
216 
217  // allow some time to wake up...
218  sys_time_usleep(20000);
219 
220  // receive memory size
221  w5100_set(REG_RX_MEM, 0x55);
222 
223  // transmit memory size
224  w5100_set(REG_TX_MEM, 0x55);
225 
226  // Setting the required socket base addresses for reads and writes to/from sockets
227  for (int i = 0; i < SOCKETS; i++) {
228  SBASE[i] = TXBUF_BASE + SSIZE * i;
229  RBASE[i] = RXBUF_BASE + RSIZE * i;
230  }
231 
232  uint8_t gateway[4];
233  gateway[0] = ip[0];
234  gateway[1] = ip[1];
235  gateway[2] = ip[2];
236  gateway[3] = 1;
237 
238  // configure gateway, subnet, mac and ip on "NIC".
239  w5100_set_buffer(REG_GAR, gateway, 4);
243 
244  // create a socket to send telemetry through.
246 
247  // make dest zero and configure socket to receive data
248  dest[ 0 ] = 0x00;
250 
251  // Configure generic device
252  chip0.device.periph = (void *)(&chip0);
258 }
259 
261 {
262 
264 
265  if (temp == chip0.tx_extract_idx[ chip0.curbuf ]) {
266  // no more room in this transaction.
267  return;
268  }
269 
270  // check if in process of sending data
272  chip0.tx_insert_idx[ chip0.curbuf ] = temp;
273 }
274 
276 {
277  // Now send off spi transaction.
279  uint8_t curbuf = chip0.curbuf;
280 
281  // switch to other buffer to accept more chars.
282  chip0.curbuf++;
283  if (chip0.curbuf >= W5100_BUFFER_NUM) {
284  chip0.curbuf = 0;
285  }
286 
288  uint16_t offset = ptr & SMASK;
289  uint16_t dstAddr = offset + SBASE[ TELEM_SOCKET ];
290 
293 
294  if (offset + len > SSIZE) {
295  // Wrap around circular buffer
296  uint16_t size = SSIZE - offset;
297  w5100_set_buffer(dstAddr, &chip0.tx_buf[curbuf][0], size);
298  w5100_set_buffer(SBASE[ TELEM_SOCKET ], &chip0.tx_buf[curbuf][0] + size, len - size);
299  } else {
300  w5100_set_buffer(dstAddr, &chip0.tx_buf[curbuf][0], len);
301  }
302 
303  // Reset write pointer
304  ptr += len;
306  w5100_sock_set(TELEM_SOCKET, SOCK_TX_WR + 1, ptr & 0xFF);
307 
308  // send
310 
312  while (complete != 0x00) {
313  complete = w5100_sock_get(TELEM_SOCKET, SOCK_CR);
314  }
315 }
316 
318 {
319  uint16_t val = 0, val1 = 0;
320 
321  do {
322  val1 = w5100_sock_get16(_s, SOCK_RSR);
323  if (val1 != 0) {
324  val = w5100_sock_get16(_s, SOCK_RSR);
325  }
326  } while (val != val1);
327  return val;
328 }
329 
331 {
332  // send command to close socket
334  // clear interrupt registers
335  w5100_sock_set(_s, SOCK_IR, 0xFF);
336 }
337 
338 static void configure_socket(uint8_t _s, uint8_t _flag, uint16_t _lport, uint16_t _dport, uint8_t *_dest)
339 {
340  // Configure socket that receives data on 1234
341  w5100_close_socket(_s);
342  // configure type of socket
343  w5100_sock_set(_s, SOCK_MR, SNMR_UDP | _flag);
344  // configure MSB+LSB of local port number
345  w5100_sock_set(_s, SOCK_PORT, _lport >> 8);
346  w5100_sock_set(_s, SOCK_PORT + 1, _lport & 0xFF);
347  if (_dest[0] != 0x00) {
348  // configure destination to send stuff to.
349  w5100_set_buffer(CH_BASE + _s * CH_SIZE + SOCK_DIPR, _dest, 4);
350  }
351 
352  // this mac corresponds to a mac for multicasting....
353  uint8_t mac_multi[] = { 0x01, 0x00, 0x5E, 0x01, 0x01, 0x0B };
354  w5100_set_buffer(CH_BASE + _s * CH_SIZE + SOCK_DHAR, mac_multi, 6);
355 
356  // configure destination port
357  w5100_sock_set(_s, SOCK_DPORT, _dport >> 8);
358  w5100_sock_set(_s, SOCK_DPORT + 1, _dport & 0xFF);
359 
360  // send command to open the socket
362 }
363 
365 {
366  if (w5100_rx_size(CMD_SOCKET) > 0) {
367  return TRUE;
368  }
369  return FALSE;
370 }
371 
372 uint16_t w5100_receive(uint8_t *buf, uint16_t len __attribute__((unused)))
373 {
374  uint8_t head[8];
375  uint16_t data_len = 0;
376  uint16_t ptr = 0;
377 
378  // Get socket read pointer
380  w5100_read_data(CMD_SOCKET, (uint8_t *)ptr, head, 0x08);
381  ptr += 8;
382  data_len = head[6];
383  data_len = (data_len << 8) + head[7];
384 
385  // read data from buffer.
386  w5100_read_data(CMD_SOCKET, (uint8_t *)ptr, buf, data_len); // data copy.
387  ptr += data_len;
388 
389  // update read pointer
390  w5100_sock_set(CMD_SOCKET, SOCK_RXRD, ptr >> 8);
391  w5100_sock_set(CMD_SOCKET, SOCK_RXRD + 1, ptr & 0xFF);
392 
393  // finalize read.
395  return data_len;
396 }
397 
398 static void w5100_read_data(uint8_t s __attribute__((unused)), volatile uint8_t *src, volatile uint8_t *dst,
399  uint16_t len)
400 {
401  uint16_t size;
402  uint16_t src_mask;
403  uint16_t src_ptr;
404 
405  src_mask = (uint16_t)src & RMASK;
406  src_ptr = RBASE[CMD_SOCKET] + src_mask;
407 
408  if ((src_mask + len) > RSIZE) {
409  size = RSIZE - src_mask;
410  w5100_read(src_ptr, (uint8_t *)dst, size);
411  dst += size;
412  w5100_read(RBASE[CMD_SOCKET], (uint8_t *) dst, len - size);
413  } else {
414  w5100_read(src_ptr, (uint8_t *) dst, len);
415  }
416 }
417 
418 static uint16_t w5100_read(uint16_t _addr, uint8_t *_buf, uint16_t _len)
419 {
420  for (int i = 0; i < _len; i++) {
421  _buf[i] = w5100_get(_addr);
422  _addr++;
423  }
424  return _len;
425 }
426 
unsigned short uint16_t
Definition: types.h:16
enum SPIClockPolarity cpol
clock polarity control
Definition: spi.h:149
uint16_t RBASE[SOCKETS]
Definition: w5100.c:105
static void w5100_set(uint16_t _reg, uint8_t _val)
Definition: w5100.c:116
volatile uint8_t work_tx[4]
Definition: w5100.h:55
#define W5100_TX_BUFFER_SIZE
Definition: w5100.h:35
static uint8_t dest[]
Definition: w5100.c:98
static void w5100_sock_set(uint8_t _sock, uint16_t _reg, uint8_t _val)
Definition: w5100.c:151
enum SPIClockDiv cdiv
prescaler of main clock to use as SPI clock
Definition: spi.h:153
#define W5100_SLAVE_IDX
Definition: w5100.c:78
uint16_t output_length
number of data words to write
Definition: spi.h:146
static void dev_transmit(struct w5100_periph *p, uint8_t byte)
Definition: w5100.c:173
static const uint16_t SSIZE
Definition: w5100.c:106
#define RXBUF_BASE
Definition: w5100.c:34
#define SNMR_MULTI
Definition: w5100.c:45
#define SOCK_MR
Definition: w5100.c:62
static int true_function(struct w5100_periph *p, uint8_t len)
Definition: w5100.c:172
uint16_t w5100_rx_size(uint8_t _s)
Definition: w5100.c:317
Some architecture independent helper functions for GPIOs.
void w5100_init(void)
Definition: w5100.c:183
#define SOCK_CLOSE
Definition: w5100.c:41
#define SMASK
Definition: w5100.c:50
#define W5100_DRDY_GPIO
Definition: w5100.c:82
#define REG_MR
Definition: w5100.c:53
#define W5100_SPI_DEV
Definition: w5100.c:74
#define CH_BASE
Definition: w5100.c:48
#define W5100_RX_BUFFER_SIZE
Definition: w5100.h:34
#define CH_SIZE
Definition: w5100.c:49
static uint8_t dev_getch(struct w5100_periph *p)
Definition: w5100.c:176
SPI transaction structure.
Definition: spi.h:142
uint8_t ck_a
Definition: w5100.c:90
#define SOCK_RECV
Definition: w5100.c:43
enum SPIBitOrder bitorder
MSB/LSB order.
Definition: spi.h:152
#define SOCK_RSR
Definition: w5100.c:70
#define W5100_BUFFER_NUM
Definition: w5100.h:36
volatile uint8_t * output_buf
pointer to transmit buffer for DMA
Definition: spi.h:144
enum SPISlaveSelect select
slave selection behavior
Definition: spi.h:148
volatile uint8_t tx_buf[W5100_BUFFER_NUM][W5100_TX_BUFFER_SIZE]
Definition: w5100.h:52
#define SOCK_CR
Definition: w5100.c:63
#define REG_SIPR
Definition: w5100.c:60
#define SOCK_PORT
Definition: w5100.c:65
#define FALSE
Definition: std.h:5
uint16_t w5100_receive(uint8_t *buf, uint16_t len)
Definition: w5100.c:372
static uint8_t w5100_sock_get(uint8_t _sock, uint16_t _reg)
Definition: w5100.c:156
Architecture independent SPI (Serial Peripheral Interface) API.
enum SPIClockPhase cpha
clock phase control
Definition: spi.h:150
static uint8_t ip[]
Definition: w5100.c:97
#define SOCK_RXRD
Definition: w5100.c:71
#define CMD_SOCKET
Definition: w5100.c:37
#define TRUE
Definition: std.h:4
#define SOCK_TX_WR
Definition: w5100.c:69
#define SOCK_OPEN
Definition: w5100.c:40
Definition: spi.h:84
#define TXBUF_BASE
Definition: w5100.c:33
#define SNMR_UDP
Definition: w5100.c:44
void gpio_set(uint32_t port, uint16_t pin)
Set a gpio output to high level.
Definition: gpio_ardrone.c:54
#define REG_RX_MEM
Definition: w5100.c:54
uint8_t ck_b
Definition: w5100.c:90
bool_t spi_submit(struct spi_periph *p, struct spi_transaction *t)
Submit a spi transaction.
Definition: spi_arch.c:48
Architecture independent timing functions.
static int dev_char_available(struct w5100_periph *p)
Definition: w5100.c:175
volatile uint16_t tx_insert_idx[W5100_BUFFER_NUM]
Definition: w5100.h:53
#define RMASK
Definition: w5100.c:51
#define SOCK_IR
Definition: w5100.c:64
static const uint16_t RSIZE
Definition: w5100.c:107
volatile uint16_t tx_extract_idx[W5100_BUFFER_NUM]
Definition: w5100.h:54
uint16_t val[TCOUPLE_NB]
#define REG_SUBR
Definition: w5100.c:58
void gpio_clear(uint32_t port, uint16_t pin)
Clear a gpio output to low level.
Definition: gpio_ardrone.c:70
volatile uint8_t work_rx[4]
Definition: w5100.h:56
static uint16_t w5100_sock_get16(uint8_t _sock, uint16_t _reg)
Definition: w5100.c:161
enum W5100Status status
Definition: w5100.h:45
#define TELEM_SOCKET
Definition: w5100.c:38
static uint16_t w5100_read(uint16_t _addr, uint8_t *_buf, uint16_t _len)
Definition: w5100.c:418
static void w5100_read_data(uint8_t s, volatile uint8_t *src, volatile uint8_t *dst, uint16_t len)
Definition: w5100.c:398
#define SOCK_DPORT
Definition: w5100.c:68
static void w5100_close_socket(uint8_t _s)
Definition: w5100.c:330
struct w5100_periph chip0
Definition: w5100.c:89
CPOL = 0.
Definition: spi.h:77
uint16_t input_length
number of data words to read
Definition: spi.h:145
static uint8_t subnet[]
Definition: w5100.c:99
uint16_t SBASE[SOCKETS]
Definition: w5100.c:104
static void w5100_set_buffer(uint16_t _reg, volatile uint8_t *_buf, uint16_t _len)
Definition: w5100.c:143
struct adc_buf * buf
Definition: adc_arch.c:587
static void sys_time_usleep(uint32_t us)
Definition: sys_time_arch.h:55
#define SOCKETS
Definition: w5100.c:35
#define W5100_DRDY_GPIO_PIN
Definition: w5100.c:86
W5100 ethernet chip I/O.
unsigned char uint8_t
Definition: types.h:14
#define SOCK_SEND
Definition: w5100.c:42
#define SOCK_DIPR
Definition: w5100.c:67
CPHA = 0.
Definition: spi.h:68
slave is selected before transaction and unselected after
Definition: spi.h:57
#define REG_SHAR
Definition: w5100.c:59
struct spi_transaction w5100_spi
Definition: w5100.c:109
void w5100_send()
Definition: w5100.c:275
enum SPIDataSizeSelect dss
data transfer word size
Definition: spi.h:151
uint8_t w5100_rx_buf[W5100_RX_BUFFER_SIZE]
Definition: w5100.c:91
static void dev_send(struct w5100_periph *p)
Definition: w5100.c:174
uint8_t slave_idx
slave id: SPI_SLAVE0 to SPI_SLAVE4
Definition: spi.h:147
Definition: spi.h:119
volatile uint8_t * input_buf
pointer to receive buffer for DMA
Definition: spi.h:143
static float p[2][2]
static uint8_t w5100_get(uint16_t _reg)
Definition: w5100.c:129
static uint16_t dport
Definition: w5100.c:100
void w5100_transmit(uint8_t data)
Definition: w5100.c:260
int curbuf
Definition: w5100.h:46
static uint8_t mac[]
Definition: w5100.c:94
#define REG_TX_MEM
Definition: w5100.c:55
struct link_device device
Generic device interface.
Definition: w5100.h:59
#define SOCK_DHAR
Definition: w5100.c:66
#define REG_GAR
Definition: w5100.c:57
bool_t w5100_ch_available()
Definition: w5100.c:364
static const uint8_t RST
Definition: w5100.c:102
static void configure_socket(uint8_t _s, uint8_t _flag, uint16_t _lport, uint16_t _dport, uint8_t *_dest)
Definition: w5100.c:338
void gpio_setup_output(uint32_t port, uint16_t gpios)
Setup one or more pins of the given GPIO port as outputs.
Definition: gpio_ardrone.c:102
enum SPITransactionStatus status
Definition: spi.h:156