Paparazzi UAS  v6.2_unstable
Paparazzi is a free software Unmanned Aircraft System.
spi_arch.c
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1 /*
2  * Copyright (C) 2013 AggieAir, A Remote Sensing Unmanned Aerial System for Scientific Applications
3  * Utah State University, http://aggieair.usu.edu/
4  *
5  * Michal Podhradsky (michal.podhradsky@aggiemail.usu.edu)
6  * Calvin Coopmans (c.r.coopmans@ieee.org)
7  *
8  * This file is part of paparazzi.
9  *
10  * paparazzi is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2, or (at your option)
13  * any later version.
14  *
15  * paparazzi is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with paparazzi; see the file COPYING. If not, write to
22  * the Free Software Foundation, 59 Temple Place - Suite 330,
23  * Boston, MA 02111-1307, USA.
24  */
31 #include "mcu_periph/spi.h"
32 #include "mcu_periph/gpio.h"
33 #include BOARD_CONFIG
34 
35 #include <string.h>
36 #include "mcu_periph/ram_arch.h"
37 
38 
39 #if SPI_SLAVE
40 #error "ChibiOS operates only in SPI_MASTER mode (Slave is TODO)"
41 #endif
42 
43 #if USE_SPI0
44 #error "ChibiOS architectures don't have SPI0"
45 #endif
46 
47 // Default stack size
48 #ifndef SPI_THREAD_STACK_SIZE
49 #define SPI_THREAD_STACK_SIZE 512
50 #endif
51 
52 // Default spi DMA buffer length for F7/H7
53 #ifndef SPI_DMA_BUF_LEN
54 #define SPI_DMA_BUF_LEN 512 // it has to be big enough
55 #endif
56 
57 // private SPI init structure
58 struct spi_init {
59 #if defined(STM32F7XX) || defined(STM32H7XX)
60  uint8_t dma_buf_out[SPI_DMA_BUF_LEN];
61  uint8_t dma_buf_in[SPI_DMA_BUF_LEN];
62 #endif
63  char *name;
64  semaphore_t sem;
65 };
66 
75 static inline ioportid_t spi_resolve_slave_port(uint8_t slave)
76 {
77  switch (slave) {
78 #if USE_SPI_SLAVE0
79  case 0:
81  break;
82 #endif // USE_SPI_SLAVE0
83 #if USE_SPI_SLAVE1
84  case 1:
86  break;
87 #endif //USE_SPI_SLAVE1
88 #if USE_SPI_SLAVE2
89  case 2:
91  break;
92 #endif //USE_SPI_SLAVE2
93 #if USE_SPI_SLAVE3
94  case 3:
96  break;
97 #endif //USE_SPI_SLAVE3
98 #if USE_SPI_SLAVE4
99  case 4:
100  return SPI_SELECT_SLAVE4_PORT;
101  break;
102 #endif //USE_SPI_SLAVE4
103 #if USE_SPI_SLAVE5
104  case 5:
105  return SPI_SELECT_SLAVE5_PORT;
106  break;
107 #endif //USE_SPI_SLAVE5
108 #if USE_SPI_SLAVE6
109  case 6:
110  return SPI_SELECT_SLAVE6_PORT;
111  break;
112 #endif //USE_SPI_SLAVE6
113 #if USE_SPI_SLAVE7
114  case 7:
115  return SPI_SELECT_SLAVE7_PORT;
116  break;
117 #endif //USE_SPI_SLAVE7
118 #if USE_SPI_SLAVE8
119  case 8:
120  return SPI_SELECT_SLAVE8_PORT;
121  break;
122 #endif //USE_SPI_SLAVE8
123  default:
124  return 0;
125  break;
126  }
127 }
128 
138 {
139  switch (slave) {
140 #if USE_SPI_SLAVE0
141  case 0:
142  return SPI_SELECT_SLAVE0_PIN;
143  break;
144 #endif // USE_SPI_SLAVE0
145 #if USE_SPI_SLAVE1
146  case 1:
147  return SPI_SELECT_SLAVE1_PIN;
148  break;
149 #endif //USE_SPI_SLAVE1
150 #if USE_SPI_SLAVE2
151  case 2:
152  return SPI_SELECT_SLAVE2_PIN;
153  break;
154 #endif //USE_SPI_SLAVE2
155 #if USE_SPI_SLAVE3
156  case 3:
157  return SPI_SELECT_SLAVE3_PIN;
158  break;
159 #endif //USE_SPI_SLAVE3
160 #if USE_SPI_SLAVE4
161  case 4:
162  return SPI_SELECT_SLAVE4_PIN;
163  break;
164 #endif //USE_SPI_SLAVE4
165 #if USE_SPI_SLAVE5
166  case 5:
167  return SPI_SELECT_SLAVE5_PIN;
168  break;
169 #endif //USE_SPI_SLAVE5
170 #if USE_SPI_SLAVE6
171  case 6:
172  return SPI_SELECT_SLAVE6_PIN;
173  break;
174 #endif //USE_SPI_SLAVE6
175 #if USE_SPI_SLAVE7
176  case 7:
177  return SPI_SELECT_SLAVE7_PIN;
178  break;
179 #endif //USE_SPI_SLAVE7
180 #if USE_SPI_SLAVE8
181  case 8:
182  return SPI_SELECT_SLAVE8_PIN;
183  break;
184 #endif //USE_SPI_SLAVE8
185  default:
186  return 0;
187  break;
188  }
189 }
190 
203 static inline uint32_t spi_resolve_CR1(struct spi_transaction *t __attribute__((unused)))
204 {
205  uint32_t CR1 = 0;
206 #if defined(STM32F1XX) || defined(STM32F4XX)
207  if (t->dss == SPIDss16bit) {
208  CR1 |= SPI_CR1_DFF;
209  }
210 #endif
211 #if defined(STM32F1XX) || defined(STM32F4XX) || defined(STM32F7XX)
212  if (t->bitorder == SPILSBFirst) {
213  CR1 |= SPI_CR1_LSBFIRST;
214  }
215  if (t->cpha == SPICphaEdge2) {
216  CR1 |= SPI_CR1_CPHA;
217  }
218  if (t->cpol == SPICpolIdleHigh) {
219  CR1 |= SPI_CR1_CPOL;
220  }
221 
222  switch (t->cdiv) {
223  case SPIDiv2://000
224  break;
225  case SPIDiv4://001
226  CR1 |= SPI_CR1_BR_0;
227  break;
228  case SPIDiv8://010
229  CR1 |= SPI_CR1_BR_1;
230  break;
231  case SPIDiv16://011
232  CR1 |= SPI_CR1_BR_1 | SPI_CR1_BR_0;
233  break;
234  case SPIDiv32://100
235  CR1 |= SPI_CR1_BR_2;
236  break;
237  case SPIDiv64://101
238  CR1 |= SPI_CR1_BR_2 | SPI_CR1_BR_0;
239  break;
240  case SPIDiv128://110
241  CR1 |= SPI_CR1_BR_2 | SPI_CR1_BR_1;
242  break;
243  case SPIDiv256://111
244  CR1 |= SPI_CR1_BR;
245  break;
246  default:
247  break;
248  }
249 #endif /* STM32F1XX || STM32F4XX || STM32F7XX */
250 #if defined(STM32H7XX)
251  if (t->dss == SPIDss16bit) {
252  CR1 |= SPI_CFG1_DSIZE_VALUE(15); // 16 bit transfer
253  } else {
254  CR1 |= SPI_CFG1_DSIZE_VALUE(7); // 8 bit transfer
255  }
256  CR1 |= SPI_CFG1_MBR_VALUE(t->cdiv);
257 #endif /* STM32H7XX */
258  return CR1;
259 }
260 
273 static inline uint32_t spi_resolve_CR2(struct spi_transaction *t __attribute__((unused)))
274 {
275  uint32_t CR2 = 0;
276 #if defined(STM32F7XX)
277  if (t->dss == SPIDss16bit) {
278  CR2 |= SPI_CR2_DS_0 | SPI_CR2_DS_1 | SPI_CR2_DS_2 | SPI_CR2_DS_3;
279  } else {
280  CR2 |= SPI_CR2_DS_0 | SPI_CR2_DS_1 | SPI_CR2_DS_2;
281  }
282 #endif /* STM32F7XX */
283 #if defined(STM32H7XX)
284  if (t->bitorder == SPILSBFirst) {
285  CR2 |= SPI_CFG2_LSBFRST;
286  }
287  if (t->cpha == SPICphaEdge2) {
288  CR2 |= SPI_CFG2_CPHA;
289  }
290  if (t->cpol == SPICpolIdleHigh) {
291  CR2 |= SPI_CFG2_CPOL;
292  }
293 #endif /* STM32H7XX */
294  return CR2;
295 }
296 
302 static void handle_spi_thd(struct spi_periph *p)
303 {
304  struct spi_init *i = (struct spi_init *) p->init_struct;
305 
306  // wait for a transaction to be pushed in the queue
307  chSemWait(&i->sem);
308 
309  if ((p->trans_insert_idx == p->trans_extract_idx) || p->suspend) {
310  p->status = SPIIdle;
311  // no transaction pending
312  return;
313  }
314 
315  // Get next transation in queue
316  struct spi_transaction *t = p->trans[p->trans_extract_idx];
317 
318  p->status = SPIRunning;
319 
320  SPIConfig spi_cfg = {
321  false, // no circular buffer
322 #if defined(HAL_LLD_SELECT_SPI_V2)
323  false, // no slave mode
324  NULL, // no callback
325 #endif
326  NULL, // no callback
329  spi_resolve_CR1(t),
330  spi_resolve_CR2(t),
331  };
332 
333  // find max transaction length
334  static size_t t_length;
335  if (t->input_length >= t->output_length) {
336  t_length = (size_t)t->input_length;
337  } else {
338  t_length = (size_t)t->output_length;
339  }
340 
341  // Configure SPI bus with the current slave select pin
342  spiStart((SPIDriver *)p->reg_addr, &spi_cfg);
343  // Select the slave after reconfiguration of the peripheral
344  if (t->select == SPISelectUnselect || t->select == SPISelect) {
345  spiSelect((SPIDriver *)p->reg_addr);
346  }
347 
348  // Run the callback after selecting the slave
349  // FIXME warning: done in spi thread
350  if (t->before_cb != 0) {
351  t->before_cb(t);
352  }
353 
354  // Start synchronous data transfer
355 #if defined(STM32F7XX) || defined(STM32H7XX)
356  // we do stupid mem copy because F7/H7 needs a special RAM for DMA operation
357  memcpy(i->dma_buf_out, (void *)t->output_buf, (size_t)t->output_length);
358  cacheBufferFlush(i->dma_buf_out, t->output_length);
359  spiExchange((SPIDriver *)p->reg_addr, t_length, i->dma_buf_out, i->dma_buf_in);
360  cacheBufferInvalidate(i->dma_buf_in, t->input_length);
361  memcpy((void *)t->input_buf, i->dma_buf_in, (size_t)t->input_length);
362 #else
363  spiExchange((SPIDriver *)p->reg_addr, t_length, (uint8_t *)t->output_buf, (uint8_t *)t->input_buf);
364 #endif
365 
366  // Unselect the slave
367  if (t->select == SPISelectUnselect || t->select == SPIUnselect) {
368  spiUnselect((SPIDriver *)p->reg_addr);
369  }
370 
371  chSysLock();
372  // end of transaction, handle fifo
373  p->trans_extract_idx++;
374  if (p->trans_extract_idx >= SPI_TRANSACTION_QUEUE_LEN) {
375  p->trans_extract_idx = 0;
376  }
377  p->status = SPIIdle;
378  chSysUnlock();
379 
380  // Report the transaction as success
381  t->status = SPITransSuccess;
382 
383  /*
384  * Run the callback after deselecting the slave
385  * to avoid recursion and/or concurency over the bus
386  */
387  // FIXME warning: done in spi thread
388  if (t->after_cb != 0) {
389  t->after_cb(t);
390  }
391 
392 }
393 
399 static __attribute__((noreturn)) void thd_spi(void *arg)
400 {
401  struct spi_periph *spip = (struct spi_periph *)arg;
402  struct spi_init *init_s = (struct spi_init *)spip->init_struct;
403  chRegSetThreadName(init_s->name);
404 
405  while (TRUE) {
406  handle_spi_thd(spip);
407  }
408 }
409 
414 #if USE_SPI1
415 // Local variables (in DMA safe memory)
416 static IN_DMA_SECTION(struct spi_init spi1_init_s) = {
417  .name = "spi1",
418  .sem = __SEMAPHORE_DATA(spi1_init_s.sem, 0),
419 };
420 static THD_WORKING_AREA(wa_thd_spi1, SPI_THREAD_STACK_SIZE);
421 
422 // Initialize the interface
423 void spi1_arch_init(void)
424 {
425  spi1.reg_addr = &SPID1;
426  spi1.init_struct = &spi1_init_s;
427  // Create thread
428  chThdCreateStatic(wa_thd_spi1, sizeof(wa_thd_spi1),
429  NORMALPRIO + 1, thd_spi, (void *)&spi1);
430 }
431 #endif
432 
433 #if USE_SPI2
434 // Local variables (in DMA safe memory)
435 static IN_DMA_SECTION(struct spi_init spi2_init_s) = {
436  .name = "spi2",
437  .sem = __SEMAPHORE_DATA(spi2_init_s.sem, 0),
438 };
439 static THD_WORKING_AREA(wa_thd_spi2, SPI_THREAD_STACK_SIZE);
440 
441 // Initialize the interface
442 void spi2_arch_init(void)
443 {
444  spi2.reg_addr = &SPID2;
445  spi2.init_struct = &spi2_init_s;
446  // Create thread
447  chThdCreateStatic(wa_thd_spi2, sizeof(wa_thd_spi2),
448  NORMALPRIO + 1, thd_spi, (void *)&spi2);
449 }
450 #endif
451 
452 #if USE_SPI3
453 // Local variables (in DMA safe memory)
454 static IN_DMA_SECTION(struct spi_init spi3_init_s) = {
455  .name = "spi3",
456  .sem = __SEMAPHORE_DATA(spi3_init_s.sem, 0),
457 };
458 static THD_WORKING_AREA(wa_thd_spi3, SPI_THREAD_STACK_SIZE);
459 
460 // Initialize the interface
461 void spi3_arch_init(void)
462 {
463  spi3.reg_addr = &SPID3;
464  spi3.init_struct = &spi3_init_s;
465  // Create thread
466  chThdCreateStatic(wa_thd_spi3, sizeof(wa_thd_spi3),
467  NORMALPRIO + 1, thd_spi, (void *)&spi3);
468 }
469 #endif
470 
471 #if USE_SPI4
472 // Local variables (in DMA safe memory)
473 static IN_DMA_SECTION(struct spi_init spi4_init_s) = {
474  .name = "spi4",
475  .sem = __SEMAPHORE_DATA(spi4_init_s.sem, 0),
476 };
477 static THD_WORKING_AREA(wa_thd_spi4, SPI_THREAD_STACK_SIZE);
478 
479 // Initialize the interface
480 void spi4_arch_init(void)
481 {
482  spi4.reg_addr = &SPID4;
483  spi4.init_struct = &spi4_init_s;
484  // Create thread
485  chThdCreateStatic(wa_thd_spi4, sizeof(wa_thd_spi4),
486  NORMALPRIO + 1, thd_spi, (void *)&spi4);
487 }
488 #endif
489 
490 
508 bool spi_submit(struct spi_periph *p, struct spi_transaction *t)
509 {
510  // system lock
511  chSysLock();
512 
513  uint8_t idx;
514  idx = p->trans_insert_idx + 1;
515  if (idx >= SPI_TRANSACTION_QUEUE_LEN) { idx = 0; }
516  if ((idx == p->trans_extract_idx) || ((t->input_length == 0) && (t->output_length == 0))) {
517  t->status = SPITransFailed;
518  chSysUnlock();
519  return FALSE; /* queue full or input_length and output_length both 0 */
520  // TODO can't tell why it failed here if it does
521  }
522 
523  t->status = SPITransPending;
524 
525  /* put transacation in queue */
526  p->trans[p->trans_insert_idx] = t;
527  p->trans_insert_idx = idx;
528 
529  chSysUnlock();
530  chSemSignal(&((struct spi_init *)p->init_struct)->sem);
531  // transaction submitted
532  return TRUE;
533 }
534 
535 
536 
542 {
543  switch (slave) {
544 #if USE_SPI_SLAVE0
545  case 0:
547  break;
548 #endif // USE_SPI_SLAVE0
549 #if USE_SPI_SLAVE1
550  case 1:
552  break;
553 #endif //USE_SPI_SLAVE1
554 #if USE_SPI_SLAVE2
555  case 2:
557  break;
558 #endif //USE_SPI_SLAVE2
559 #if USE_SPI_SLAVE3
560  case 3:
562  break;
563 #endif //USE_SPI_SLAVE3
564 #if USE_SPI_SLAVE4
565  case 4:
567  break;
568 #endif //USE_SPI_SLAVE4
569 #if USE_SPI_SLAVE5
570  case 5:
572  break;
573 #endif //USE_SPI_SLAVE5
574 #if USE_SPI_SLAVE6
575  case 6:
576  gpio_clear(SPI_SELECT_SLAVE6_PORT, SPI_SELECT_SLAVE6_PIN);
577  break;
578 #endif //USE_SPI_SLAVE6
579 #if USE_SPI_SLAVE7
580  case 7:
581  gpio_clear(SPI_SELECT_SLAVE7_PORT, SPI_SELECT_SLAVE7_PIN);
582  break;
583 #endif //USE_SPI_SLAVE7
584 #if USE_SPI_SLAVE8
585  case 8:
586  gpio_clear(SPI_SELECT_SLAVE8_PORT, SPI_SELECT_SLAVE8_PIN);
587  break;
588 #endif //USE_SPI_SLAVE8
589  default:
590  break;
591  }
592 }
593 
599 {
600  switch (slave) {
601 #if USE_SPI_SLAVE0
602  case 0:
604  break;
605 #endif // USE_SPI_SLAVE0
606 #if USE_SPI_SLAVE1
607  case 1:
609  break;
610 #endif //USE_SPI_SLAVE1
611 #if USE_SPI_SLAVE2
612  case 2:
614  break;
615 #endif //USE_SPI_SLAVE2
616 #if USE_SPI_SLAVE3
617  case 3:
619  break;
620 #endif //USE_SPI_SLAVE3
621 #if USE_SPI_SLAVE4
622  case 4:
624  break;
625 #endif //USE_SPI_SLAVE4
626 #if USE_SPI_SLAVE5
627  case 5:
629  break;
630 #endif //USE_SPI_SLAVE5
631 #if USE_SPI_SLAVE6
632  case 6:
633  gpio_set(SPI_SELECT_SLAVE6_PORT, SPI_SELECT_SLAVE6_PIN);
634  break;
635 #endif //USE_SPI_SLAVE6
636 #if USE_SPI_SLAVE7
637  case 7:
638  gpio_set(SPI_SELECT_SLAVE7_PORT, SPI_SELECT_SLAVE7_PIN);
639  break;
640 #endif //USE_SPI_SLAVE7
641 #if USE_SPI_SLAVE8
642  case 8:
643  gpio_set(SPI_SELECT_SLAVE8_PORT, SPI_SELECT_SLAVE8_PIN);
644  break;
645 #endif //USE_SPI_SLAVE8
646  default:
647  break;
648  }
649 }
650 
656 bool spi_lock(struct spi_periph *p, uint8_t slave)
657 {
658  if (slave < 254 && p->suspend == 0) {
659  p->suspend = slave + 1; // 0 is reserved for unlock state
660  return TRUE;
661  }
662  return FALSE;
663 }
664 
670 bool spi_resume(struct spi_periph *p, uint8_t slave)
671 {
672  if (p->suspend == slave + 1) {
673  // restart fifo
674  p->suspend = 0;
675  return TRUE;
676  }
677  return FALSE;
678 }
679 
684 void spi_init_slaves(void)
685 {
686 #if USE_SPI_SLAVE0
689 #endif
690 
691 #if USE_SPI_SLAVE1
694 #endif
695 
696 #if USE_SPI_SLAVE2
699 #endif
700 
701 #if USE_SPI_SLAVE3
704 #endif
705 
706 #if USE_SPI_SLAVE4
709 #endif
710 
711 #if USE_SPI_SLAVE5
714 #endif
715 
716 #if USE_SPI_SLAVE6
717  gpio_setup_output(SPI_SELECT_SLAVE6_PORT, SPI_SELECT_SLAVE6_PIN);
719 #endif
720 
721 #if USE_SPI_SLAVE7
722  gpio_setup_output(SPI_SELECT_SLAVE7_PORT, SPI_SELECT_SLAVE7_PIN);
724 #endif
725 
726 #if USE_SPI_SLAVE8
727  gpio_setup_output(SPI_SELECT_SLAVE8_PORT, SPI_SELECT_SLAVE8_PIN);
729 #endif
730 }
SPI_SELECT_SLAVE3_PIN
#define SPI_SELECT_SLAVE3_PIN
Definition: board.h:479
SPIRunning
@ SPIRunning
Definition: spi.h:108
uint32_t
unsigned int uint32_t
Typedef defining 32 bit unsigned int type.
Definition: vl53l1_types.h:78
uint8_t
unsigned char uint8_t
Typedef defining 8 bit unsigned char type.
Definition: vl53l1_types.h:98
SPITransPending
@ SPITransPending
Definition: spi.h:97
handle_spi_thd
static void handle_spi_thd(struct spi_periph *p)
main thread function
Definition: spi_arch.c:302
spi_transaction::output_length
uint16_t output_length
number of data words to write
Definition: spi.h:152
spi.h
spi_transaction
SPI transaction structure.
Definition: spi.h:148
SPI_THREAD_STACK_SIZE
#define SPI_THREAD_STACK_SIZE
Definition: spi_arch.c:49
spi_resolve_slave_pin
static uint16_t spi_resolve_slave_pin(uint8_t slave)
Resolve slave pin.
Definition: spi_arch.c:137
IN_DMA_SECTION
static IN_DMA_SECTION(struct spi_init spi1_init_s)
Configure SPI peripherals.
SPI_SELECT_SLAVE4_PORT
#define SPI_SELECT_SLAVE4_PORT
Definition: board.h:481
gpio_setup_output
void gpio_setup_output(ioportid_t port, uint16_t gpios)
Setup one or more pins of the given GPIO port as outputs.
Definition: gpio_arch.c:33
spi_periph::init_struct
void * init_struct
Definition: spi.h:184
SPI_SELECT_SLAVE3_PORT
#define SPI_SELECT_SLAVE3_PORT
Definition: board.h:478
spi_resolve_CR2
static uint32_t spi_resolve_CR2(struct spi_transaction *t)
Resolve CR2 (or CFG2)
Definition: spi_arch.c:273
SPISelectUnselect
@ SPISelectUnselect
slave is selected before transaction and unselected after
Definition: spi.h:63
SPITransSuccess
@ SPITransSuccess
Definition: spi.h:99
spi2
process_rx_dma_interrupt & spi2
receive transferred over DMA
Definition: spi_arch.c:1004
SPI_SELECT_SLAVE0_PIN
#define SPI_SELECT_SLAVE0_PIN
Definition: board.h:470
idx
static uint32_t idx
Definition: nps_radio_control_spektrum.c:105
spi_init::sem
semaphore_t sem
Definition: spi_arch.c:64
spi_resolve_CR1
static uint32_t spi_resolve_CR1(struct spi_transaction *t)
Resolve CR1 (or CFG1)
Definition: spi_arch.c:203
spi_transaction::output_buf
volatile uint8_t * output_buf
pointer to transmit buffer for DMA
Definition: spi.h:150
spi_periph
SPI peripheral structure.
Definition: spi.h:174
spi_transaction::select
enum SPISlaveSelect select
slave selection behavior
Definition: spi.h:154
spi2_arch_init
void spi2_arch_init(void)
Architecture dependent SPI2 initialization.
Definition: spi_arch.c:442
SPIUnselect
@ SPIUnselect
slave is not selected but unselected after transaction
Definition: spi.h:65
gpio_clear
static void gpio_clear(ioportid_t port, uint16_t pin)
Clear a gpio output to low level.
Definition: gpio_arch.h:108
SPIDiv4
@ SPIDiv4
Definition: spi.h:121
spi_init
Definition: spi_arch.c:58
SPI_SELECT_SLAVE0_PORT
#define SPI_SELECT_SLAVE0_PORT
Definition: board.h:469
spi_init::name
char * name
Definition: spi_arch.c:63
SPI_SELECT_SLAVE1_PIN
#define SPI_SELECT_SLAVE1_PIN
Definition: board.h:473
spi_transaction::after_cb
SPICallback after_cb
NULL or function called after the transaction.
Definition: spi.h:161
spi_submit
bool spi_submit(struct spi_periph *p, struct spi_transaction *t)
Submit SPI transaction.
Definition: spi_arch.c:508
SPITransFailed
@ SPITransFailed
Definition: spi.h:100
thd_spi
static void thd_spi(void *arg)
Default spi thread.
Definition: spi_arch.c:399
spi_resume
bool spi_resume(struct spi_periph *p, uint8_t slave)
spi_resume() function
Definition: spi_arch.c:670
SPIDiv128
@ SPIDiv128
Definition: spi.h:126
SPI_SELECT_SLAVE1_PORT
#define SPI_SELECT_SLAVE1_PORT
Definition: board.h:472
spi_slave_unselect
void spi_slave_unselect(uint8_t slave)
spi_slave_unselect() function
Definition: spi_arch.c:598
SPICpolIdleHigh
@ SPICpolIdleHigh
CPOL = 1.
Definition: spi.h:84
THD_WORKING_AREA
static THD_WORKING_AREA(wa_thd_spi1, SPI_THREAD_STACK_SIZE)
SPI_SELECT_SLAVE2_PORT
#define SPI_SELECT_SLAVE2_PORT
Definition: board.h:475
SPIDiv32
@ SPIDiv32
Definition: spi.h:124
SPIDiv64
@ SPIDiv64
Definition: spi.h:125
spi_slave_select
void spi_slave_select(uint8_t slave)
spi_slave_select() function
Definition: spi_arch.c:541
spi_lock
bool spi_lock(struct spi_periph *p, uint8_t slave)
spi_lock() function
Definition: spi_arch.c:656
spi_transaction::input_length
uint16_t input_length
number of data words to read
Definition: spi.h:151
SPI_SELECT_SLAVE2_PIN
#define SPI_SELECT_SLAVE2_PIN
Definition: board.h:476
gpio.h
spi_transaction::slave_idx
uint8_t slave_idx
slave id: SPI_SLAVE0 to SPI_SLAVE4
Definition: spi.h:153
ram_arch.h
spi_resolve_slave_port
static ioportid_t spi_resolve_slave_port(uint8_t slave)
Resolve slave port.
Definition: spi_arch.c:75
SPISelect
@ SPISelect
slave is selected before transaction but not unselected
Definition: spi.h:64
spi_transaction::input_buf
volatile uint8_t * input_buf
pointer to receive buffer for DMA
Definition: spi.h:149
SPILSBFirst
@ SPILSBFirst
Definition: spi.h:113
SPICphaEdge2
@ SPICphaEdge2
CPHA = 1.
Definition: spi.h:75
SPI_SELECT_SLAVE5_PIN
#define SPI_SELECT_SLAVE5_PIN
Definition: chimera.h:532
SPI_DMA_BUF_LEN
#define SPI_DMA_BUF_LEN
Definition: spi_arch.c:54
SPI_SELECT_SLAVE5_PORT
#define SPI_SELECT_SLAVE5_PORT
Definition: chimera.h:531
spi1
process_rx_dma_interrupt & spi1
receive transferred over DMA
Definition: spi_arch.c:967
SPI_SELECT_SLAVE4_PIN
#define SPI_SELECT_SLAVE4_PIN
Definition: board.h:482
spi1_arch_init
void spi1_arch_init(void)
Architecture dependent SPI1 initialization.
Definition: spi_arch.c:423
spi_transaction::before_cb
SPICallback before_cb
NULL or function called before the transaction.
Definition: spi.h:160
FALSE
#define FALSE
Definition: std.h:5
SPIIdle
@ SPIIdle
Definition: spi.h:107
TRUE
#define TRUE
Definition: std.h:4
uint16_t
unsigned short uint16_t
Typedef defining 16 bit unsigned short type.
Definition: vl53l1_types.h:88
gpio_set
static void gpio_set(ioportid_t port, uint16_t pin)
Set a gpio output to high level.
Definition: gpio_arch.h:98
SPIDiv16
@ SPIDiv16
Definition: spi.h:123
SPIDiv256
@ SPIDiv256
Definition: spi.h:127
spi_init_slaves
void spi_init_slaves(void)
spi_init_slaves() function
Definition: spi_arch.c:684
SPI_TRANSACTION_QUEUE_LEN
#define SPI_TRANSACTION_QUEUE_LEN
SPI transaction queue length.
Definition: spi.h:169
spi_transaction::status
enum SPITransactionStatus status
Definition: spi.h:162
SPIDiv2
@ SPIDiv2
Definition: spi.h:120
SPIDss16bit
@ SPIDss16bit
Definition: spi.h:91
p
static float p[2][2]
Definition: ins_alt_float.c:268
SPIDiv8
@ SPIDiv8
Definition: spi.h:122