imu_crista_arch.c

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/*
 * Copyright (C) 2008-2009 Antoine Drouin <poinix@gmail.com>
 *
 * This file is part of paparazzi.
 *
 * paparazzi is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 *
 * paparazzi is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with paparazzi; see the file COPYING.  If not, write to
 * the Free Software Foundation, 59 Temple Place - Suite 330,
 * Boston, MA 02111-1307, USA.
 */

#include "subsystems/imu.h"

#include "LPC21xx.h"
#include "armVIC.h"
#include "ssp_hw.h"
#include BOARD_CONFIG

#define ADS8344_SS_IODIR IO0DIR
#define ADS8344_SS_IOSET IO0SET
#define ADS8344_SS_IOCLR IO0CLR
#define ADS8344_SS_PIN   20

#define ADS8344Select()   SetBit(ADS8344_SS_IOCLR,ADS8344_SS_PIN)
#define ADS8344Unselect() SetBit(ADS8344_SS_IOSET,ADS8344_SS_PIN)

#define POWER_MODE (1 << 1 | 1)
#define SGL_DIF 1 // Single ended

/* SSPCR0 settings */
#define SSP_DSS  0x07 << 0  /* data size            : 8 bits   */
#define SSP_FRF  0x00 << 4  /* frame format         : SPI      */
#define SSP_CPOL 0x00 << 6  /* clock polarity       : idle low */
#define SSP_CPHA 0x00 << 7  /* clock phase          : 1        */
#define SSP_SCR  0x09 << 8  /* serial clock rate    : 1MHz     */

/* SSPCR1 settings */
#define SSP_LBM  0x00 << 0  /* loopback mode        : disabled */
#define SSP_SSE  0x00 << 1  /* SSP enable           : disabled */
#define SSP_MS   0x00 << 2  /* master slave mode    : master   */
#define SSP_SOD  0x00 << 3  /* slave output disable : disabled */

static void SPI1_ISR(void) __attribute__((naked));
static uint8_t channel;

#warning "This driver should be updated to use the new SPI peripheral"

void imu_crista_arch_init(void)
{
  channel = 0;

  /* setup pins for SSP (SCK, MISO, MOSI) */
  PINSEL1 |= 2 << 2 | 2 << 4 | 2 << 6;

  /* setup SSP */
  SSPCR0 = SSP_DSS | SSP_FRF | SSP_CPOL | SSP_CPHA | SSP_SCR;
  SSPCR1 = SSP_LBM | SSP_MS | SSP_SOD;
  SSPCPSR = 2; /* -> 50kHz */

  /* initialize interrupt vector */
  VICIntSelect &= ~VIC_BIT(VIC_SPI1);   // SPI1 selected as IRQ
  VICIntEnable = VIC_BIT(VIC_SPI1);     // SPI1 interrupt enabled
  _VIC_CNTL(SPI1_VIC_SLOT) = VIC_ENABLE | VIC_SPI1;
  _VIC_ADDR(SPI1_VIC_SLOT) = (uint32_t)SPI1_ISR;    // address of the ISR

  /* setup slave select */
  /* configure SS pin */
  SetBit(ADS8344_SS_IODIR,  ADS8344_SS_PIN);   /* pin is output  */
  ADS8344Unselect();                           /* pin low        */
}


static inline void read_values(void)
{
  uint8_t foo __attribute__((unused)) = SSPDR;
  uint8_t msb = SSPDR;
  uint8_t lsb = SSPDR;
  uint8_t llsb = SSPDR;
  ADS8344_values[channel] = (msb << 8 | lsb) << 1 | llsb >> 7;
}

static inline void send_request(void)
{
  uint8_t control = 1 << 7 | channel << 4 | SGL_DIF << 2 | POWER_MODE;
  SSP_Send(control);
  SSP_Send(0);
  SSP_Send(0);
  SSP_Send(0);
}

void ADS8344_start(void)
{
  ADS8344Select();
  SSP_ClearRti();
  SSP_EnableRti();
  SSP_Enable();
  send_request();
}

void SPI1_ISR(void)
{
  ISR_ENTRY();
  read_values();
  channel++;
  if (channel > 7 - 1) {
    channel = 0;
    ADS8344_available = TRUE;
    ADS8344Unselect();
  } else {
    send_request();
  }

  SSP_ClearRti();

  VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
  ISR_EXIT();
}