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spi_slave_hs_arch.c
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2  * Copyright (C) 2011 The Paparazzi Team
3  *
4  * This file is part of paparazzi.
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14  * GNU General Public License for more details.
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21 
29 #include "spi_slave_hs_arch.h"
30 #include "mcu_periph/spi.h"
31 
32 #include BOARD_CONFIG
33 #include "std.h"
34 #include "mcu.h"
35 #include "led.h"
36 #include "LPC21xx.h"
37 #include "ssp_hw.h"
38 #include "pprz_debug.h"
39 #include "armVIC.h"
40 
42 
43 /* High Speed SPI Slave Circular Buffer */
48 
49 /* Prototypes */
50 static void SSP_ISR(void) __attribute__((naked));
51 
52 /* SSPCR0 settings */
53 #define SSP_DDS 0x07 << 0 /* data size : 8 bits */
54 //#define SSP_DDS 0x0F << 0 /* data size : 16 bits */
55 #define SSP_FRF 0x00 << 4 /* frame format : SPI */
56 #define SSP_CPOL 0x00 << 6 /* clock polarity : data captured on first clock transition */
57 #define SSP_CPHA 0x00 << 7 /* clock phase : SCK idles low */
58 #define SSP_SCR 0x00 << 8 /* serial clock rate : divide by 1 */
59 
60 #define SSPCR0_VAL (SSP_DDS | SSP_FRF | SSP_CPOL | SSP_CPHA | SSP_SCR )
61 
62 /* SSPCR1 settings */
63 #define SSP_LBM 0x00 << 0 /* loopback mode : disabled */
64 #define SSP_SSE 0x00 << 1 /* SSP enable : enable later when init ready */
65 #define SSP_MS 0x01 << 2 /* master slave mode : slave */
66 #define SSP_SOD 0x00 << 3 /* slave output disable : don't care when master */
67 
68 #define SSPCR1_VAL (SSP_LBM | SSP_SSE | SSP_MS | SSP_SOD )
69 
70 /* SSPCPSR settings
71  * min value as master: 2
72  * min value as slave: 12
73  */
74 #if (PCLK == 15000000)
75 #define CPSDVSR 12
76 #else
77 
78 #if (PCLK == 30000000)
79 #define CPSDVSR 24
80 #else
81 
82 #if (PCLK == 60000000)
83 #define CPSDVSR 28
84 #else
85 
86 #error unknown PCLK frequency
87 #endif
88 #endif
89 #endif
90 
91 #define SSP_PINSEL1_SCK (2<<2)
92 #define SSP_PINSEL1_MISO (2<<4)
93 #define SSP_PINSEL1_MOSI (2<<6)
94 #define SSP_PINSEL1_SSEL (2<<8)
95 
96 
97 #define SSP_Write(X) SSPDR=(X)
98 #define SSP_Read() SSPDR
99 #define SSP_Status() SSPSR
100 
102 #ifndef SPI1_VIC_SLOT
103 #define SPI1_VIC_SLOT 7
104 #endif
105 
106 
107 // Functions for the generic device API
108 static int spi_slave_hs_check_free_space(struct spi_slave_hs *p __attribute__((unused)), uint8_t len __attribute__((unused)))
109 {
110  return TRUE;
111 }
112 
113 static void spi_slave_hs_transmit(struct spi_slave_hs *p __attribute__((unused)), uint8_t byte)
114 {
116  if (temp != spi_slave_hs_tx_extract_idx) /* there is room left */
117  {
120  }
121 }
122 
123 static void spi_slave_hs_send(struct spi_slave_hs *p __attribute__((unused))) { }
124 
125 static int spi_slave_hs_char_available(struct spi_slave_hs *p __attribute__((unused)))
126 {
128 }
129 
130 static uint8_t spi_slave_hs_getch(struct spi_slave_hs *p __attribute__((unused)))
131 {
134  return ret;
135 }
136 
138 {
139 
140  /* setup pins for SSP (SCK, MISO, MOSI) */
142 
143  /* setup SSP */
144  // Control Registers
145  SSPCR0 = SSPCR0_VAL;
146  SSPCR1 = SSPCR1_VAL;
147  // Clock Prescale Registers
148  SSPCPSR = CPSDVSR;
149 
150  /* initialize interrupt vector */
151  VICIntSelect &= ~VIC_BIT(VIC_SPI1); /* SPI1 selected as IRQ */
152  VICIntEnable = VIC_BIT(VIC_SPI1); /* enable it */
154  _VIC_ADDR(SPI1_VIC_SLOT) = (uint32_t)SSP_ISR; /* address of the ISR */
155 
156 
157  // Enable SPI Slave
158  SetBit(SSPCR1, SSE);
159 
160  // Enable Receive interrupt
161  SetBit(SSPIMSC, RXIM);
162 
163  // Configure generic device
164  spi_slave_hs.device.periph = (void *)(&spi_slave_hs);
170 
171 }
172 
173 /*
174  * SSP Status:
175  *
176  * ROVR Read Overrun
177  * WCOL Write Collision (send new byte during a transfer in progress
178  * ABRT SSEL inactive before end of transfer
179  *
180  *
181  */
182 
183 
184 static void SSP_ISR(void)
185 {
186  ISR_ENTRY();
187 
188  //LED_TOGGLE(3);
189 
190  // If any TX bytes are pending
194  SSP_Write(ret);
195  } else {
196  SSP_Write(0x00);
197  }
198 
199 
200  //do
201  {
202  uint16_t temp;
203 
204  // calc next insert index & store character
207 
208  // check for more room in queue
209  if (temp != spi_slave_hs_rx_extract_idx) {
210  spi_slave_hs_rx_insert_idx = temp; // update insert index
211  }
212 
213  // else overrun
214  }
215  // while FIFO not empty
216  //while (SSPSR & RNE);
217 
218  /*
219  // loop until not more interrupt sources
220  while (((iid = U0IIR) & UIIR_NO_INT) == 0)
221  while (U0LSR & ULSR_THRE)
222  {
223  // check if more data to send
224  if (uart0_tx_insert_idx != uart0_tx_extract_idx)
225  {
226  U0THR = uart0_tx_buffer[uart0_tx_extract_idx];
227  uart0_tx_extract_idx++;
228  uart0_tx_extract_idx %= UART0_TX_BUFFER_SIZE;
229  }
230  else
231  {
232  // no
233  uart0_tx_running = 0; // clear running flag
234  break;
235  }
236  }
237 
238  */
239  VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
240  ISR_EXIT();
241 }
242 
#define VICIntSelect
Definition: LPC21xx.h:430
#define SPI1_VIC_SLOT
default initial settings
unsigned short uint16_t
Definition: types.h:16
#define SSPCPSR
Definition: LPC21xx.h:226
#define _VIC_CNTL(idx)
Definition: armVIC.h:19
#define SSPCR0_VAL
uint8_t spi_slave_hs_rx_buffer[SPI_SLAVE_HS_RX_BUFFER_SIZE]
#define RXIM
Definition: LPC21xx.h:273
#define SSPCR1_VAL
void spi_slave_hs_init(void)
#define SSP_PINSEL1_SSEL
#define SSPCR0
Definition: LPC21xx.h:222
uint16_t spi_slave_hs_rx_extract_idx
#define _VIC_ADDR(idx)
Definition: armVIC.h:20
static int spi_slave_hs_char_available(struct spi_slave_hs *p)
Architecture independent SPI (Serial Peripheral Interface) API.
#define SSP_PINSEL1_SCK
#define TRUE
Definition: std.h:4
#define SSP_Write(X)
#define SPI_SLAVE_HS_TX_BUFFER_SIZE
#define VICVectAddr
Definition: LPC21xx.h:436
unsigned long uint32_t
Definition: types.h:18
static void SSP_ISR(void)
uint8_t spi_slave_hs_tx_extract_idx
#define VIC_BIT(chan)
Definition: lpcVIC.h:105
uint8_t spi_slave_hs_tx_insert_idx
Arch independent mcu ( Micro Controller Unit ) utilities.
#define SPI_SLAVE_HS_RX_BUFFER_SIZE
struct link_device device
Generic device interface.
unsigned char uint8_t
Definition: types.h:14
static uint8_t spi_slave_hs_getch(struct spi_slave_hs *p)
uint8_t spi_slave_hs_tx_buffer[SPI_SLAVE_HS_TX_BUFFER_SIZE]
#define ISR_EXIT()
Definition: armVIC.h:61
#define VICIntEnable
Definition: LPC21xx.h:431
#define PINSEL1
Definition: LPC21xx.h:348
static void spi_slave_hs_send(struct spi_slave_hs *p)
#define SSP_PINSEL1_MOSI
#define VIC_SPI1
Definition: lpcVIC.h:81
arch independent LED (Light Emitting Diodes) API
static float p[2][2]
Highspeed SPI Slave Interface.
#define SSP_PINSEL1_MISO
static int spi_slave_hs_check_free_space(struct spi_slave_hs *p, uint8_t len)
#define SSPCR1
Definition: LPC21xx.h:223
#define SSE
Definition: LPC21xx.h:266
#define SSP_Read()
uint16_t spi_slave_hs_rx_insert_idx
#define SSPIMSC
Definition: LPC21xx.h:227
#define ISR_ENTRY()
Definition: armVIC.h:40
#define VIC_ENABLE
Definition: lpcVIC.h:102
static void spi_slave_hs_transmit(struct spi_slave_hs *p, uint8_t byte)