Paparazzi UAS  v5.18.0_stable
Paparazzi is a free software Unmanned Aircraft System.
lpcTMR.h
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1 /******************************************************************************
2  *
3  * $RCSfile$
4  * $Revision$
5  *
6  * Header file for Philips LPC ARM Processors.
7  * Copyright 2004 R O SoftWare
8  *
9  * No guarantees, warrantees, or promises, implied or otherwise.
10  * May be used for hobby or commercial purposes provided copyright
11  * notice remains intact.
12  *
13  *****************************************************************************/
14 #ifndef INC_LPC_TMR_H
15 #define INC_LPC_TMR_H
16 
17 // Timer & PWM Registers
18 typedef struct
19 {
20  REG32 ir; // Interrupt Register
21  REG32 tcr; // Timer Control Register
22  REG32 tc; // Timer Counter
23  REG32 pr; // Prescale Register
24  REG32 pc; // Prescale Counter Register
25  REG32 mcr; // Match Control Register
26  REG32 mr0; // Match Register 0
27  REG32 mr1; // Match Register 1
28  REG32 mr2; // Match Register 2
29  REG32 mr3; // Match Register 3
30  REG32 ccr; // Capture Control Register
31  REG32 cr0; // Capture Register 0
32  REG32 cr1; // Capture Register 1
33  REG32 cr2; // Capture Register 2
34  REG32 cr3; // Capture Register 3
35  REG32 emr; // External Match Register
36  REG32 mr4; // Match Register 4
37  REG32 mr5; // Match Register 5
38  REG32 mr6; // Match Register 6
39  REG32 pcr; // Control Register
40  REG32 ler; // Latch Enable Register
41 } pwmTmrRegs_t;
42 
43 // Timer Interrupt Register Bit Definitions
44 #define TIR_MR0I (1 << 0) // Interrupt flag for match channel 0
45 #define TIR_MR1I (1 << 1) // Interrupt flag for match channel 1
46 #define TIR_MR2I (1 << 2) // Interrupt flag for match channel 2
47 #define TIR_MR3I (1 << 3) // Interrupt flag for match channel 3
48 #define TIR_CR0I (1 << 4) // Interrupt flag for capture channel 0 event
49 #define TIR_CR1I (1 << 5) // Interrupt flag for capture channel 1 event
50 #define TIR_CR2I (1 << 6) // Interrupt flag for capture channel 2 event
51 #define TIR_CR3I (1 << 7) // Interrupt flag for capture channel 3 event
52 
53 // Timer Control Register Bit Definitions
54 #define TCR_ENABLE (1 << 0)
55 #define TCR_RESET (1 << 1)
56 
57 
58 // Timer Match Control Register Bit Definitions
59 #define TMCR_MR0_I (1 << 0) // Enable Interrupt when MR0 matches TC
60 #define TMCR_MR0_R (1 << 1) // Enable Reset of TC upon MR0 match
61 #define TMCR_MR0_S (1 << 2) // Enable Stop of TC upon MR0 match
62 #define TMCR_MR1_I (1 << 3) // Enable Interrupt when MR1 matches TC
63 #define TMCR_MR1_R (1 << 4) // Enable Reset of TC upon MR1 match
64 #define TMCR_MR1_S (1 << 5) // Enable Stop of TC upon MR1 match
65 #define TMCR_MR2_I (1 << 6) // Enable Interrupt when MR2 matches TC
66 #define TMCR_MR2_R (1 << 7) // Enable Reset of TC upon MR2 match
67 #define TMCR_MR2_S (1 << 8) // Enable Stop of TC upon MR2 match
68 #define TMCR_MR3_I (1 << 9) // Enable Interrupt when MR3 matches TC
69 #define TMCR_MR3_R (1 << 10) // Enable Reset of TC upon MR3 match
70 #define TMCR_MR3_S (1 << 11) // Enable Stop of TC upon MR3 match
71 
72 /* PWMIR ( Interrupt Register ) bits definitions */
73 #define PWMIR_MR0I _BV(0) /* Interrupt flag for match channel 0 */
74 #define PWMIR_MR1I _BV(1) /* Interrupt flag for match channel 1 */
75 #define PWMIR_MR2I _BV(2) /* Interrupt flag for match channel 2 */
76 #define PWMIR_MR3I _BV(3) /* Interrupt flag for match channel 3 */
77 #define PWMIR_MR4I _BV(8) /* Interrupt flag for match channel 4 */
78 #define PWMIR_MR5I _BV(9) /* Interrupt flag for match channel 5 */
79 #define PWMIR_MR6I _BV(10) /* Interrupt flag for match channel 6 */
80 #define PWMIR_MASK (0x070F)
81 
82 /* PWMTCR ( Timer Control Register ) bits definitions */
83 #define PWMTCR_COUNTER_ENABLE _BV(0) /* enable PWM timer counter */
84 #define PWMTCR_COUNTER_RESET _BV(1) /* reset PWM timer counter */
85 #define PWMTCR_PWM_ENABLE _BV(3) /* enable PWM mode */
86 
87 /* PWMMCR ( Match Control Register ) bits definitions */
88 #define PWMMCR_MR0I (1 << 0) /* enable interrupt on match channel 0 */
89 #define PWMMCR_MR0R (1 << 1) /* enable reset on match channel 0 */
90 #define PWMMCR_MR0S (1 << 2) /* enable stop on match channel 0 */
91 #define PWMMCR_MR1I (1 << 3) /* enable interrupt on match channel 1 */
92 #define PWMMCR_MR1R (1 << 4) /* enable reset on match channel 1 */
93 #define PWMMCR_MR1S (1 << 5) /* enable stop on match channel 1 */
94 #define PWMMCR_MR2I (1 << 6) /* enable interrupt on match channel 2 */
95 #define PWMMCR_MR2R (1 << 7) /* enable reset on match channel 2 */
96 #define PWMMCR_MR2S (1 << 8) /* enable stop on match channel 2 */
97 #define PWMMCR_MR3I (1 << 9) /* enable interrupt on match channel 3 */
98 #define PWMMCR_MR3R (1 << 10) /* enable reset on match channel 3 */
99 #define PWMMCR_MR3S (1 << 11) /* enable stop on match channel 3 */
100 #define PWMMCR_MR4I (1 << 12) /* enable interrupt on match channel 4 */
101 #define PWMMCR_MR4R (1 << 13) /* enable reset on match channel 4 */
102 #define PWMMCR_MR4S (1 << 14) /* enable stop on match channel 4 */
103 #define PWMMCR_MR5I (1 << 15) /* enable interrupt on match channel 5 */
104 #define PWMMCR_MR5R (1 << 16) /* enable reset on match channel 5 */
105 #define PWMMCR_MR5S (1 << 17) /* enable stop on match channel 5 */
106 #define PWMMCR_MR6I (1 << 18) /* enable interrupt on match channel 6 */
107 #define PWMMCR_MR6R (1 << 19) /* enable reset on match channel 6 */
108 #define PWMMCR_MR6S (1 << 20) /* enable stop on match channel 6 */
109 
110 /* PWMPCR ( Control Register ) bit definitions */
111 #define PWMPCR_SEL2 _BV(2) /* select double edge for PWM2 output */
112 #define PWMPCR_SEL3 _BV(3) /* select double edge for PWM3 output */
113 #define PWMPCR_SEL4 _BV(4) /* select double edge for PWM4 output */
114 #define PWMPCR_SEL5 _BV(5) /* select double edge for PWM5 output */
115 #define PWMPCR_SEL6 _BV(6) /* select double edge for PWM6 output */
116 #define PWMPCR_ENA1 _BV(9) /* PWM1 output enabled */
117 #define PWMPCR_ENA2 _BV(10) /* PWM2 output enabled */
118 #define PWMPCR_ENA3 _BV(11) /* PWM3 output enabled */
119 #define PWMPCR_ENA4 _BV(12) /* PWM4 output enabled */
120 #define PWMPCR_ENA5 _BV(13) /* PWM5 output enabled */
121 #define PWMPCR_ENA6 _BV(14) /* PWM6 output enabled */
122 
123 /* PWMLER ( Latch Enable Register ) bit definitions */
124 #define PWMLER_LATCH0 _BV(0) /* latch last MATCH0 register value */
125 #define PWMLER_LATCH1 _BV(1) /* latch last MATCH1 register value */
126 #define PWMLER_LATCH2 _BV(2) /* latch last MATCH2 register value */
127 #define PWMLER_LATCH3 _BV(3) /* latch last MATCH3 register value */
128 #define PWMLER_LATCH4 _BV(4) /* latch last MATCH4 register value */
129 #define PWMLER_LATCH5 _BV(5) /* latch last MATCH5 register value */
130 #define PWMLER_LATCH6 _BV(6) /* latch last MATCH6 register value */
131 
132 
133 // Timer Capture Control Register Bit Definitions
134 #define TCCR_CR0_R (1 << 0) // Enable Rising edge on CAPn.0 will load TC to CR0
135 #define TCCR_CR0_F (1 << 1) // Enable Falling edge on CAPn.0 will load TC to CR0
136 #define TCCR_CR0_I (1 << 2) // Enable Interrupt on load of CR0
137 #define TCCR_CR1_R (1 << 3) // Enable Rising edge on CAPn.1 will load TC to CR1
138 #define TCCR_CR1_F (1 << 4) // Enable Falling edge on CAPn.1 will load TC to CR1
139 #define TCCR_CR1_I (1 << 5) // Enable Interrupt on load of CR1
140 #define TCCR_CR2_R (1 << 6) // Enable Rising edge on CAPn.2 will load TC to CR2
141 #define TCCR_CR2_F (1 << 7) // Enable Falling edge on CAPn.2 will load TC to CR2
142 #define TCCR_CR2_I (1 << 8) // Enable Interrupt on load of CR2
143 #define TCCR_CR3_R (1 << 9) // Enable Rising edge on CAPn.3 will load TC to CR3
144 #define TCCR_CR3_F (1 << 10) // Enable Falling edge on CAPn.3 will load TC to CR3
145 #define TCCR_CR3_I (1 << 11) // Enable Interrupt on load of CR3
146 
147 
148 // Timer External Match Register
149 #define TEMR_EM0 (1 << 0) // reflects state of output match 0
150 #define TEMR_EM1 (1 << 1) // reflects state of output match 1
151 #define TEMR_EM2 (1 << 2) // reflects state of output match 2
152 #define TEMR_EM3 (1 << 3) // reflects state of output match 3
153 #define TEMR_EMC0_0 (0 << 4) // configure match 0 pin behaviour
154 #define TEMR_EMC0_1 (1 << 4) // configure match 0 pin behaviour
155 #define TEMR_EMC0_2 (2 << 4) // configure match 0 pin behaviour
156 #define TEMR_EMC0_3 (3 << 4) // configure match 0 pin behaviour
157 #define TEMR_EMC1_0 (0 << 6) // configure match 1 pin behaviour
158 #define TEMR_EMC1_1 (1 << 6) // configure match 1 pin behaviour
159 #define TEMR_EMC1_2 (2 << 6) // configure match 1 pin behaviour
160 #define TEMR_EMC1_3 (3 << 6) // configure match 0 pin behaviour
161 #define TEMR_EMC2_0 (0 << 8) // configure match 1 pin behaviour
162 #define TEMR_EMC2_1 (1 << 8) // configure match 1 pin behaviour
163 #define TEMR_EMC2_2 (2 << 8) // configure match 1 pin behaviour
164 #define TEMR_EMC2_3 (3 << 8) // configure match 0 pin behaviour
165 #define TEMR_EMC3_0 (0 << 10) // configure match 1 pin behaviour
166 #define TEMR_EMC3_1 (1 << 10) // configure match 1 pin behaviour
167 #define TEMR_EMC3_2 (2 << 10) // configure match 1 pin behaviour
168 #define TEMR_EMC3_3 (3 << 10) // configure match 0 pin behaviour
169 
170 
171 #endif
REG32
#define REG32
Definition: LPC21xx.h:20
pwmTmrRegs_t
Definition: lpcTMR.h:18