Paparazzi UAS  v5.18.0_stable
Paparazzi is a free software Unmanned Aircraft System.
LPC21xx.h
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1 /******************************************************************************
2  *
3  * $RCSfile$
4  * $Revision$
5  *
6  * Header file for Philips LPC21xx ARM Processors
7  * Copyright 2004 R O SoftWare
8  *
9  * No guarantees, warrantees, or promises, implied or otherwise.
10  * May be used for hobby or commercial purposes provided copyright
11  * notice remains intact.
12  *
13  *****************************************************************************/
14 #ifndef INC_LPC21xx_H
15 #define INC_LPC21xx_H
16 
17 
18 #define REG_8 volatile unsigned char
19 #define REG16 volatile unsigned short
20 #define REG32 volatile unsigned long
21 
22 #include "lpcWD.h"
23 #include "lpcTMR.h"
24 #include "lpcUART.h"
25 #include "lpcI2C.h"
26 #include "lpcSPI.h"
27 #include "lpcRTC.h"
28 #include "lpcGPIO.h"
29 #include "lpcPIN.h"
30 #include "lpcADC.h"
31 #include "lpcSCB.h"
32 #include "lpcVIC.h"
33 #include "lpcCAN.h"
34 
36 // Watchdog
37 #define WD ((wdRegs_t *)0xE0000000)
38 
39 // Watchdog Registers
40 #define WDMOD WD->mod /* Watchdog Mode Register */
41 #define WDTC WD->tc /* Watchdog Time Constant Register */
42 #define WDFEED WD->feed /* Watchdog Feed Register */
43 #define WDTV WD->tv /* Watchdog Time Value Register */
44 
46 // Timer 0
47 #define TMR0 ((pwmTmrRegs_t *)0xE0004000)
48 
49 // Timer 0 Registers
50 #define T0IR TMR0->ir /* Interrupt Register */
51 #define T0TCR TMR0->tcr /* Timer Control Register */
52 #define T0TC TMR0->tc /* Timer Counter */
53 #define T0PR TMR0->pr /* Prescale Register */
54 #define T0PC TMR0->pc /* Prescale Counter Register */
55 #define T0MCR TMR0->mcr /* Match Control Register */
56 #define T0MR0 TMR0->mr0 /* Match Register 0 */
57 #define T0MR1 TMR0->mr1 /* Match Register 1 */
58 #define T0MR2 TMR0->mr2 /* Match Register 2 */
59 #define T0MR3 TMR0->mr3 /* Match Register 3 */
60 #define T0CCR TMR0->ccr /* Capture Control Register */
61 #define T0CR0 TMR0->cr0 /* Capture Register 0 */
62 #define T0CR1 TMR0->cr1 /* Capture Register 1 */
63 #define T0CR2 TMR0->cr2 /* Capture Register 2 */
64 #define T0CR3 TMR0->cr3 /* Capture Register 3 */
65 #define T0EMR TMR0->emr /* External Match Register */
66 
68 // Timer 1
69 #define TMR1 ((pwmTmrRegs_t *)0xE0008000)
70 
71 // Timer 1 Registers
72 #define T1IR TMR1->ir /* Interrupt Register */
73 #define T1TCR TMR1->tcr /* Timer Control Register */
74 #define T1TC TMR1->tc /* Timer Counter */
75 #define T1PR TMR1->pr /* Prescale Register */
76 #define T1PC TMR1->pc /* Prescale Counter Register */
77 #define T1MCR TMR1->mcr /* Match Control Register */
78 #define T1MR0 TMR1->mr0 /* Match Register 0 */
79 #define T1MR1 TMR1->mr1 /* Match Register 1 */
80 #define T1MR2 TMR1->mr2 /* Match Register 2 */
81 #define T1MR3 TMR1->mr3 /* Match Register 3 */
82 #define T1CCR TMR1->ccr /* Capture Control Register */
83 #define T1CR0 TMR1->cr0 /* Capture Register 0 */
84 #define T1CR1 TMR1->cr1 /* Capture Register 1 */
85 #define T1CR2 TMR1->cr2 /* Capture Register 2 */
86 #define T1CR3 TMR1->cr3 /* Capture Register 3 */
87 #define T1EMR TMR1->emr /* External Match Register */
88 
90 // Pulse Width Modulator (PWM)
91 #define PWM ((pwmTmrRegs_t *)0xE0014000)
92 
93 // PWM Registers
94 #define PWMIR PWM->ir /* Interrupt Register */
95 #define PWMTCR PWM->tcr /* Timer Control Register */
96 #define PWMTC PWM->tc /* Timer Counter */
97 #define PWMPR PWM->pr /* Prescale Register */
98 #define PWMPC PWM->pc /* Prescale Counter Register */
99 #define PWMMCR PWM->mcr /* Match Control Register */
100 #define PWMMR0 PWM->mr0 /* Match Register 0 */
101 #define PWMMR1 PWM->mr1 /* Match Register 1 */
102 #define PWMMR2 PWM->mr2 /* Match Register 2 */
103 #define PWMMR3 PWM->mr3 /* Match Register 3 */
104 #define PWMMR4 PWM->mr4 /* Match Register 4 */
105 #define PWMMR5 PWM->mr5 /* Match Register 5 */
106 #define PWMMR6 PWM->mr6 /* Match Register 6 */
107 #define PWMPCR PWM->pcr /* Control Register */
108 #define PWMLER PWM->ler /* Latch Enable Register */
109 
111 // Universal Asynchronous Receiver Transmitter 0 (UART0)
112 #define UART0_BASE ((uartRegs_t *)0xE000C000)
113 #define U0_PINSEL (0x00000005) /* PINSEL0 Value for UART0 */
114 #define U0_PINMASK (0x0000000F) /* PINSEL0 Mask for UART0 */
115 #define U0_PINSEL_RX (0x00000004) /* PINSEL0 Value for UART0 RX only */
116 #define U0_PINMASK_RX (0x0000000C) /* PINSEL0 Mask for UART0 RX only */
117 
118 // UART0 Registers
119 #define U0RBR UART0_BASE->rbr /* Receive Buffer Register */
120 #define U0THR UART0_BASE->thr /* Transmit Holding Register */
121 #define U0IER UART0_BASE->ier /* Interrupt Enable Register */
122 #define U0IIR UART0_BASE->iir /* Interrupt ID Register */
123 #define U0FCR UART0_BASE->fcr /* FIFO Control Register */
124 #define U0LCR UART0_BASE->lcr /* Line Control Register */
125 #define U0LSR UART0_BASE->lsr /* Line Status Register */
126 #define U0SCR UART0_BASE->scr /* Scratch Pad Register */
127 #define U0DLL UART0_BASE->dll /* Divisor Latch Register (LSB) */
128 #define U0DLM UART0_BASE->dlm /* Divisor Latch Register (MSB) */
129 
131 // Universal Asynchronous Receiver Transmitter 1 (UART1)
132 #define UART1_BASE ((uartRegs_t *)0xE0010000)
133 #define U1_PINSEL (0x00050000) /* PINSEL0 Value for UART1 */
134 #define U1_PINMASK (0x000F0000) /* PINSEL0 Mask for UART1 */
135 #define U1_PINSEL_RX (0x00040000) /* PINSEL0 Value for UART1 RX only */
136 #define U1_PINMASK_RX (0x000C0000) /* PINSEL0 Mask for UART1 RX only */
137 
138 // UART1 Registers
139 #define U1RBR UART1_BASE->rbr /* Receive Buffer Register */
140 #define U1THR UART1_BASE->thr /* Transmit Holding Register */
141 #define U1IER UART1_BASE->ier /* Interrupt Enable Register */
142 #define U1IIR UART1_BASE->iir /* Interrupt ID Register */
143 #define U1FCR UART1_BASE->fcr /* FIFO Control Register */
144 #define U1LCR UART1_BASE->lcr /* Line Control Register */
145 #define U1MCR UART1_BASE->mcr /* MODEM Control Register */
146 #define U1LSR UART1_BASE->lsr /* Line Status Register */
147 #define U1MSR UART1_BASE->msr /* MODEM Status Register */
148 #define U1SCR UART1_BASE->scr /* Scratch Pad Register */
149 #define U1DLL UART1_BASE->dll /* Divisor Latch Register (LSB) */
150 #define U1DLM UART1_BASE->dlm /* Divisor Latch Register (MSB) */
151 
153 // I2C Interface
154 #define I2C0 ((i2cRegs_t *)0xE001C000)
155 
156 // I2C Registers
157 #define I2C0CONSET I2C0->conset /* Control Set Register */
158 #define I2C0STAT I2C0->stat /* Status Register */
159 #define I2C0DAT I2C0->dat /* Data Register */
160 #define I2C0ADR I2C0->adr /* Slave Address Register */
161 #define I2C0SCLH I2C0->sclh /* SCL Duty Cycle Register (high half word) */
162 #define I2C0SCLL I2C0->scll /* SCL Duty Cycle Register (low half word) */
163 #define I2C0CONCLR I2C0->conclr /* Control Clear Register */
164 
165 
166 #define I2C1 ((i2cRegs_t *)0xE005C000)
167 // I2C Registers
168 #define I2C1CONSET I2C1->conset /* Control Set Register */
169 #define I2C1STAT I2C1->stat /* Status Register */
170 #define I2C1DAT I2C1->dat /* Data Register */
171 #define I2C1ADR I2C1->adr /* Slave Address Register */
172 #define I2C1SCLH I2C1->sclh /* SCL Duty Cycle Register (high half word) */
173 #define I2C1SCLL I2C1->scll /* SCL Duty Cycle Register (low half word) */
174 #define I2C1CONCLR I2C1->conclr /* Control Clear Register */
175 
176 
177 // I2CONSET bit definition
178 
179 #define AA 2
180 #define SI 3
181 #define STO 4
182 #define STA 5
183 #define I2EN 6
184 
185 // I2CONCLR bit definition
186 
187 #define AAC 2
188 #define SIC 3
189 #define STAC 5
190 #define I2ENC 6
191 
192 
194 // Serial Peripheral Interface 0 (SPI0)
195 #define SPI0 ((spiRegs_t *)0xE0020000)
196 
197 // SPI0 Registers
198 #define S0SPCR SPI0->cr /* Control Register */
199 #define S0SPSR SPI0->sr /* Status Register */
200 #define S0SPDR SPI0->dr /* Data Register */
201 #define S0SPCCR SPI0->ccr /* Clock Counter Register */
202 #define S0SPINT SPI0->flag /* Interrupt Flag Register */
203 
204 /* S0SPINT bits definition */
205 #define SPI0IF 0
206 
207 
209 // Serial Peripheral Interface 1 (SPI1)
210 #define SPI1 ((sspRegs_t *)0xE0068000)
211 
212 // SPI1 Registers
213 //#define S1SPCR SPI1->cr /* Control Register */
214 //#define S1SPSR SPI1->sr /* Status Register */
215 //#define S1SPDR SPI1->dr /* Data Register */
216 //#define S1SPCCR SPI1->ccr /* Clock Counter Register */
217 //#define S1SPINT SPI1->flag /* Interrupt Flag Register */
218 
219 /* S1SPINT bits definition */
220 #define SPI1IF 0
221 
222 #define SSPCR0 SPI1->cr0 /* Control Register 0 */
223 #define SSPCR1 SPI1->cr1 /* Control Register 1 */
224 #define SSPDR SPI1->dr /* Data register */
225 #define SSPSR SPI1->sr /* Status register */
226 #define SSPCPSR SPI1->cpsr /* Clock prescale register */
227 #define SSPIMSC SPI1->imsc /* Interrupt mask register */
228 #define SSPRIS SPI1->ris /* Raw interrupt status register */
229 #define SSPMIS SPI1->mis /* Masked interrupt status register */
230 #define SSPICR SPI1->icr /* Interrupt clear register */
231 
232 //#define SSPCR0 (*(REG16*) 0xE0068000) /* Control Register 0 */
233 //#define SSPCR1 (*(REG_8*) 0xE0068004) /* Control Register 1 */
234 //#define SSPDR (*(REG16*) 0xE0068008) /* Data register */
235 //#define SSPSR (*(REG_8*) 0xE006800C) /* Status register */
236 //#define SSPCPSR (*(REG_8*) 0xE0068010) /* Clock prescale register */
237 //#define SSPIMSC (*(REG_8*) 0xE0068014) /* Interrupt mask register */
238 //#define SSPRIS (*(REG_8*) 0xE0068018) /* Raw interrupt status register */
239 //#define SSPMIS (*(REG_8*) 0xE006801C) /* Masked interrupt status register */
240 //#define SSPICR (*(REG_8*) 0xE0068020) /* Interrupt clear register */
241 
242 /* SSPCR0 bits definition */
243 #define DSS 0
244 #define FRF 4
245 #define CPOL 6
246 #define CPHA 7
247 #define SCR 8
248 
249 /* SSPDSS values definition */
250 #define DSS_VAL4 0x3
251 #define DSS_VAL5 0x4
252 #define DSS_VAL6 0x5
253 #define DSS_VAL7 0x6
254 #define DSS_VAL8 0x7
255 #define DSS_VAL9 0x8
256 #define DSS_VAL10 0x9
257 #define DSS_VAL11 0xA
258 #define DSS_VAL12 0xB
259 #define DSS_VAL13 0XC
260 #define DSS_VAL14 0xD
261 #define DSS_VAL15 0xE
262 #define DSS_VAL16 0xF
263 
264 /* SSPCR1 bits definition */
265 #define LBM 0
266 #define SSE 1
267 #define MS 2
268 #define SOD 3
269 
270 /* SSPIMSC bits definition */
271 #define RORIM 0
272 #define RTIM 1
273 #define RXIM 2
274 #define TXIM 3
275 
276 /* SSPSR bits definition */
277 #define TFE 0
278 #define TNF 1
279 #define RNE 2
280 #define RFF 3
281 #define BSY 4
282 
283 /* SSPMIS bits definition */
284 #define RORMIS 0
285 #define RTMIS 1
286 #define RXMIS 2
287 #define TXMIS 3
288 
289 /* SSPICR bits definition */
290 #define RORIC 0
291 #define RTIC 1
292 
293 
294 
295 
297 // Real Time Clock
298 #define RTC ((rtcRegs_t *)0xE0024000)
299 
300 // RTC Registers
301 #define RTCILR RTC->ilr /* Interrupt Location Register */
302 #define RTCCTC RTC->ctc /* Clock Tick Counter */
303 #define RTCCCR RTC->ccr /* Clock Control Register */
304 #define RTCCIIR RTC->ciir /* Counter Increment Interrupt Register */
305 #define RTCAMR RTC->amr /* Alarm Mask Register */
306 #define RTCCTIME0 RTC->ctime0 /* Consolidated Time Register 0 */
307 #define RTCCTIME1 RTC->ctime1 /* Consolidated Time Register 1 */
308 #define RTCCTIME2 RTC->ctime2 /* Consolidated Time Register 2 */
309 #define RTCSEC RTC->sec /* Seconds Register */
310 #define RTCMIN RTC->min /* Minutes Register */
311 #define RTCHOUR RTC->hour /* Hours Register */
312 #define RTCDOM RTC->dom /* Day Of Month Register */
313 #define RTCDOW RTC->dow /* Day Of Week Register */
314 #define RTCDOY RTC->doy /* Day Of Year Register */
315 #define RTCMONTH RTC->month /* Months Register */
316 #define RTCYEAR RTC->year /* Years Register */
317 #define RTCALSEC RTC->alsec /* Alarm Seconds Register */
318 #define RTCALMIN RTC->almin /* Alarm Minutes Register */
319 #define RTCALHOUR RTC->alhour /* Alarm Hours Register */
320 #define RTCALDOM RTC->aldom /* Alarm Day Of Month Register */
321 #define RTCALDOW RTC->aldow /* Alarm Day Of Week Register */
322 #define RTCALDOY RTC->aldoy /* Alarm Day Of Year Register */
323 #define RTCALMON RTC->almon /* Alarm Months Register */
324 #define RTCALYEAR RTC->alyear /* Alarm Years Register */
325 #define RTCPREINT RTC->preint /* Prescale Value Register (integer) */
326 #define RTCPREFRAC RTC->prefrac /* Prescale Value Register (fraction) */
327 
329 // General Purpose Input/Output
330 #define GPIO ((gpioRegs_t *)0xE0028000)
331 
332 // GPIO Registers
333 #define IO0PIN GPIO->in0 /* P0 Pin Value Register */
334 #define IO0SET GPIO->set0 /* P0 Pin Output Set Register */
335 #define IO0DIR GPIO->dir0 /* P0 Pin Direction Register */
336 #define IO0CLR GPIO->clr0 /* P0 Pin Output Clear Register */
337 #define IO1PIN GPIO->in1 /* P1 Pin Value Register */
338 #define IO1SET GPIO->set1 /* P1 Pin Output Set Register */
339 #define IO1DIR GPIO->dir1 /* P1 Pin Direction Register */
340 #define IO1CLR GPIO->clr1 /* P1 Pin Output Clear Register */
341 
343 // Pin Connect Block
344 #define PINSEL ((pinRegs_t *)0xE002C000)
345 
346 // Pin Connect Block Registers
347 #define PINSEL0 PINSEL->sel0 /* Pin Function Select Register 0 */
348 #define PINSEL1 PINSEL->sel1 /* Pin Function Select Register 1 */
349 #define PINSEL2 PINSEL->sel2 /* Pin Function Select Register 2 */
350 
352 // A/D Converter
353 #define ADC0 ((adcRegs_t *)0xE0034000)
354 
355 // A/D0 Converter Registers
356 #define AD0CR ADC0->cr /* Control Register */
357 #define AD0GDR ADC0->gdr /* Global Data Register */
358 #define ADGSR ADC0->gsr /* ADC global start resister */
359 #define AD0INTEN ADC0->inten /* Interrupt Enable Register */
360 #define AD0DR0 ADC0->dr0 /* Channel 0 Data Register */
361 #define AD0DR1 ADC0->dr1 /* Channel 1 Data Register */
362 #define AD0DR2 ADC0->dr2 /* Channel 2 Data Register */
363 #define AD0DR3 ADC0->dr3 /* Channel 3 Data Register */
364 #define AD0DR4 ADC0->dr4 /* Channel 4 Data Register */
365 #define AD0DR5 ADC0->dr5 /* Channel 5 Data Register */
366 #define AD0DR6 ADC0->dr6 /* Channel 6 Data Register */
367 #define AD0DR7 ADC0->dr7 /* Channel 7 Data Register */
368 #define AD0STAT ADC0->stat /* Status Register */
369 
370 #define ADC1 ((adcRegs_t *)0xE0060000)
371 
372 // A/D1 Converter Registers
373 #define AD1CR ADC1->cr /* Control Register */
374 #define AD1GDR ADC1->gdr /* Data Register */
375 #define AD1INTEN ADC1->inten /* Interrupt Enable Register */
376 #define AD1DR0 ADC1->dr0 /* Channel 0 Data Register */
377 #define AD1DR1 ADC1->dr1 /* Channel 1 Data Register */
378 #define AD1DR2 ADC1->dr2 /* Channel 2 Data Register */
379 #define AD1DR3 ADC1->dr3 /* Channel 3 Data Register */
380 #define AD1DR4 ADC1->dr4 /* Channel 4 Data Register */
381 #define AD1DR5 ADC1->dr5 /* Channel 5 Data Register */
382 #define AD1DR6 ADC1->dr6 /* Channel 6 Data Register */
383 #define AD1DR7 ADC1->dr7 /* Channel 7 Data Register */
384 #define AD1STAT ADC1->stat /* Status Register */
385 
386 
388 // Digital to Analog Converter
389 #define DACR (*(REG32*) 0xE006C000)
390 
391 
393 // System Contol Block
394 #define SCB ((scbRegs_t *)0xE01FC000)
395 
396 // Memory Accelerator Module Registers (MAM)
397 #define MAMCR SCB->mam.cr /* Control Register */
398 #define MAMTIM SCB->mam.tim /* Timing Control Register */
399 
400 // Memory Mapping Control Register
401 #define MEMMAP SCB->memmap
402 
403 // Phase Locked Loop Registers (PLL)
404 #define PLLCON SCB->pll.con /* Control Register */
405 #define PLLCFG SCB->pll.cfg /* Configuration Register */
406 #define PLLSTAT SCB->pll.stat /* Status Register */
407 #define PLLFEED SCB->pll.feed /* Feed Register */
408 
409 // Power Control Registers
410 #define PCON SCB->p.con /* Control Register */
411 #define PCONP SCB->p.conp /* Peripherals Register */
412 
413 // VPB Divider Register
414 #define VPBDIV SCB->vpbdiv
415 
416 // External Interrupt Registers
417 #define EXTINT SCB->ext.flag /* Flag Register */
418 #define EXTWAKE SCB->ext.wake /* Wakeup Register */
419 #define EXTMODE SCB->ext.mode /* Mode Register */
420 #define EXTPOLAR SCB->ext.polar /* Polarity Register */
421 
423 // Vectored Interrupt Controller
424 #define VIC ((vicRegs_t *)0xFFFFF000)
425 
426 // Vectored Interrupt Controller Registers
427 #define VICIRQStatus VIC->irqStatus /* IRQ Status Register */
428 #define VICFIQStatus VIC->fiqStatus /* FIQ Status Register */
429 #define VICRawIntr VIC->rawIntr /* Raw Interrupt Status Register */
430 #define VICIntSelect VIC->intSelect /* Interrupt Select Register */
431 #define VICIntEnable VIC->intEnable /* Interrupt Enable Register */
432 #define VICIntEnClear VIC->intEnClear /* Interrupt Enable Clear Register */
433 #define VICSoftInt VIC->softInt /* Software Interrupt Register */
434 #define VICSoftIntClear VIC->softIntClear /* Software Interrupt Clear Register */
435 #define VICProtection VIC->protection /* Protection Enable Register */
436 #define VICVectAddr VIC->vectAddr /* Vector Address Register */
437 #define VICDefVectAddr VIC->defVectAddr /* Default Vector Address Register */
438 #define VICVectAddr0 VIC->vectAddr0 /* Vector Address 0 Register */
439 #define VICVectAddr1 VIC->vectAddr1 /* Vector Address 1 Register */
440 #define VICVectAddr2 VIC->vectAddr2 /* Vector Address 2 Register */
441 #define VICVectAddr3 VIC->vectAddr3 /* Vector Address 3 Register */
442 #define VICVectAddr4 VIC->vectAddr4 /* Vector Address 4 Register */
443 #define VICVectAddr5 VIC->vectAddr5 /* Vector Address 5 Register */
444 #define VICVectAddr6 VIC->vectAddr6 /* Vector Address 6 Register */
445 #define VICVectAddr7 VIC->vectAddr7 /* Vector Address 7 Register */
446 #define VICVectAddr8 VIC->vectAddr8 /* Vector Address 8 Register */
447 #define VICVectAddr9 VIC->vectAddr9 /* Vector Address 9 Register */
448 #define VICVectAddr10 VIC->vectAddr10 /* Vector Address 10 Register */
449 #define VICVectAddr11 VIC->vectAddr11 /* Vector Address 11 Register */
450 #define VICVectAddr12 VIC->vectAddr12 /* Vector Address 12 Register */
451 #define VICVectAddr13 VIC->vectAddr13 /* Vector Address 13 Register */
452 #define VICVectAddr14 VIC->vectAddr14 /* Vector Address 14 Register */
453 #define VICVectAddr15 VIC->vectAddr15 /* Vector Address 15 Register */
454 #define VICVectCntl0 VIC->vectCntl0 /* Vector Control 0 Register */
455 #define VICVectCntl1 VIC->vectCntl1 /* Vector Control 1 Register */
456 #define VICVectCntl2 VIC->vectCntl2 /* Vector Control 2 Register */
457 #define VICVectCntl3 VIC->vectCntl3 /* Vector Control 3 Register */
458 #define VICVectCntl4 VIC->vectCntl4 /* Vector Control 4 Register */
459 #define VICVectCntl5 VIC->vectCntl5 /* Vector Control 5 Register */
460 #define VICVectCntl6 VIC->vectCntl6 /* Vector Control 6 Register */
461 #define VICVectCntl7 VIC->vectCntl7 /* Vector Control 7 Register */
462 #define VICVectCntl8 VIC->vectCntl8 /* Vector Control 8 Register */
463 #define VICVectCntl9 VIC->vectCntl9 /* Vector Control 9 Register */
464 #define VICVectCntl10 VIC->vectCntl10 /* Vector Control 10 Register */
465 #define VICVectCntl11 VIC->vectCntl11 /* Vector Control 11 Register */
466 #define VICVectCntl12 VIC->vectCntl12 /* Vector Control 12 Register */
467 #define VICVectCntl13 VIC->vectCntl13 /* Vector Control 13 Register */
468 #define VICVectCntl14 VIC->vectCntl14 /* Vector Control 14 Register */
469 #define VICVectCntl15 VIC->vectCntl15 /* Vector Control 15 Register */
470 
471 
473 // CAN controllers
474 
475 
476 #define CAN_CENTRAL ((can_central_Regs_t *)0xE0040000)
477 #define CANTxSR CAN_CENTRAL->tx_sr /* CAN Central Transmit Status Register */
478 #define CANRxSR CAN_CENTRAL->rx_sr /* CAN Central Receive Status Register */
479 #define CANMSR CAN_CENTRAL->m_sr /* CAN Central Miscellanous Register */
480 
481 #define CAN_ACCEPT ((can_accept_Regs_t *)0xE003C000)
482 #define AFMR CAN_ACCEPT->afmr /* Acceptance Filter Register */
483 
484 #define CAN1 ((can_Regs_t *)0xE0044000)
485 #define C1MOD CAN1->can_mod /* */
486 #define C1CMR CAN1->can_cmr /* */
487 #define C1GSR CAN1->can_gsr /* */
488 #define C1ICR CAN1->can_icr
489 #define C1IER CAN1->can_ier
490 #define C1BTR CAN1->can_btr
491 #define C1EWL CAN1->can_ewl
492 #define C1SR CAN1->can_sr
493 #define C1RFS CAN1->can_rfs
494 #define C1RID CAN1->can_rid
495 #define C1RDA CAN1->can_rda
496 #define C1RDB CAN1->can_rdb
497 #define C1TFI1 CAN1->can_tfi1
498 #define C1TID1 CAN1->can_tid1
499 #define C1TDA1 CAN1->can_tda1
500 #define C1TDB1 CAN1->can_tdb1
501 #define C1TFI2 CAN1->can_tfi2
502 #define C1TID2 CAN1->can_tid2
503 #define C1TDA2 CAN1->can_tda2
504 #define C1TDB2 CAN1->can_tdb2
505 #define C1TFI3 CAN1->can_tfi3
506 #define C1TID3 CAN1->can_tid3
507 #define C1TDA3 CAN1->can_tda3
508 #define C1TDB3 CAN1->can_tdb3
509 
510 #define CAN2 ((can_Regs_t *)0xE0048000)
511 #define C2MOD CAN2->can_mod /* */
512 #define C2CMR CAN2->can_cmr /* */
513 #define C2GSR CAN2->can_gsr /* */
514 #define C2ICR CAN2->can_icr
515 #define C2IER CAN2->can_ier
516 #define C2BTR CAN2->can_btr
517 #define C2EWL CAN2->can_ewl
518 #define C2SR CAN2->can_sr
519 #define C2RFS CAN2->can_rfs
520 #define C2RID CAN2->can_rid
521 #define C2RDA CAN2->can_rda
522 #define C2RDB CAN2->can_rdb
523 #define C2TFI1 CAN2->can_tfi1
524 #define C2TID1 CAN2->can_tid1
525 #define C2TDA1 CAN2->can_tda1
526 #define C2TDB1 CAN2->can_tdb1
527 #define C2TFI2 CAN2->can_tfi2
528 #define C2TID2 CAN2->can_tid2
529 #define C2TDA2 CAN2->can_tda2
530 #define C2TDB2 CAN2->can_tdb2
531 #define C2TFI3 CAN2->can_tfi3
532 #define C2TID3 CAN2->can_tid3
533 #define C2TDA3 CAN2->can_tda3
534 #define C2TDB3 CAN2->can_tdb3
535 
536 
537 
538 #endif
lpcUART.h
lpcPIN.h
lpcTMR.h
lpcGPIO.h
lpcWD.h
lpcVIC.h
lpcI2C.h
lpcADC.h
lpcSCB.h
lpcCAN.h
lpcRTC.h
lpcSPI.h