Paparazzi UAS  v7.0_unstable
Paparazzi is a free software Unmanned Aircraft System.
input_capture_arch.c
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1 #include "mcu_periph/input_capture_arch.h"
2 
3 
4 enum TimICChannel {TIMIC_CH1=1<<0, TIMIC_CH2=1<<1, TIMIC_CH3=1<<2, TIMIC_CH4=1<<3};
5 
6 static const TimICDriver* driverByTimerIndex[6] = {NULL};
7 
8 
9 static void input_capture_lld_serve_interrupt(const TimICDriver * const timicp) __attribute__((unused));
10 static void _input_capture_isr_invoke_capture_cb(const TimICDriver * const timicp, uint32_t channel);
11 static void _input_capture_isr_invoke_overflow_cb(const TimICDriver * const timicp);
12 
13 void timIcObjectInit(TimICDriver *timicp)
14 {
15  timicp->config = NULL;
16  timicp->state = TIMIC_STOP;
17  timicp->dier = 0;
18 }
19 
20 void timIcStart(TimICDriver *timicp, const TimICConfig *configp)
21 {
22  osalDbgCheck((configp != NULL) && (timicp != NULL));
23  osalDbgAssert((configp->prescaler >= 1) &&
24  (configp->prescaler <= 65536),
25  "prescaler must be 1 .. 65536");
26  osalDbgAssert(timicp->state == TIMIC_STOP, "state error");
27  timicp->config = configp;
28  stm32_tim_t * const timer = timicp->config->timer;
29  chMtxObjectInit(&timicp->mut);
30  timIcRccEnable(timicp);
31  timicp->channel = 0;
32  if (timicp->config->active & (CH1_RISING_EDGE | CH1_FALLING_EDGE | CH1_BOTH_EDGES))
33  timicp->channel |= TIMIC_CH1;
34  if (timicp->config->active & (CH2_RISING_EDGE | CH2_FALLING_EDGE | CH2_BOTH_EDGES))
35  timicp->channel |= TIMIC_CH2;
36  if (timicp->config->active & (CH3_RISING_EDGE | CH3_FALLING_EDGE | CH3_BOTH_EDGES))
37  timicp->channel |= TIMIC_CH3;
38  if (timicp->config->active & (CH4_RISING_EDGE | CH4_FALLING_EDGE | CH4_BOTH_EDGES))
39  timicp->channel |= TIMIC_CH4;
40 
41  timer->CR1 = 0; // disable timer
42 
43  // hack in case of timer with more fields
44 #if defined (STM32G0XX) || defined (STM32G4XX)|| defined (STM32H7XX)
45 
46  TIM_TypeDef *cmsisTimer = (TIM_TypeDef *) timer;
47  cmsisTimer->CCMR3 = cmsisTimer->AF1 = cmsisTimer->AF2 =
48  cmsisTimer->TISEL = 0;
49 #endif
50 
51  timer->PSC = configp->prescaler - 1U; // prescaler
52  timer->ARR = configp->arr ? configp->arr : 0xffffffff;
53  timer->DCR = configp->dcr;
54  if (timicp->config->mode == TIMIC_PWM_IN) {
55  chDbgAssert(__builtin_popcount(timicp->channel) == 1, "In pwm mode, only one channel must be set");
56  chDbgAssert((timicp->config->capture_cb == NULL) && (timicp->config->overflow_cb == NULL),
57  "In pwm mode, callback are not implemented, use PWMDriver instead");
58  switch (timicp->channel) {
59  case TIMIC_CH1:
60  timer->CCMR1 = (0b01 << TIM_CCMR1_CC1S_Pos) | (0b10 << TIM_CCMR1_CC2S_Pos);
61  timer->CCMR2 = 0U;
62  timer->CCER = TIM_CCER_CC2P; /* CC1P et CC1NP = 0 */
63  timer->SMCR = (0b101 << TIM_SMCR_TS_Pos) | (0b100 << TIM_SMCR_SMS_Pos);
64  timer->CCER |= (TIM_CCER_CC1E | TIM_CCER_CC2E);
65  break;
66  case TIMIC_CH2:
67  timer->CCMR1 = (0b10 << TIM_CCMR1_CC1S_Pos) | (0b01 << TIM_CCMR1_CC2S_Pos);
68  timer->CCMR2 = 0U;
69  timer->CCER = TIM_CCER_CC1P; /* CC2P et CC2NP = 0 */
70  timer->SMCR = (0b110 << TIM_SMCR_TS_Pos) | (0b100 << TIM_SMCR_SMS_Pos);
71  timer->CCER |= (TIM_CCER_CC1E | TIM_CCER_CC2E);
72  break;
73  case TIMIC_CH3:
74  timer->CCMR2 = (0b01 << TIM_CCMR2_CC3S_Pos) | (0b10 << TIM_CCMR2_CC4S_Pos);
75  timer->CCMR1 = 0U;
76  timer->CCER = TIM_CCER_CC4P; /* CC3P et CC3NP = 0 */
77  timer->SMCR = (0b101 << TIM_SMCR_TS_Pos) | (0b100 << TIM_SMCR_SMS_Pos);
78  timer->CCER |= (TIM_CCER_CC3E | TIM_CCER_CC4E);
79  break;
80  case TIMIC_CH4:
81  timer->CCMR2 = (0b10 << TIM_CCMR2_CC3S_Pos) | (0b01 << TIM_CCMR2_CC4S_Pos);
82  timer->CCMR1 = 0U;
83  timer->CCER = TIM_CCER_CC3P; /* CC4P et CC4NP = 0 */
84  timer->SMCR = (0b110 << TIM_SMCR_TS_Pos) | (0b100 << TIM_SMCR_SMS_Pos);
85  timer->CCER |= (TIM_CCER_CC3E | TIM_CCER_CC4E);
86  break;
87  default:
88  chSysHalt("channel must be TIMIC_CH1 .. TIMIC_CH4");
89  }
90  } else if (timicp->config->mode == TIMIC_INPUT_CAPTURE) {
91  /*
92  Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S
93  bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00,
94  the channel is configured in input and the TIMx_CCR1 register becomes read-only.
95  •
96  Select the edge of the active transition on the TI1 channel by writing CC1P and CC1NP
97  bits to 0 in the TIMx_CCER register (rising edge in this case).
98  •
99  •
100  Enable capture from the counter into the capture register by setting the CC1E bit in the
101  TIMx_CCER register.
102  •
103  If needed, enable the related interrupt request by setting the CC1IE bit in the
104  TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the
105  TIMx_DIER register.
106  */
107 
108 
109  timer->CCMR1 = 0;
110  timer->CCMR2 = 0;
111  timer->CCER = 0;
112  timer->SMCR = 0;
113  timer->CCER = 0;
114 
115  if (timicp->channel & TIMIC_CH1) {
116  switch (timicp->config->active & (CH1_RISING_EDGE | CH1_FALLING_EDGE | CH1_BOTH_EDGES)) {
117  case CH1_RISING_EDGE:
118  timer->CCER |= 0;
119  break;
120  case CH1_FALLING_EDGE:
121  timer->CCER |= TIM_CCER_CC1P;
122  break;
123  case CH1_BOTH_EDGES:
124  timer->CCER |= (TIM_CCER_CC1P | TIM_CCER_CC1NP);
125  break;
126  default:
127  chSysHalt("No configuration given for CH1");
128  }
129  timer->CCMR1 |= (0b01 << TIM_CCMR1_CC1S_Pos);
130  timer->CCER |= TIM_CCER_CC1E;
131  timicp->dier |= STM32_TIM_DIER_CC1IE;
132  }
133  if (timicp->channel & TIMIC_CH2) {
134  switch (timicp->config->active & (CH2_RISING_EDGE | CH2_FALLING_EDGE | CH2_BOTH_EDGES)) {
135  case CH2_RISING_EDGE:
136  timer->CCER |= 0;
137  break;
138  case CH2_FALLING_EDGE:
139  timer->CCER |= TIM_CCER_CC2P;
140  break;
141  case CH2_BOTH_EDGES:
142  timer->CCER |= (TIM_CCER_CC2P | TIM_CCER_CC2NP);
143  break;
144  default:
145  chSysHalt("No configuration given for CH2");
146  }
147  timer->CCMR1 |= (0b01 << TIM_CCMR1_CC2S_Pos);
148  timer->CCER |= TIM_CCER_CC2E;
149  timicp->dier |= STM32_TIM_DIER_CC2IE;
150  }
151  if (timicp->channel & TIMIC_CH3) {
152  switch (timicp->config->active & (CH3_RISING_EDGE | CH3_FALLING_EDGE | CH3_BOTH_EDGES)) {
153  case CH3_RISING_EDGE:
154  timer->CCER |= 0;
155  break;
156  case CH3_FALLING_EDGE:
157  timer->CCER |= TIM_CCER_CC3P;
158  break;
159  case CH3_BOTH_EDGES:
160  timer->CCER |= (TIM_CCER_CC3P | TIM_CCER_CC3NP);
161  break;
162  default:
163  chSysHalt("No configuration given for CH3");
164  }
165  timer->CCMR2 |= (0b01 << TIM_CCMR2_CC3S_Pos);
166  timer->CCER |= TIM_CCER_CC3E;
167  timicp->dier |= STM32_TIM_DIER_CC3IE;
168  }
169  if (timicp->channel & TIMIC_CH4) {
170  switch (timicp->config->active & (CH4_RISING_EDGE | CH4_FALLING_EDGE | CH4_BOTH_EDGES)) {
171  case CH4_RISING_EDGE:
172  timer->CCER |= 0;
173  break;
174  case CH4_FALLING_EDGE:
175  timer->CCER |= TIM_CCER_CC4P;
176  break;
177  case CH4_BOTH_EDGES:
178  timer->CCER |= (TIM_CCER_CC4P | TIM_CCER_CC4NP);
179  break;
180  default:
181  chSysHalt("No configuration given for CH4");
182  }
183  timer->CCMR2 |= (0b01 << TIM_CCMR2_CC4S_Pos);
184  timer->CCER |= TIM_CCER_CC4E;
185  timicp->dier |= STM32_TIM_DIER_CC4IE;
186  }
187  } else {
188  chSysHalt("invalid mode");
189  }
190  // keep only DMA bits, not ISR bits that are handle by driver
191  if (timicp->config->capture_cb == NULL)
192  timicp->dier = 0;
193  if (timicp->config->overflow_cb)
194  timicp->dier |= STM32_TIM_DIER_UIE;
195 
196  timicp->dier = timicp->dier | (timicp->config->dier & (~ STM32_TIM_DIER_IRQ_MASK));
197  timicp->state = TIMIC_READY;
198 }
199 
200 void timIcStartCapture(TimICDriver *timicp)
201 {
202  osalDbgCheck(timicp != NULL);
203  osalDbgAssert(timicp->state == TIMIC_READY, "state error");
204  stm32_tim_t * const timer = timicp->config->timer;
205  osalDbgCheck(timer != NULL);
206  timer->CR1 = STM32_TIM_CR1_URS;
207  timer->EGR |= STM32_TIM_EGR_UG;
208  timer->SR = 0;
209  timer->DIER = timicp->dier;
210  timer->CR1 = STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN;
211  timicp->state = TIMIC_ACTIVE;
212 }
213 
214 void timIcStopCapture(TimICDriver *timicp)
215 {
216  osalDbgCheck(timicp != NULL);
217  osalDbgAssert(timicp->state != TIMIC_STOP, "state error");
218  stm32_tim_t * const timer = timicp->config->timer;
219  osalDbgCheck(timer != NULL);
220  timer->CR1 &= ~TIM_CR1_CEN;
221  timer->DIER = 0;
222  timicp->state = TIMIC_READY;
223 }
224 
225 void timIcStop(TimICDriver *timicp)
226 {
227  osalDbgAssert(timicp->state != TIMIC_STOP, "state error");
228  chMtxLock(&timicp->mut);
229  timIcRccDisable(timicp);
230  timIcObjectInit(timicp);
231  chMtxUnlock(&timicp->mut);
232  timicp->state = TIMIC_STOP;
233  timicp->dier = 0;
234 }
235 
236 
237 
238 
239 void timIcRccEnable(const TimICDriver * const timicp)
240 {
241  const stm32_tim_t * const timer = timicp->config->timer;
242  const bool use_isr = timicp->config->capture_cb || timicp->config->overflow_cb;
243 #ifdef TIM1
244  if (timer == STM32_TIM1) {
245  driverByTimerIndex[0] = timicp;
246  rccEnableTIM1(true);
247  rccResetTIM1();
248  if (use_isr) {
249 #ifdef STM32_TIM1_UP_TIM10_NUMBER
250  nvicEnableVector(STM32_TIM1_UP_TIM10_NUMBER, STM32_IRQ_TIM1_UP_TIM10_PRIORITY);
251 #endif
252 #ifdef STM32_TIM1_CC_NUMBER
253  nvicEnableVector(STM32_TIM1_CC_NUMBER, STM32_IRQ_TIM1_CC_PRIORITY);
254 #endif
255  }
256  }
257 #endif
258 #ifdef TIM2
259  else if (timer == STM32_TIM2) {
260  driverByTimerIndex[1] = timicp;
261  rccEnableTIM2(true);
262  rccResetTIM2();
263  if (use_isr) {
264  nvicEnableVector(STM32_TIM2_NUMBER, STM32_IRQ_TIM2_PRIORITY);
265  }
266  }
267 #endif
268 #ifdef TIM3
269  else if (timer == STM32_TIM3) {
270  driverByTimerIndex[2] = timicp;
271  rccEnableTIM3(true);
272  rccResetTIM3();
273  if (use_isr) {
274  nvicEnableVector(STM32_TIM3_NUMBER, STM32_IRQ_TIM3_PRIORITY);
275  }
276  }
277 #endif
278 #ifdef TIM4
279  else if (timer == STM32_TIM4) {
280  driverByTimerIndex[3] = timicp;
281  rccEnableTIM4(true);
282  rccResetTIM4();
283  if (use_isr) {
284  nvicEnableVector(STM32_TIM4_NUMBER, STM32_IRQ_TIM4_PRIORITY);
285  }
286  }
287 #endif
288 #ifdef TIM5
289  else if (timer == STM32_TIM5) {
290  driverByTimerIndex[4] = timicp;
291  rccEnableTIM5(true);
292  rccResetTIM5();
293  if (use_isr) {
294  nvicEnableVector(STM32_TIM5_NUMBER, STM32_IRQ_TIM5_PRIORITY);
295  }
296  }
297 #endif
298 #ifdef TIM8
299  else if (timer == STM32_TIM8) {
300  driverByTimerIndex[5] = timicp;
301  rccEnableTIM8(true);
302  rccResetTIM8();
303  if (use_isr) {
304 #ifdef STM32_TIM8_UP_TIM13_NUMBER
305  nvicEnableVector(STM32_TIM8_UP_TIM13_NUMBER, STM32_IRQ_TIM8_UP_TIM13_PRIORITY);
306 #endif
307 #ifdef STM32_TIM8_CC_NUMBER
308  nvicEnableVector(STM32_TIM8_CC_NUMBER, STM32_IRQ_TIM8_CC_PRIORITY);
309 #endif
310  }
311  }
312 #endif
313 #ifdef TIM9
314  else if (timer == STM32_TIM9) {
315  rccEnableTIM9(true);
316  rccResetTIM9();
317  }
318 #endif
319 #ifdef TIM10
320  else if (timer == STM32_TIM10) {
321  rccEnableTIM10(true);
322  rccResetTIM10();
323  }
324 #endif
325 #ifdef TIM11
326  else if (timer == STM32_TIM11) {
327  rccEnableTIM11(true);
328  rccResetTIM11();
329  }
330 #endif
331 #ifdef TIM12
332  else if (timer == STM32_TIM12) {
333  rccEnableTIM12(true);
334  rccResetTIM12();
335  }
336 #endif
337 #ifdef TIM13
338  else if (timer == STM32_TIM13) {
339  rccEnableTIM13(true);
340  rccResetTIM13();
341  }
342 #endif
343 #ifdef TIM14
344  else if (timer == STM32_TIM14) {
345  rccEnableTIM14(true);
346  rccResetTIM14();
347  }
348 #endif
349 #ifdef TIM15
350  else if (timer == STM32_TIM15) {
351  rccEnableTIM15(true);
352  rccResetTIM15();
353  }
354 #endif
355 #ifdef TIM16
356  else if (timer == STM32_TIM16) {
357  rccEnableTIM16(true);
358  rccResetTIM16();
359  }
360 #endif
361 #ifdef TIM17
362  else if (timer == STM32_TIM17) {
363  rccEnableTIM17(true);
364  rccResetTIM17();
365  }
366 #endif
367 #ifdef TIM18
368  else if (timer == STM32_TIM18) {
369  rccEnableTIM18(true);
370  rccResetTIM18();
371  }
372 #endif
373 #ifdef TIM19
374  else if (timer == STM32_TIM19) {
375  rccEnableTIM19(true);
376  rccResetTIM19();
377  }
378 #endif
379  else {
380  chSysHalt("not a valid timer");
381  }
382 };
383 
384 void timIcRccDisable(const TimICDriver * const timicp)
385 {
386  const stm32_tim_t * const timer = timicp->config->timer;
387 #ifdef TIM1
388  if (timer == STM32_TIM1) {
389  rccResetTIM1();
390  rccDisableTIM1();
391  }
392 #endif
393 #ifdef TIM2
394  else if (timer == STM32_TIM2) {
395  rccResetTIM2();
396  rccDisableTIM2();
397  }
398 #endif
399 #ifdef TIM3
400  else if (timer == STM32_TIM3) {
401  rccResetTIM3();
402  rccDisableTIM3();
403  }
404 #endif
405 #ifdef TIM4
406  else if (timer == STM32_TIM4) {
407  rccResetTIM4();
408  rccDisableTIM4();
409  }
410 #endif
411 #ifdef TIM5
412  else if (timer == STM32_TIM5) {
413  rccResetTIM5();
414  rccDisableTIM5();
415  }
416 #endif
417 #ifdef TIM8
418  else if (timer == STM32_TIM8) {
419  rccResetTIM8();
420  rccDisableTIM8();
421  }
422 #endif
423 #ifdef TIM9
424  else if (timer == STM32_TIM9) {
425  rccResetTIM9();
426  rccDisableTIM9();
427  }
428 #endif
429 #ifdef TIM10
430  else if (timer == STM32_TIM10) {
431  rccResetTIM10();
432  rccDisableTIM10();
433  }
434 #endif
435 #ifdef TIM11
436  else if (timer == STM32_TIM11) {
437  rccResetTIM11();
438  rccDisableTIM11();
439  }
440 #endif
441 #ifdef TIM12
442  else if (timer == STM32_TIM12) {
443  rccResetTIM12();
444  rccDisableTIM12();
445  }
446 #endif
447 #ifdef TIM13
448  else if (timer == STM32_TIM13) {
449  rccResetTIM13();
450  rccDisableTIM13();
451  }
452 #endif
453 #ifdef TIM14
454  else if (timer == STM32_TIM14) {
455  rccResetTIM14();
456  rccDisableTIM14();
457  }
458 #endif
459 #ifdef TIM15
460  else if (timer == STM32_TIM15) {
461  rccResetTIM15();
462  rccDisableTIM15();
463  }
464 #endif
465 #ifdef TIM16
466  else if (timer == STM32_TIM16) {
467  rccResetTIM16();
468  rccDisableTIM16();
469  }
470 #endif
471 #ifdef TIM17
472  else if (timer == STM32_TIM17) {
473  rccResetTIM17();
474  rccDisableTIM17();
475  }
476 #endif
477 #ifdef TIM18
478  else if (timer == STM32_TIM18) {
479  rccResetTIM18();
480  rccDisableTIM18();
481  }
482 #endif
483 #ifdef TIM19
484  else if (timer == STM32_TIM19) {
485  rccResetTIM19();
486  rccDisableTIM19();
487  }
488 #endif
489  else {
490  chSysHalt("not a valid timer");
491  }
492 };
493 
494 
495 /*===========================================================================*/
496 /* Driver interrupt handlers. */
497 /*===========================================================================*/
498 #ifndef STM32_INPUT_CAPTURE_USE_TIM1
499 #define STM32_INPUT_CAPTURE_USE_TIM1 false
500 #endif
501 
502 #ifndef STM32_INPUT_CAPTURE_USE_TIM2
503 #define STM32_INPUT_CAPTURE_USE_TIM2 false
504 #endif
505 
506 #ifndef STM32_INPUT_CAPTURE_USE_TIM3
507 #define STM32_INPUT_CAPTURE_USE_TIM3 false
508 #endif
509 
510 #ifndef STM32_INPUT_CAPTURE_USE_TIM4
511 #define STM32_INPUT_CAPTURE_USE_TIM4 false
512 #endif
513 
514 #ifndef STM32_INPUT_CAPTURE_USE_TIM5
515 #define STM32_INPUT_CAPTURE_USE_TIM5 false
516 #endif
517 
518 #ifndef STM32_INPUT_CAPTURE_USE_TIM8
519 #define STM32_INPUT_CAPTURE_USE_TIM8 false
520 #endif
521 
522 #ifndef STM32_INPUT_CAPTURE_SHARE_TIM1
523 #define STM32_INPUT_CAPTURE_SHARE_TIM1 false
524 #endif
525 
526 #ifndef STM32_INPUT_CAPTURE_SHARE_TIM2
527 #define STM32_INPUT_CAPTURE_SHARE_TIM2 false
528 #endif
529 
530 #ifndef STM32_INPUT_CAPTURE_SHARE_TIM3
531 #define STM32_INPUT_CAPTURE_SHARE_TIM3 false
532 #endif
533 
534 #ifndef STM32_INPUT_CAPTURE_SHARE_TIM4
535 #define STM32_INPUT_CAPTURE_SHARE_TIM4 false
536 #endif
537 
538 #ifndef STM32_INPUT_CAPTURE_SHARE_TIM5
539 #define STM32_INPUT_CAPTURE_SHARE_TIM5 false
540 #endif
541 
542 #ifndef STM32_INPUT_CAPTURE_SHARE_TIM8
543 #define STM32_INPUT_CAPTURE_SHARE_TIM8 false
544 #endif
545 
546 #ifndef STM32_INPUT_CAPTURE_ENABLE_TIM1_ISR
547 #define STM32_INPUT_CAPTURE_ENABLE_TIM1_ISR false
548 #endif
549 
550 #ifndef STM32_INPUT_CAPTURE_ENABLE_TIM2_ISR
551 #define STM32_INPUT_CAPTURE_ENABLE_TIM2_ISR false
552 #endif
553 
554 
555 #ifndef STM32_INPUT_CAPTURE_ENABLE_TIM3_ISR
556 #define STM32_INPUT_CAPTURE_ENABLE_TIM3_ISR false
557 #endif
558 
559 
560 #ifndef STM32_INPUT_CAPTURE_ENABLE_TIM4_ISR
561 #define STM32_INPUT_CAPTURE_ENABLE_TIM4_ISR false
562 #endif
563 
564 
565 #ifndef STM32_INPUT_CAPTURE_ENABLE_TIM5_ISR
566 #define STM32_INPUT_CAPTURE_ENABLE_TIM5_ISR false
567 #endif
568 
569 
570 #ifndef STM32_INPUT_CAPTURE_ENABLE_TIM8_ISR
571 #define STM32_INPUT_CAPTURE_ENABLE_TIM8_ISR false
572 #endif
573 
574 
575 
576 #if STM32_INPUT_CAPTURE_USE_TIM1 && (!STM32_INPUT_CAPTURE_SHARE_TIM1) && \
577 (STM32_GPT_USE_TIM1 || STM32_ICU_USE_TIM1 || STM32_PWM_USE_TIM1)
578 #error "STM32 INPUT_CAPTURE USE TIM1 but already used by GPT or ICU or PWM"
579 #endif
580 
581 #if STM32_INPUT_CAPTURE_USE_TIM2 && (!STM32_INPUT_CAPTURE_SHARE_TIM2) && \
582 (STM32_GPT_USE_TIM2 || STM32_ICU_USE_TIM2 || STM32_PWM_USE_TIM2)
583 #error "STM32 INPUT_CAPTURE USE TIM2 but already used by GPT or ICU or PWM"
584 #endif
585 
586 #if STM32_INPUT_CAPTURE_USE_TIM3 && (!STM32_INPUT_CAPTURE_SHARE_TIM3) && \
587 (STM32_GPT_USE_TIM3 || STM32_ICU_USE_TIM3 || STM32_PWM_USE_TIM3)
588 #error "STM32 INPUT_CAPTURE USE TIM3 but already used by GPT or ICU or PWM"
589 #endif
590 
591 #if STM32_INPUT_CAPTURE_USE_TIM4 && (!STM32_INPUT_CAPTURE_SHARE_TIM4) && \
592 (STM32_GPT_USE_TIM4 || STM32_ICU_USE_TIM4 || STM32_PWM_USE_TIM4)
593 #error "STM32 INPUT_CAPTURE USE TIM4 but already used by GPT or ICU or PWM"
594 #endif
595 
596 #if STM32_INPUT_CAPTURE_USE_TIM5 && (!STM32_INPUT_CAPTURE_SHARE_TIM5) && \
597 (STM32_GPT_USE_TIM5 || STM32_ICU_USE_TIM5 || STM32_PWM_USE_TIM5)
598 #error "STM32 INPUT_CAPTURE USE TIM5 but already used by GPT or ICU or PWM"
599 #endif
600 
601 #if STM32_INPUT_CAPTURE_USE_TIM8 && (!STM32_INPUT_CAPTURE_SHARE_TIM8) && \
602 (STM32_GPT_USE_TIM8 || STM32_ICU_USE_TIM8 || STM32_PWM_USE_TIM8)
603 #error "STM32 INPUT_CAPTURE USE TIM8 but already used by GPT or ICU or PWM"
604 #endif
605 
606 
607 #if STM32_INPUT_CAPTURE_USE_TIM1 || defined(__DOXYGEN__)
608 #if STM32_INPUT_CAPTURE_ENABLE_TIM1_ISR
609 #if defined(STM32_TIM1_UP_TIM10_HANDLER)
615 OSAL_IRQ_HANDLER(STM32_TIM1_UP_TIM10_HANDLER) {
616 
617  OSAL_IRQ_PROLOGUE();
618 
619  input_capture_lld_serve_interrupt(driverByTimerIndex[0]);
620 
621  OSAL_IRQ_EPILOGUE();
622 }
623 #elif defined(STM32_TIM1_UP_HANDLER)
624 OSAL_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
625 
626  OSAL_IRQ_PROLOGUE();
627 
628  input_capture_lld_serve_interrupt(driverByTimerIndex[0]);
629 
630  OSAL_IRQ_EPILOGUE();
631 }
632 #else
633 #error "no handler defined for TIM1"
634 #endif
635 
636 #if !defined(STM32_TIM1_CC_HANDLER)
637 #error "STM32_TIM1_CC_HANDLER not defined"
638 #endif
644 OSAL_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) {
645 
646  OSAL_IRQ_PROLOGUE();
647 
648  input_capture_lld_serve_interrupt(driverByTimerIndex[0]);
649 
650  OSAL_IRQ_EPILOGUE();
651 }
652 #endif /* STM32_INPUT_CAPTURE_ENABLE_TIM1_ISR */
653 #endif /* STM32_INPUT_CAPTURE_USE_TIM1 */
654 
655 #if STM32_INPUT_CAPTURE_USE_TIM2 || defined(__DOXYGEN__)
656 #if STM32_INPUT_CAPTURE_ENABLE_TIM2_ISR
657 #if !defined(STM32_TIM2_HANDLER)
658 #error "STM32_TIM2_HANDLER not defined"
659 #endif
665 OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) {
666 
667  OSAL_IRQ_PROLOGUE();
668 
669  input_capture_lld_serve_interrupt(driverByTimerIndex[1]);
670 
671  OSAL_IRQ_EPILOGUE();
672 }
673 #endif /* STM32_INPUT_CAPTURE_ENABLE_TIM2_ISR */
674 #endif /* STM32_INPUT_CAPTURE_USE_TIM2 */
675 
676 #if STM32_INPUT_CAPTURE_USE_TIM3 || defined(__DOXYGEN__)
677 #if STM32_INPUT_CAPTURE_ENABLE_TIM3_ISR
678 #if !defined(STM32_TIM3_HANDLER)
679 #error "STM32_TIM3_HANDLER not defined"
680 #endif
686 OSAL_IRQ_HANDLER(STM32_TIM3_HANDLER) {
687 
688  OSAL_IRQ_PROLOGUE();
689 
690  input_capture_lld_serve_interrupt(driverByTimerIndex[2]);
691 
692  OSAL_IRQ_EPILOGUE();
693 }
694 #endif /* STM32_INPUT_CAPTURE_ENABLE_TIM3_ISR */
695 #endif /* STM32_INPUT_CAPTURE_USE_TIM3 */
696 
697 #if STM32_INPUT_CAPTURE_USE_TIM4 || defined(__DOXYGEN__)
698 #if STM32_INPUT_CAPTURE_ENABLE_TIM4_ISR
699 #if !defined(STM32_TIM4_HANDLER)
700 #error "STM32_TIM4_HANDLER not defined"
701 #endif
707 OSAL_IRQ_HANDLER(STM32_TIM4_HANDLER) {
708 
709  OSAL_IRQ_PROLOGUE();
710 
711  input_capture_lld_serve_interrupt(driverByTimerIndex[3]);
712 
713  OSAL_IRQ_EPILOGUE();
714 }
715 #endif /* STM32_INPUT_CAPTURE_ENABLE_TIM4_ISR */
716 #endif /* STM32_INPUT_CAPTURE_USE_TIM4 */
717 
718 #if STM32_INPUT_CAPTURE_USE_TIM5 || defined(__DOXYGEN__)
719 #if STM32_INPUT_CAPTURE_ENABLE_TIM5_ISR
720 #if !defined(STM32_TIM5_HANDLER)
721 #error "STM32_TIM5_HANDLER not defined"
722 #endif
728 OSAL_IRQ_HANDLER(STM32_TIM5_HANDLER) {
729 
730  OSAL_IRQ_PROLOGUE();
731 
732  input_capture_lld_serve_interrupt(driverByTimerIndex[4]);
733 
734  OSAL_IRQ_EPILOGUE();
735 }
736 #endif /* STM32_INPUT_CAPTURE_ENABLE_TIM5_ISR */
737 #endif /* STM32_INPUT_CAPTURE_USE_TIM5 */
738 
739 #if STM32_INPUT_CAPTURE_USE_TIM8 || defined(__DOXYGEN__)
740 #if STM32_INPUT_CAPTURE_ENABLE_TIM8_ISR
741 #if defined(STM32_TIM8_UP_TIM13_HANDLER)
747 OSAL_IRQ_HANDLER(STM32_TIM8_UP_TIM13_HANDLER) {
748 
749  OSAL_IRQ_PROLOGUE();
750 
751  input_capture_lld_serve_interrupt(driverByTimerIndex[5]);
752 
753  OSAL_IRQ_EPILOGUE();
754 }
755 #endif
756 
757 #if !defined(STM32_TIM8_CC_HANDLER)
758 #error "STM32_TIM8_CC_HANDLER not defined"
759 #endif
765 OSAL_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) {
766 
767  OSAL_IRQ_PROLOGUE();
768 
769  input_capture_lld_serve_interrupt(driverByTimerIndex[5]);
770 
771  OSAL_IRQ_EPILOGUE();
772 }
773 #endif /* STM32_INPUT_CAPTURE_ENABLE_TIM8_ISR */
774 #endif /* STM32_INPUT_CAPTURE_USE_TIM8 */
775 
776 static void input_capture_lld_serve_interrupt(const TimICDriver * const timicp)
777 {
778  uint32_t sr;
779  stm32_tim_t * const timer = timicp->config->timer;
780 
781  sr = timer->SR;
782  sr &= (timer->DIER & STM32_TIM_DIER_IRQ_MASK);
783  timer->SR = ~sr;
784 
785  if (timicp->channel & TIMIC_CH1) {
786  if ((sr & STM32_TIM_SR_CC1IF) != 0)
787  _input_capture_isr_invoke_capture_cb(timicp, 0);
788  }
789  if (timicp->channel & TIMIC_CH2) {
790  if ((sr & STM32_TIM_SR_CC2IF) != 0)
791  _input_capture_isr_invoke_capture_cb(timicp, 1);
792  }
793  if (timicp->channel & TIMIC_CH3) {
794  if ((sr & STM32_TIM_SR_CC3IF) != 0)
795  _input_capture_isr_invoke_capture_cb(timicp, 2);
796  }
797  if (timicp->channel & TIMIC_CH4) {
798  if ((sr & STM32_TIM_SR_CC4IF) != 0)
799  _input_capture_isr_invoke_capture_cb(timicp, 3);
800  }
801 
802  if ((sr & STM32_TIM_SR_UIF) != 0)
803  _input_capture_isr_invoke_overflow_cb(timicp);
804 }
805 
806 static void _input_capture_isr_invoke_capture_cb(const TimICDriver * const timicp, uint32_t channel)
807 {
808  if (timicp->config->capture_cb) {
809  timicp->config->capture_cb(timicp, channel, timicp->config->timer->CCR[channel]);
810  }
811 }
812 
813 static void _input_capture_isr_invoke_overflow_cb(const TimICDriver * const timicp)
814 {
815  if (timicp->config->overflow_cb)
816  timicp->config->overflow_cb(timicp);
817 }
STM32_IRQ_TIM1_UP_TIM10_PRIORITY
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY
Definition: mcuconf.h:90
STM32_IRQ_TIM5_PRIORITY
#define STM32_IRQ_TIM5_PRIORITY
Definition: mcuconf.h:96
STM32_IRQ_TIM8_UP_TIM13_PRIORITY
#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY
Definition: mcuconf.h:100
STM32_IRQ_TIM2_PRIORITY
#define STM32_IRQ_TIM2_PRIORITY
Definition: mcuconf.h:93
STM32_IRQ_TIM4_PRIORITY
#define STM32_IRQ_TIM4_PRIORITY
Definition: mcuconf.h:95
STM32_IRQ_TIM3_PRIORITY
#define STM32_IRQ_TIM3_PRIORITY
Definition: mcuconf.h:94
STM32_IRQ_TIM1_CC_PRIORITY
#define STM32_IRQ_TIM1_CC_PRIORITY
Definition: mcuconf.h:92
STM32_IRQ_TIM8_CC_PRIORITY
#define STM32_IRQ_TIM8_CC_PRIORITY
Definition: mcuconf.h:102
input_capture_lld_serve_interrupt
static void input_capture_lld_serve_interrupt(const TimICDriver *const timicp)
Definition: input_capture_arch.c:776
timIcStop
void timIcStop(TimICDriver *timicp)
stop a quadrature encoder driver
Definition: input_capture_arch.c:225
timIcObjectInit
void timIcObjectInit(TimICDriver *timicp)
Initializes an input capture driver.
Definition: input_capture_arch.c:13
_input_capture_isr_invoke_capture_cb
static void _input_capture_isr_invoke_capture_cb(const TimICDriver *const timicp, uint32_t channel)
Definition: input_capture_arch.c:806
timIcStopCapture
void timIcStopCapture(TimICDriver *timicp)
stop to capture
Definition: input_capture_arch.c:214
timIcRccEnable
void timIcRccEnable(const TimICDriver *const timicp)
Definition: input_capture_arch.c:239
timIcStart
void timIcStart(TimICDriver *timicp, const TimICConfig *configp)
start an input capture driver
Definition: input_capture_arch.c:20
timIcStartCapture
void timIcStartCapture(TimICDriver *timicp)
start to capture
Definition: input_capture_arch.c:200
_input_capture_isr_invoke_overflow_cb
static void _input_capture_isr_invoke_overflow_cb(const TimICDriver *const timicp)
Definition: input_capture_arch.c:813
timIcRccDisable
void timIcRccDisable(const TimICDriver *const timicp)
Definition: input_capture_arch.c:384
TimICChannel
TimICChannel
Definition: input_capture_arch.c:4
TIMIC_CH1
@ TIMIC_CH1
Definition: input_capture_arch.c:4
TIMIC_CH4
@ TIMIC_CH4
Definition: input_capture_arch.c:4
TIMIC_CH2
@ TIMIC_CH2
Definition: input_capture_arch.c:4
TIMIC_CH3
@ TIMIC_CH3
Definition: input_capture_arch.c:4
driverByTimerIndex
static const TimICDriver * driverByTimerIndex[6]
Definition: input_capture_arch.c:6
input_capture_arch.h
TimICConfig::dcr
uint32_t dcr
Definition: input_capture_arch.h:35
TimICConfig::capture_cb
TimICCallbackCapture_t capture_cb
Definition: input_capture_arch.h:30
TimICDriver::channel
uint32_t channel
mutex to protect data read/write in concurrent context
Definition: input_capture_arch.h:52
TimICDriver::mut
mutex_t mut
Definition: input_capture_arch.h:54
TIMIC_READY
@ TIMIC_READY
Definition: input_capture_arch.h:17
TIMIC_ACTIVE
@ TIMIC_ACTIVE
Definition: input_capture_arch.h:17
TIMIC_STOP
@ TIMIC_STOP
Definition: input_capture_arch.h:17
TimICDriver::dier
uint32_t dier
Definition: input_capture_arch.h:53
CH2_FALLING_EDGE
@ CH2_FALLING_EDGE
Definition: input_capture_arch.h:13
CH1_RISING_EDGE
@ CH1_RISING_EDGE
Definition: input_capture_arch.h:12
CH4_RISING_EDGE
@ CH4_RISING_EDGE
Definition: input_capture_arch.h:15
CH3_RISING_EDGE
@ CH3_RISING_EDGE
Definition: input_capture_arch.h:14
CH2_RISING_EDGE
@ CH2_RISING_EDGE
Definition: input_capture_arch.h:13
CH1_BOTH_EDGES
@ CH1_BOTH_EDGES
Definition: input_capture_arch.h:12
CH4_FALLING_EDGE
@ CH4_FALLING_EDGE
Definition: input_capture_arch.h:15
CH3_BOTH_EDGES
@ CH3_BOTH_EDGES
Definition: input_capture_arch.h:14
CH3_FALLING_EDGE
@ CH3_FALLING_EDGE
Definition: input_capture_arch.h:14
CH4_BOTH_EDGES
@ CH4_BOTH_EDGES
Definition: input_capture_arch.h:15
CH1_FALLING_EDGE
@ CH1_FALLING_EDGE
Definition: input_capture_arch.h:12
CH2_BOTH_EDGES
@ CH2_BOTH_EDGES
Definition: input_capture_arch.h:13
TimICConfig::prescaler
uint32_t prescaler
Definition: input_capture_arch.h:36
TimICConfig::overflow_cb
TimICCallbackOverflow_t overflow_cb
Definition: input_capture_arch.h:31
TIMIC_INPUT_CAPTURE
@ TIMIC_INPUT_CAPTURE
Definition: input_capture_arch.h:11
TIMIC_PWM_IN
@ TIMIC_PWM_IN
Definition: input_capture_arch.h:11
TimICConfig::active
uint32_t active
Definition: input_capture_arch.h:33
TimICDriver::state
enum TimICState state
Definition: input_capture_arch.h:55
TimICConfig::arr
uint32_t arr
Definition: input_capture_arch.h:37
TimICConfig::mode
enum TimICMode mode
Definition: input_capture_arch.h:32
TimICDriver::config
const TimICConfig * config
Current configuration data.
Definition: input_capture_arch.h:48
TimICConfig::timer
stm32_tim_t * timer
hardware timer pointer (example : &STM32_TIM1)
Definition: input_capture_arch.h:29
TimICConfig::dier
uint32_t dier
Definition: input_capture_arch.h:34
TimICConfig
TimIC Driver configuration structure.
Definition: input_capture_arch.h:25
TimICDriver
Structure representing a TimIC driver.
Definition: input_capture_arch.h:44
uint32_t
unsigned int uint32_t
Typedef defining 32 bit unsigned int type.
Definition: vl53l1_types.h:78