Paparazzi UAS  v5.18.0_stable
Paparazzi is a free software Unmanned Aircraft System.
mcuconf.h
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1 /*
2  ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3 
4  Licensed under the Apache License, Version 2.0 (the "License");
5  you may not use this file except in compliance with the License.
6  You may obtain a copy of the License at
7 
8  http://www.apache.org/licenses/LICENSE-2.0
9 
10  Unless required by applicable law or agreed to in writing, software
11  distributed under the License is distributed on an "AS IS" BASIS,
12  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  See the License for the specific language governing permissions and
14  limitations under the License.
15 */
16 
17 #ifndef MCUCONF_H
18 #define MCUCONF_H
19 
20 /*
21  * STM32F7xx drivers configuration.
22  * The following settings override the default settings present in
23  * the various device driver implementation headers.
24  * Note that the settings for each driver only have effect if the whole
25  * driver is enabled in halconf.h.
26  *
27  * IRQ priorities:
28  * 15...0 Lowest...Highest.
29  *
30  * DMA priorities:
31  * 0...3 Lowest...Highest.
32  */
33 
34 #define STM32F7xx_MCUCONF
35 #define STM32F765_MCUCONF
36 #define STM32F767_MCUCONF
37 #define STM32F777_MCUCONF
38 #define STM32F769_MCUCONF
39 #define STM32F779_MCUCONF
40 
41 /*
42  * HAL driver system settings.
43  */
44 #define STM32_NO_INIT FALSE
45 #define STM32_PVD_ENABLE FALSE
46 #define STM32_PLS STM32_PLS_LEV0
47 #define STM32_BKPRAM_ENABLE FALSE
48 #define STM32_HSI_ENABLED TRUE
49 #define STM32_LSI_ENABLED FALSE
50 #define STM32_HSE_ENABLED TRUE
51 #define STM32_LSE_ENABLED TRUE
52 #define STM32_CLOCK48_REQUIRED TRUE
53 #define STM32_SW STM32_SW_PLL
54 #define STM32_PLLSRC STM32_PLLSRC_HSE
55 #define STM32_PLLM_VALUE 8
56 #define STM32_PLLN_VALUE 432
57 #define STM32_PLLP_VALUE 2
58 #define STM32_PLLQ_VALUE 9
59 #define STM32_HPRE STM32_HPRE_DIV1
60 #define STM32_PPRE1 STM32_PPRE1_DIV4
61 #define STM32_PPRE2 STM32_PPRE2_DIV2
62 #if HAL_USE_RTC
63 #define STM32_RTCSEL STM32_RTCSEL_LSE
64 #else
65 #define STM32_RTCSEL STM32_RTCSEL_NOCLOCK
66 #endif
67 #define STM32_RTCPRE_VALUE 25
68 #define STM32_MCO1SEL STM32_MCO1SEL_HSI
69 #define STM32_MCO1PRE STM32_MCO1PRE_DIV1
70 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
71 #define STM32_MCO2PRE STM32_MCO2PRE_DIV4
72 #define STM32_TIMPRE_ENABLE FALSE
73 #define STM32_I2SSRC STM32_I2SSRC_OFF
74 #define STM32_PLLI2SN_VALUE 192
75 #define STM32_PLLI2SP_VALUE 4
76 #define STM32_PLLI2SQ_VALUE 4
77 #define STM32_PLLI2SR_VALUE 4
78 #define STM32_PLLI2SDIVQ_VALUE 2
79 #define STM32_PLLSAIN_VALUE 192
80 #define STM32_PLLSAIP_VALUE 4
81 #define STM32_PLLSAIQ_VALUE 4
82 #define STM32_PLLSAIR_VALUE 4
83 #define STM32_PLLSAIDIVQ_VALUE 2
84 #define STM32_PLLSAIDIVR_VALUE 2
85 #define STM32_SAI1SEL STM32_SAI1SEL_OFF
86 #define STM32_SAI2SEL STM32_SAI2SEL_OFF
87 #define STM32_LCDTFT_REQUIRED FALSE
88 #define STM32_USART1SEL STM32_USART1SEL_PCLK2
89 #define STM32_USART2SEL STM32_USART2SEL_PCLK1
90 #define STM32_USART3SEL STM32_USART3SEL_PCLK1
91 #define STM32_UART4SEL STM32_UART4SEL_PCLK1
92 #define STM32_UART5SEL STM32_UART5SEL_PCLK1
93 #define STM32_USART6SEL STM32_USART6SEL_PCLK2
94 #define STM32_UART7SEL STM32_UART7SEL_PCLK1
95 #define STM32_UART8SEL STM32_UART8SEL_PCLK1
96 #define STM32_I2C1SEL STM32_I2C1SEL_PCLK1
97 #define STM32_I2C2SEL STM32_I2C2SEL_PCLK1
98 #define STM32_I2C3SEL STM32_I2C3SEL_PCLK1
99 #define STM32_I2C4SEL STM32_I2C4SEL_PCLK1
100 #define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
101 #define STM32_CECSEL STM32_CECSEL_LSE
102 #define STM32_CK48MSEL STM32_CK48MSEL_PLL
103 #define STM32_SDMMC1SEL STM32_SDMMC1SEL_PLL48CLK
104 #define STM32_SDMMC2SEL STM32_SDMMC2SEL_PLL48CLK
105 #define STM32_SRAM2_NOCACHE FALSE
106 
107 /*
108  * IRQ system settings.
109  */
110 #define STM32_IRQ_EXTI0_PRIORITY 6
111 #define STM32_IRQ_EXTI1_PRIORITY 6
112 #define STM32_IRQ_EXTI2_PRIORITY 6
113 #define STM32_IRQ_EXTI3_PRIORITY 6
114 #define STM32_IRQ_EXTI4_PRIORITY 6
115 #define STM32_IRQ_EXTI5_9_PRIORITY 6
116 #define STM32_IRQ_EXTI10_15_PRIORITY 6
117 #define STM32_IRQ_EXTI16_PRIORITY 6
118 #define STM32_IRQ_EXTI17_PRIORITY 15
119 #define STM32_IRQ_EXTI18_PRIORITY 6
120 #define STM32_IRQ_EXTI19_PRIORITY 6
121 #define STM32_IRQ_EXTI20_PRIORITY 6
122 #define STM32_IRQ_EXTI21_PRIORITY 15
123 #define STM32_IRQ_EXTI22_PRIORITY 15
124 #define STM32_IRQ_EXTI23_PRIORITY 6
125 
126 #define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7
127 #define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7
128 #define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7
129 #define STM32_IRQ_TIM1_CC_PRIORITY 7
130 #define STM32_IRQ_TIM2_PRIORITY 7
131 #define STM32_IRQ_TIM3_PRIORITY 7
132 #define STM32_IRQ_TIM4_PRIORITY 7
133 #define STM32_IRQ_TIM5_PRIORITY 7
134 #define STM32_IRQ_TIM6_PRIORITY 7
135 #define STM32_IRQ_TIM7_PRIORITY 7
136 #define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7
137 #define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7
138 #define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7
139 #define STM32_IRQ_TIM8_CC_PRIORITY 7
140 
141 #define STM32_IRQ_USART1_PRIORITY 12
142 #define STM32_IRQ_USART2_PRIORITY 12
143 #define STM32_IRQ_USART3_PRIORITY 12
144 #define STM32_IRQ_UART4_PRIORITY 12
145 #define STM32_IRQ_UART5_PRIORITY 12
146 #define STM32_IRQ_USART6_PRIORITY 12
147 #define STM32_IRQ_UART7_PRIORITY 12
148 #define STM32_IRQ_UART8_PRIORITY 12
149 
150 /*
151  * ADC driver system settings.
152  */
153 #define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
154 #define STM32_ADC_USE_ADC1 TRUE
155 #define STM32_ADC_USE_ADC2 FALSE
156 #define STM32_ADC_USE_ADC3 FALSE
157 #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
158 #define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
159 #define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
160 #define STM32_ADC_ADC1_DMA_PRIORITY 2
161 #define STM32_ADC_ADC2_DMA_PRIORITY 2
162 #define STM32_ADC_ADC3_DMA_PRIORITY 2
163 #define STM32_ADC_IRQ_PRIORITY 6
164 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
165 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
166 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
167 
168 /*
169  * CAN driver system settings.
170  */
171 #if USE_CAN1
172 #define STM32_CAN_USE_CAN1 TRUE
173 #else
174 #define STM32_CAN_USE_CAN1 FALSE
175 #endif
176 #define STM32_CAN_USE_CAN2 FALSE
177 #define STM32_CAN_USE_CAN3 FALSE
178 #define STM32_CAN_CAN1_IRQ_PRIORITY 11
179 #define STM32_CAN_CAN2_IRQ_PRIORITY 11
180 #define STM32_CAN_CAN3_IRQ_PRIORITY 11
181 
182 /*
183  * DAC driver system settings.
184  */
185 #define STM32_DAC_DUAL_MODE FALSE
186 #define STM32_DAC_USE_DAC1_CH1 FALSE
187 #define STM32_DAC_USE_DAC1_CH2 FALSE
188 #define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
189 #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
190 #define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
191 #define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
192 #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
193 #define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
194 
195 /*
196  * GPT driver system settings.
197  */
198 #define STM32_GPT_USE_TIM1 FALSE
199 #define STM32_GPT_USE_TIM2 FALSE // keep free if in tickless mode
200 #define STM32_GPT_USE_TIM3 FALSE
201 #define STM32_GPT_USE_TIM4 FALSE
202 #define STM32_GPT_USE_TIM5 FALSE
203 #define STM32_GPT_USE_TIM6 FALSE
204 #define STM32_GPT_USE_TIM7 FALSE
205 #define STM32_GPT_USE_TIM8 FALSE
206 #define STM32_GPT_USE_TIM9 FALSE
207 #define STM32_GPT_USE_TIM10 FALSE
208 #define STM32_GPT_USE_TIM11 FALSE
209 #define STM32_GPT_USE_TIM12 FALSE
210 #define STM32_GPT_USE_TIM13 FALSE
211 #define STM32_GPT_USE_TIM14 FALSE
212 #define STM32_GPT_USE_TIM15 FALSE
213 #define STM32_GPT_USE_TIM16 FALSE
214 #define STM32_GPT_USE_TIM17 FALSE
215 
216 /*
217  * I2C driver system settings.
218  */
219 #define STM32_I2C_USE_I2C1 FALSE // incompatible with I2C2 and I2C4
220 #if USE_I2C2
221 #define STM32_I2C_USE_I2C2 TRUE
222 #else
223 #define STM32_I2C_USE_I2C2 FALSE
224 #endif
225 #define STM32_I2C_USE_I2C3 FALSE
226 #if USE_I2C4
227 #define STM32_I2C_USE_I2C4 TRUE
228 #else
229 #define STM32_I2C_USE_I2C4 FALSE
230 #endif
231 #define STM32_I2C_BUSY_TIMEOUT 50
232 #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
233 #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
234 #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
235 #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
236 #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
237 #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
238 #define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
239 #define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
240 #define STM32_I2C_I2C1_IRQ_PRIORITY 5
241 #define STM32_I2C_I2C2_IRQ_PRIORITY 5
242 #define STM32_I2C_I2C3_IRQ_PRIORITY 5
243 #define STM32_I2C_I2C4_IRQ_PRIORITY 5
244 #define STM32_I2C_I2C1_DMA_PRIORITY 3
245 #define STM32_I2C_I2C2_DMA_PRIORITY 3
246 #define STM32_I2C_I2C3_DMA_PRIORITY 3
247 #define STM32_I2C_I2C4_DMA_PRIORITY 3
248 #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
249 
250 /*
251  * ICU driver system settings.
252  */
253 #define STM32_ICU_USE_TIM1 FALSE
254 #ifdef USE_PWM_INPUT1
255 #define STM32_ICU_USE_TIM2 TRUE
256 #else
257 #define STM32_ICU_USE_TIM2 FALSE // keep free if in tickless mode
258 #endif
259 #define STM32_ICU_USE_TIM3 FALSE
260 #define STM32_ICU_USE_TIM4 FALSE
261 #if RADIO_CONTROL_TYPE_PPM
262 #define STM32_ICU_USE_TIM5 TRUE
263 #else
264 #define STM32_ICU_USE_TIM5 FALSE
265 #endif
266 #ifdef USE_PWM_INPUT2
267 #define STM32_ICU_USE_TIM8 TRUE
268 #else
269 #define STM32_ICU_USE_TIM8 FALSE
270 #endif
271 #define STM32_ICU_USE_TIM9 FALSE
272 #define STM32_ICU_USE_TIM10 FALSE
273 #define STM32_ICU_USE_TIM11 FALSE
274 #define STM32_ICU_USE_TIM12 FALSE
275 #define STM32_ICU_USE_TIM13 FALSE
276 #define STM32_ICU_USE_TIM14 FALSE
277 #define STM32_ICU_USE_TIM15 FALSE
278 #define STM32_ICU_USE_TIM16 FALSE
279 #define STM32_ICU_USE_TIM17 FALSE
280 
281 /*
282  * MAC driver system settings.
283  */
284 #define STM32_MAC_TRANSMIT_BUFFERS 2
285 #define STM32_MAC_RECEIVE_BUFFERS 4
286 #define STM32_MAC_BUFFERS_SIZE 1522
287 #define STM32_MAC_PHY_TIMEOUT 100
288 #define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
289 #define STM32_MAC_ETH1_IRQ_PRIORITY 13
290 #define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
291 
292 /*
293  * PWM driver system settings.
294  */
295 #define STM32_PWM_USE_ADVANCED FALSE
296 #ifndef STM32_PWM_USE_TIM1
297 #define STM32_PWM_USE_TIM1 TRUE
298 #endif
299 #ifndef STM32_PWM_USE_TIM2
300 #define STM32_PWM_USE_TIM2 FALSE // keep free if in tickless mode, can be used in systick mode
301 #endif
302 #ifndef STM32_PWM_USE_TIM3
303 #define STM32_PWM_USE_TIM3 FALSE // enable for servo 12, 14, 15, 16 on AUX connectors
304 #endif
305 #ifndef STM32_PWM_USE_TIM4
306 #define STM32_PWM_USE_TIM4 TRUE
307 #endif
308 #ifndef STM32_PWM_USE_TIM5
309 #define STM32_PWM_USE_TIM5 FALSE // enable for servo 9, 10, 11, 13 on AUX connectors
310 #endif
311 #define STM32_PWM_USE_TIM8 FALSE
312 #define STM32_PWM_USE_TIM9 FALSE
313 #define STM32_PWM_USE_TIM10 FALSE
314 #define STM32_PWM_USE_TIM11 FALSE
315 #define STM32_PWM_USE_TIM12 FALSE
316 #define STM32_PWM_USE_TIM13 FALSE
317 #define STM32_PWM_USE_TIM14 FALSE
318 #define STM32_PWM_USE_TIM15 FALSE
319 #define STM32_PWM_USE_TIM16 FALSE
320 #define STM32_PWM_USE_TIM17 FALSE
321 
322 /*
323  * RTC driver system settings.
324  */
325 #define STM32_RTC_PRESA_VALUE 32
326 #define STM32_RTC_PRESS_VALUE 1024
327 #define STM32_RTC_CR_INIT 0
328 #define STM32_RTC_TAMPCR_INIT 0
329 
330 /*
331  * SDC driver system settings.
332  */
333 #define STM32_SDC_USE_SDMMC1 FALSE
334 #define STM32_SDC_USE_SDMMC2 FALSE
335 #define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE
336 #define STM32_SDC_SDMMC_WRITE_TIMEOUT 250
337 #define STM32_SDC_SDMMC_READ_TIMEOUT 25
338 #define STM32_SDC_SDMMC_CLOCK_DELAY 10
339 #define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
340 #define STM32_SDC_SDMMC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
341 #define STM32_SDC_SDMMC1_DMA_PRIORITY 3
342 #define STM32_SDC_SDMMC2_DMA_PRIORITY 3
343 #define STM32_SDC_SDMMC1_IRQ_PRIORITY 9
344 #define STM32_SDC_SDMMC2_IRQ_PRIORITY 9
345 
346 /*
347  * SERIAL driver system settings.
348  */
349 #if USE_UART1
350 #define STM32_SERIAL_USE_USART1 TRUE
351 #else
352 #define STM32_SERIAL_USE_USART1 FALSE
353 #endif
354 #if USE_UART2
355 #define STM32_SERIAL_USE_USART2 TRUE
356 #else
357 #define STM32_SERIAL_USE_USART2 FALSE
358 #endif
359 #if USE_UART3
360 #define STM32_SERIAL_USE_USART3 TRUE
361 #else
362 #define STM32_SERIAL_USE_USART3 FALSE
363 #endif
364 #if USE_UART4
365 #define STM32_SERIAL_USE_UART4 TRUE
366 #else
367 #define STM32_SERIAL_USE_UART4 FALSE
368 #endif
369 #if USE_UART5
370 #define STM32_SERIAL_USE_UART5 TRUE
371 #else
372 #define STM32_SERIAL_USE_UART5 FALSE
373 #endif
374 #if USE_UART6
375 #define STM32_SERIAL_USE_USART6 TRUE
376 #else
377 #define STM32_SERIAL_USE_USART6 FALSE
378 #endif
379 #if USE_UART7
380 #define STM32_SERIAL_USE_UART7 TRUE
381 #else
382 #define STM32_SERIAL_USE_UART7 FALSE
383 #endif
384 #if USE_UART8
385 #define STM32_SERIAL_USE_UART8 TRUE
386 #else
387 #define STM32_SERIAL_USE_UART8 FALSE
388 #endif
389 
390 /*
391  * SPI driver system settings.
392  */
393 #define STM32_SPI_USE_SPI1 FALSE
394 #if USE_SPI2
395 #define STM32_SPI_USE_SPI2 TRUE
396 #else
397 #define STM32_SPI_USE_SPI2 FALSE
398 #endif
399 #define STM32_SPI_USE_SPI3 FALSE
400 #define STM32_SPI_USE_SPI4 TRUE
401 #define STM32_SPI_USE_SPI5 FALSE
402 #define STM32_SPI_USE_SPI6 FALSE
403 #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
404 #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
405 #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
406 #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
407 #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
408 #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
409 #define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
410 #define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
411 #define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
412 #define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
413 #define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
414 #define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
415 #define STM32_SPI_SPI1_DMA_PRIORITY 1
416 #define STM32_SPI_SPI2_DMA_PRIORITY 1
417 #define STM32_SPI_SPI3_DMA_PRIORITY 1
418 #define STM32_SPI_SPI4_DMA_PRIORITY 1
419 #define STM32_SPI_SPI5_DMA_PRIORITY 1
420 #define STM32_SPI_SPI6_DMA_PRIORITY 1
421 #define STM32_SPI_SPI1_IRQ_PRIORITY 10
422 #define STM32_SPI_SPI2_IRQ_PRIORITY 10
423 #define STM32_SPI_SPI3_IRQ_PRIORITY 10
424 #define STM32_SPI_SPI4_IRQ_PRIORITY 10
425 #define STM32_SPI_SPI5_IRQ_PRIORITY 10
426 #define STM32_SPI_SPI6_IRQ_PRIORITY 10
427 #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
428 
429 /*
430  * ST driver system settings.
431  */
432 #define STM32_ST_IRQ_PRIORITY 8
433 #define STM32_ST_USE_TIMER 2
434 
435 /*
436  * TRNG driver system settings.
437  */
438 #define STM32_TRNG_USE_RNG1 FALSE
439 
440 /*
441  * UART driver system settings.
442  */
443 #define STM32_UART_USE_USART1 FALSE /* DMA OK */
444 #define STM32_UART_USE_USART2 FALSE /* NO DMA AVAIL */
445 #define STM32_UART_USE_USART3 FALSE /* DMA OK */
446 #define STM32_UART_USE_UART4 FALSE /* NO DMA AVAIL */
447 #define STM32_UART_USE_UART5 FALSE /* NO DMA AVAIL */
448 #define STM32_UART_USE_USART6 FALSE /* NO DMA AVAIL */
449 #define STM32_UART_USE_UART7 FALSE /* NO DMA AVAIL */
450 #define STM32_UART_USE_UART8 FALSE /* NO DMA AVAIL */
451 #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
452 #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
453 #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
454 #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
455 #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
456 #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
457 #define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
458 #define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
459 #define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
460 #define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
461 #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
462 #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
463 #define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
464 #define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
465 #define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
466 #define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
467 #define STM32_UART_USART1_DMA_PRIORITY 0
468 #define STM32_UART_USART2_DMA_PRIORITY 0
469 #define STM32_UART_USART3_DMA_PRIORITY 0
470 #define STM32_UART_UART4_DMA_PRIORITY 0
471 #define STM32_UART_UART5_DMA_PRIORITY 0
472 #define STM32_UART_USART6_DMA_PRIORITY 0
473 #define STM32_UART_UART7_DMA_PRIORITY 0
474 #define STM32_UART_UART8_DMA_PRIORITY 0
475 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
476 
477 /*
478  * USB driver system settings.
479  */
480 #define STM32_USB_USE_OTG1 TRUE
481 #define STM32_USB_USE_OTG2 FALSE
482 #define STM32_USB_OTG1_IRQ_PRIORITY 14
483 #define STM32_USB_OTG2_IRQ_PRIORITY 14
484 #define STM32_USB_OTG1_RX_FIFO_SIZE 512
485 #define STM32_USB_OTG2_RX_FIFO_SIZE 1024
486 
487 /*
488  * WDG driver system settings.
489  */
490 #define STM32_WDG_USE_IWDG FALSE
491 
492 /*
493  * WSPI driver system settings.
494  */
495 #define STM32_WSPI_USE_QUADSPI1 FALSE
496 #define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
497 
498 #endif /* MCUCONF_H */