Paparazzi UAS  v5.10_stable-5-g83a0da5-dirty
Paparazzi is a free software Unmanned Aircraft System.
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mt9f002.c
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1 /*
2  * Copyright (C) 2016 Freek van Tienen <freek.v.tienen@gmail.com>
3  *
4  * This file is part of Paparazzi.
5  *
6  * Paparazzi is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2, or (at your option)
9  * any later version.
10  *
11  * Paparazzi is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with paparazzi; see the file COPYING. If not, see
18  * <http://www.gnu.org/licenses/>.
19  *
20  */
21 
27 #include "std.h"
28 #include "mt9f002.h"
29 #include "mt9f002_regs.h"
30 #include "math/pprz_algebra_int.h"
31 #include "boards/bebop.h"
32 
33 #include <stdio.h>
34 #include <unistd.h>
35 #include <fcntl.h>
36 #include <sys/ioctl.h>
37 #include <linux/i2c-dev.h>
38 #include <linux/videodev2.h>
39 #include <linux/v4l2-mediabus.h>
40 
41 #define MAX(x,y) (((x) > (y)) ? (x) : (y))
42 
43 /* Camera structure */
44 struct video_config_t front_camera = {
45  .output_size = {
46  .w = MT9F002_OUTPUT_WIDTH,
47  .h = MT9F002_OUTPUT_HEIGHT
48  },
49  .sensor_size = {
50  .w = MT9F002_OUTPUT_WIDTH,
51  .h = MT9F002_OUTPUT_HEIGHT,
52  },
53  .crop = {
54  .x = 0,
55  .y = 0,
56  .w = MT9F002_OUTPUT_WIDTH,
57  .h = MT9F002_OUTPUT_HEIGHT
58  },
59  .dev_name = "/dev/video1",
60  .subdev_name = "/dev/v4l-subdev1",
61  .format = V4L2_PIX_FMT_UYVY,
62  .subdev_format = V4L2_MBUS_FMT_SGRBG10_1X10,
63  .buf_cnt = 3,
64  .filters = VIDEO_FILTER_ISP,
65  .cv_listener = NULL,
66  .fps = MT9F002_TARGET_FPS
67 };
68 
72 static void write_reg(struct mt9f002_t *mt, uint16_t addr, uint32_t val, uint8_t len)
73 {
74  mt->i2c_trans.buf[0] = addr >> 8;
75  mt->i2c_trans.buf[1] = addr & 0xFF;
76 
77  // Fix sigdness based on length
78  if(len == 1) {
79  mt->i2c_trans.buf[2] = val & 0xFF;
80  }
81  else if(len == 2) {
82  mt->i2c_trans.buf[2] = (val >> 8) & 0xFF;
83  mt->i2c_trans.buf[3] = val & 0xFF;
84  }
85  else if(len == 4) {
86  mt->i2c_trans.buf[2] = (val >> 24) & 0xFF;
87  mt->i2c_trans.buf[3] = (val >> 16) & 0xFF;
88  mt->i2c_trans.buf[4] = (val >> 8) & 0xFF;
89  mt->i2c_trans.buf[5] = val & 0xFF;
90  }
91  else {
92  printf("[MT9F002] write_reg with incorrect length %d\r\n", len);
93  }
94 
95  // Transmit the buffer
96  i2c_transmit(mt->i2c_periph, &mt->i2c_trans, MT9F002_ADDRESS, len + 2);
97 }
98 
102 static uint32_t read_reg(struct mt9f002_t *mt, uint16_t addr, uint8_t len)
103 {
104  uint32_t ret = 0;
105  mt->i2c_trans.buf[0] = addr >> 8;
106  mt->i2c_trans.buf[1] = addr & 0xFF;
107 
108  // Transmit the buffer and receive back
109  i2c_transceive(mt->i2c_periph, &mt->i2c_trans, MT9F002_ADDRESS, 2, len);
110 
111  /* Fix sigdness */
112  for(uint8_t i =0; i < len; i++) {
113  ret |= mt->i2c_trans.buf[len-i-1] << (8*i);
114  }
115  return ret;
116 }
117 
121 static inline void mt9f002_mipi_stage1(struct mt9f002_t *mt)
122 {
123  write_reg(mt, MT9F002_RESET_REGISTER, 0x0118, 2);
124  write_reg(mt, MT9F002_MODE_SELECT, 0x00, 1);
125 
126  uint32_t serialFormat;
127  if (mt->interface == MT9F002_HiSPi) {
128  serialFormat = (3<<8) | 2; // 2 Serial lanes
129  }
130  else {
131  serialFormat = (2<<8) | 2; // 2 Serial lanes
132  }
133  write_reg(mt, MT9F002_SERIAL_FORMAT, serialFormat, 2);
134  uint32_t dataFormat = (8 << 8) | 8; // 8 Bits pixel depth
135  write_reg(mt, MT9F002_CPP_DATA_FORMAT, dataFormat, 2);
136 
137  write_reg(mt, MT9F002_MFR_3D00, 0x0435, 2);
138  write_reg(mt, MT9F002_MFR_3D02, 0x435D, 2);
139  write_reg(mt, MT9F002_MFR_3D04, 0x6698, 2);
140  write_reg(mt, MT9F002_MFR_3D06, 0xFFFF, 2);
141  write_reg(mt, MT9F002_MFR_3D08, 0x7783, 2);
142  write_reg(mt, MT9F002_MFR_3D0A, 0x101B, 2);
143  write_reg(mt, MT9F002_MFR_3D0C, 0x732C, 2);
144  write_reg(mt, MT9F002_MFR_3D0E, 0x4230, 2);
145  write_reg(mt, MT9F002_MFR_3D10, 0x5881, 2);
146  write_reg(mt, MT9F002_MFR_3D12, 0x5C3A, 2);
147  write_reg(mt, MT9F002_MFR_3D14, 0x0140, 2);
148  write_reg(mt, MT9F002_MFR_3D16, 0x2300, 2);
149  write_reg(mt, MT9F002_MFR_3D18, 0x815F, 2);
150  write_reg(mt, MT9F002_MFR_3D1A, 0x6789, 2);
151  write_reg(mt, MT9F002_MFR_3D1C, 0x5920, 2);
152  write_reg(mt, MT9F002_MFR_3D1E, 0x0C20, 2);
153  write_reg(mt, MT9F002_MFR_3D20, 0x21C0, 2);
154  write_reg(mt, MT9F002_MFR_3D22, 0x4684, 2);
155  write_reg(mt, MT9F002_MFR_3D24, 0x4892, 2);
156  write_reg(mt, MT9F002_MFR_3D26, 0x1A00, 2);
157  write_reg(mt, MT9F002_MFR_3D28, 0xBA4C, 2);
158  write_reg(mt, MT9F002_MFR_3D2A, 0x8D48, 2);
159  write_reg(mt, MT9F002_MFR_3D2C, 0x4641, 2);
160  write_reg(mt, MT9F002_MFR_3D2E, 0x408C, 2);
161  write_reg(mt, MT9F002_MFR_3D30, 0x4784, 2);
162  write_reg(mt, MT9F002_MFR_3D32, 0x4A87, 2);
163  write_reg(mt, MT9F002_MFR_3D34, 0x561A, 2);
164  write_reg(mt, MT9F002_MFR_3D36, 0x00A5, 2);
165  write_reg(mt, MT9F002_MFR_3D38, 0x1A00, 2);
166  write_reg(mt, MT9F002_MFR_3D3A, 0x5693, 2);
167  write_reg(mt, MT9F002_MFR_3D3C, 0x4D8D, 2);
168  write_reg(mt, MT9F002_MFR_3D3E, 0x4A47, 2);
169  write_reg(mt, MT9F002_MFR_3D40, 0x4041, 2);
170  write_reg(mt, MT9F002_MFR_3D42, 0x8200, 2);
171  write_reg(mt, MT9F002_MFR_3D44, 0x24B7, 2);
172  write_reg(mt, MT9F002_MFR_3D46, 0x0024, 2);
173  write_reg(mt, MT9F002_MFR_3D48, 0x8D4F, 2);
174  write_reg(mt, MT9F002_MFR_3D4A, 0x831A, 2);
175  write_reg(mt, MT9F002_MFR_3D4C, 0x00B4, 2);
176  write_reg(mt, MT9F002_MFR_3D4E, 0x4684, 2);
177  write_reg(mt, MT9F002_MFR_3D50, 0x49CE, 2);
178  write_reg(mt, MT9F002_MFR_3D52, 0x4946, 2);
179  write_reg(mt, MT9F002_MFR_3D54, 0x4140, 2);
180  write_reg(mt, MT9F002_MFR_3D56, 0x9247, 2);
181  write_reg(mt, MT9F002_MFR_3D58, 0x844B, 2);
182  write_reg(mt, MT9F002_MFR_3D5A, 0xCE4B, 2);
183  write_reg(mt, MT9F002_MFR_3D5C, 0x4741, 2);
184  write_reg(mt, MT9F002_MFR_3D5E, 0x502F, 2);
185  write_reg(mt, MT9F002_MFR_3D60, 0xBD3A, 2);
186  write_reg(mt, MT9F002_MFR_3D62, 0x5181, 2);
187  write_reg(mt, MT9F002_MFR_3D64, 0x5E73, 2);
188  write_reg(mt, MT9F002_MFR_3D66, 0x7C0A, 2);
189  write_reg(mt, MT9F002_MFR_3D68, 0x7770, 2);
190  write_reg(mt, MT9F002_MFR_3D6A, 0x8085, 2);
191  write_reg(mt, MT9F002_MFR_3D6C, 0x6A82, 2);
192  write_reg(mt, MT9F002_MFR_3D6E, 0x6742, 2);
193  write_reg(mt, MT9F002_MFR_3D70, 0x8244, 2);
194  write_reg(mt, MT9F002_MFR_3D72, 0x831A, 2);
195  write_reg(mt, MT9F002_MFR_3D74, 0x0099, 2);
196  write_reg(mt, MT9F002_MFR_3D76, 0x44DF, 2);
197  write_reg(mt, MT9F002_MFR_3D78, 0x1A00, 2);
198  write_reg(mt, MT9F002_MFR_3D7A, 0x8542, 2);
199  write_reg(mt, MT9F002_MFR_3D7C, 0x8567, 2);
200  write_reg(mt, MT9F002_MFR_3D7E, 0x826A, 2);
201  write_reg(mt, MT9F002_MFR_3D80, 0x857C, 2);
202  write_reg(mt, MT9F002_MFR_3D82, 0x6B80, 2);
203  write_reg(mt, MT9F002_MFR_3D84, 0x7000, 2);
204  write_reg(mt, MT9F002_MFR_3D86, 0xB831, 2);
205  write_reg(mt, MT9F002_MFR_3D88, 0x40BE, 2);
206  write_reg(mt, MT9F002_MFR_3D8A, 0x6700, 2);
207  write_reg(mt, MT9F002_MFR_3D8C, 0x0CBD, 2);
208  write_reg(mt, MT9F002_MFR_3D8E, 0x4482, 2);
209  write_reg(mt, MT9F002_MFR_3D90, 0x7898, 2);
210  write_reg(mt, MT9F002_MFR_3D92, 0x7480, 2);
211  write_reg(mt, MT9F002_MFR_3D94, 0x5680, 2);
212  write_reg(mt, MT9F002_MFR_3D96, 0x9755, 2);
213  write_reg(mt, MT9F002_MFR_3D98, 0x8057, 2);
214  write_reg(mt, MT9F002_MFR_3D9A, 0x8056, 2);
215  write_reg(mt, MT9F002_MFR_3D9C, 0x9256, 2);
216  write_reg(mt, MT9F002_MFR_3D9E, 0x8057, 2);
217  write_reg(mt, MT9F002_MFR_3DA0, 0x8055, 2);
218  write_reg(mt, MT9F002_MFR_3DA2, 0x817C, 2);
219  write_reg(mt, MT9F002_MFR_3DA4, 0x969B, 2);
220  write_reg(mt, MT9F002_MFR_3DA6, 0x56A6, 2);
221  write_reg(mt, MT9F002_MFR_3DA8, 0x44BE, 2);
222  write_reg(mt, MT9F002_MFR_3DAA, 0x000C, 2);
223  write_reg(mt, MT9F002_MFR_3DAC, 0x867A, 2);
224  write_reg(mt, MT9F002_MFR_3DAE, 0x9474, 2);
225  write_reg(mt, MT9F002_MFR_3DB0, 0x8A79, 2);
226  write_reg(mt, MT9F002_MFR_3DB2, 0x9367, 2);
227  write_reg(mt, MT9F002_MFR_3DB4, 0xBF6A, 2);
228  write_reg(mt, MT9F002_MFR_3DB6, 0x816C, 2);
229  write_reg(mt, MT9F002_MFR_3DB8, 0x8570, 2);
230  write_reg(mt, MT9F002_MFR_3DBA, 0x836C, 2);
231  write_reg(mt, MT9F002_MFR_3DBC, 0x826A, 2);
232  write_reg(mt, MT9F002_MFR_3DBE, 0x8245, 2);
233  write_reg(mt, MT9F002_MFR_3DC0, 0xFFFF, 2);
234  write_reg(mt, MT9F002_MFR_3DC2, 0xFFD6, 2);
235  write_reg(mt, MT9F002_MFR_3DC4, 0x4582, 2);
236  write_reg(mt, MT9F002_MFR_3DC6, 0x6A82, 2);
237  write_reg(mt, MT9F002_MFR_3DC8, 0x6C83, 2);
238  write_reg(mt, MT9F002_MFR_3DCA, 0x7000, 2);
239  write_reg(mt, MT9F002_MFR_3DCC, 0x8024, 2);
240  write_reg(mt, MT9F002_MFR_3DCE, 0xB181, 2);
241  write_reg(mt, MT9F002_MFR_3DD0, 0x6859, 2);
242  write_reg(mt, MT9F002_MFR_3DD2, 0x732B, 2);
243  write_reg(mt, MT9F002_MFR_3DD4, 0x4030, 2);
244  write_reg(mt, MT9F002_MFR_3DD6, 0x4982, 2);
245  write_reg(mt, MT9F002_MFR_3DD8, 0x101B, 2);
246  write_reg(mt, MT9F002_MFR_3DDA, 0x4083, 2);
247  write_reg(mt, MT9F002_MFR_3DDC, 0x6785, 2);
248  write_reg(mt, MT9F002_MFR_3DDE, 0x3A00, 2);
249  write_reg(mt, MT9F002_MFR_3DE0, 0x8820, 2);
250  write_reg(mt, MT9F002_MFR_3DE2, 0x0C59, 2);
251  write_reg(mt, MT9F002_MFR_3DE4, 0x8546, 2);
252  write_reg(mt, MT9F002_MFR_3DE6, 0x8348, 2);
253  write_reg(mt, MT9F002_MFR_3DE8, 0xD04C, 2);
254  write_reg(mt, MT9F002_MFR_3DEA, 0x8B48, 2);
255  write_reg(mt, MT9F002_MFR_3DEC, 0x4641, 2);
256  write_reg(mt, MT9F002_MFR_3DEE, 0x4083, 2);
257  write_reg(mt, MT9F002_MFR_3DF0, 0x1A00, 2);
258  write_reg(mt, MT9F002_MFR_3DF2, 0x8347, 2);
259  write_reg(mt, MT9F002_MFR_3DF4, 0x824A, 2);
260  write_reg(mt, MT9F002_MFR_3DF6, 0x9A56, 2);
261  write_reg(mt, MT9F002_MFR_3DF8, 0x1A00, 2);
262  write_reg(mt, MT9F002_MFR_3DFA, 0x951A, 2);
263  write_reg(mt, MT9F002_MFR_3DFC, 0x0056, 2);
264  write_reg(mt, MT9F002_MFR_3DFE, 0x914D, 2);
265  write_reg(mt, MT9F002_MFR_3E00, 0x8B4A, 2);
266  write_reg(mt, MT9F002_MFR_3E02, 0x4700, 2);
267  write_reg(mt, MT9F002_MFR_3E04, 0x0300, 2);
268  write_reg(mt, MT9F002_MFR_3E06, 0x2492, 2);
269  write_reg(mt, MT9F002_MFR_3E08, 0x0024, 2);
270  write_reg(mt, MT9F002_MFR_3E0A, 0x8A1A, 2);
271  write_reg(mt, MT9F002_MFR_3E0C, 0x004F, 2);
272  write_reg(mt, MT9F002_MFR_3E0E, 0xB446, 2);
273  write_reg(mt, MT9F002_MFR_3E10, 0x8349, 2);
274  write_reg(mt, MT9F002_MFR_3E12, 0xB249, 2);
275  write_reg(mt, MT9F002_MFR_3E14, 0x4641, 2);
276  write_reg(mt, MT9F002_MFR_3E16, 0x408B, 2);
277  write_reg(mt, MT9F002_MFR_3E18, 0x4783, 2);
278  write_reg(mt, MT9F002_MFR_3E1A, 0x4BDB, 2);
279  write_reg(mt, MT9F002_MFR_3E1C, 0x4B47, 2);
280  write_reg(mt, MT9F002_MFR_3E1E, 0x4180, 2);
281  write_reg(mt, MT9F002_MFR_3E20, 0x502B, 2);
282  write_reg(mt, MT9F002_MFR_3E22, 0x4C3A, 2);
283  write_reg(mt, MT9F002_MFR_3E24, 0x4180, 2);
284  write_reg(mt, MT9F002_MFR_3E26, 0x737C, 2);
285  write_reg(mt, MT9F002_MFR_3E28, 0xD124, 2);
286  write_reg(mt, MT9F002_MFR_3E2A, 0x9068, 2);
287  write_reg(mt, MT9F002_MFR_3E2C, 0x8A20, 2);
288  write_reg(mt, MT9F002_MFR_3E2E, 0x2170, 2);
289  write_reg(mt, MT9F002_MFR_3E30, 0x8081, 2);
290  write_reg(mt, MT9F002_MFR_3E32, 0x6A67, 2);
291  write_reg(mt, MT9F002_MFR_3E34, 0x4257, 2);
292  write_reg(mt, MT9F002_MFR_3E36, 0x5544, 2);
293  write_reg(mt, MT9F002_MFR_3E38, 0x8644, 2);
294  write_reg(mt, MT9F002_MFR_3E3A, 0x9755, 2);
295  write_reg(mt, MT9F002_MFR_3E3C, 0x5742, 2);
296  write_reg(mt, MT9F002_MFR_3E3E, 0x676A, 2);
297  write_reg(mt, MT9F002_MFR_3E40, 0x807D, 2);
298  write_reg(mt, MT9F002_MFR_3E42, 0x3180, 2);
299  write_reg(mt, MT9F002_MFR_3E44, 0x7000, 2);
300  write_reg(mt, MT9F002_MFR_3E46, 0x0000, 2);
301  write_reg(mt, MT9F002_MFR_3E48, 0x0000, 2);
302  write_reg(mt, MT9F002_MFR_3E4A, 0x0000, 2);
303  write_reg(mt, MT9F002_MFR_3E4C, 0x0000, 2);
304  write_reg(mt, MT9F002_MFR_3E4E, 0x0000, 2);
305  write_reg(mt, MT9F002_MFR_3E50, 0x0000, 2);
306  write_reg(mt, MT9F002_MFR_3E52, 0x0000, 2);
307  write_reg(mt, MT9F002_MFR_3E54, 0x0000, 2);
308  write_reg(mt, MT9F002_MFR_3E56, 0x0000, 2);
309  write_reg(mt, MT9F002_MFR_3E58, 0x0000, 2);
310  write_reg(mt, MT9F002_MFR_3E5A, 0x0000, 2);
311  write_reg(mt, MT9F002_MFR_3E5C, 0x0000, 2);
312  write_reg(mt, MT9F002_MFR_3E5E, 0x0000, 2);
313  write_reg(mt, MT9F002_MFR_3E60, 0x0000, 2);
314  write_reg(mt, MT9F002_MFR_3E62, 0x0000, 2);
315  write_reg(mt, MT9F002_MFR_3E64, 0x0000, 2);
316  write_reg(mt, MT9F002_MFR_3E66, 0x0000, 2);
317  write_reg(mt, MT9F002_MFR_3E68, 0x0000, 2);
318  write_reg(mt, MT9F002_MFR_3E6A, 0x0000, 2);
319  write_reg(mt, MT9F002_MFR_3E6C, 0x0000, 2);
320  write_reg(mt, MT9F002_MFR_3E6E, 0x0000, 2);
321  write_reg(mt, MT9F002_MFR_3E70, 0x0000, 2);
322  write_reg(mt, MT9F002_MFR_3E72, 0x0000, 2);
323  write_reg(mt, MT9F002_MFR_3E74, 0x0000, 2);
324  write_reg(mt, MT9F002_MFR_3E76, 0x0000, 2);
325  write_reg(mt, MT9F002_MFR_3E78, 0x0000, 2);
326  write_reg(mt, MT9F002_MFR_3E7A, 0x0000, 2);
327  write_reg(mt, MT9F002_MFR_3E7C, 0x0000, 2);
328  write_reg(mt, MT9F002_MFR_3E7E, 0x0000, 2);
329  write_reg(mt, MT9F002_MFR_3E80, 0x0000, 2);
330  write_reg(mt, MT9F002_MFR_3E82, 0x0000, 2);
331  write_reg(mt, MT9F002_MFR_3E84, 0x0000, 2);
332  write_reg(mt, MT9F002_MFR_3E86, 0x0000, 2);
333  write_reg(mt, MT9F002_MFR_3E88, 0x0000, 2);
334  write_reg(mt, MT9F002_MFR_3E8A, 0x0000, 2);
335  write_reg(mt, MT9F002_MFR_3E8C, 0x0000, 2);
336  write_reg(mt, MT9F002_MFR_3E8E, 0x0000, 2);
337  write_reg(mt, MT9F002_MFR_3E90, 0x0000, 2);
338  write_reg(mt, MT9F002_MFR_3E92, 0x0000, 2);
339  write_reg(mt, MT9F002_MFR_3E94, 0x0000, 2);
340  write_reg(mt, MT9F002_MFR_3E96, 0x0000, 2);
341  write_reg(mt, MT9F002_MFR_3E98, 0x0000, 2);
342  write_reg(mt, MT9F002_MFR_3E9A, 0x0000, 2);
343  write_reg(mt, MT9F002_MFR_3E9C, 0x0000, 2);
344  write_reg(mt, MT9F002_MFR_3E9E, 0x0000, 2);
345  write_reg(mt, MT9F002_MFR_3EA0, 0x0000, 2);
346  write_reg(mt, MT9F002_MFR_3EA2, 0x0000, 2);
347  write_reg(mt, MT9F002_MFR_3EA4, 0x0000, 2);
348  write_reg(mt, MT9F002_MFR_3EA6, 0x0000, 2);
349  write_reg(mt, MT9F002_MFR_3EA8, 0x0000, 2);
350  write_reg(mt, MT9F002_MFR_3EAA, 0x0000, 2);
351  write_reg(mt, MT9F002_MFR_3EAC, 0x0000, 2);
352  write_reg(mt, MT9F002_MFR_3EAE, 0x0000, 2);
353  write_reg(mt, MT9F002_MFR_3EB0, 0x0000, 2);
354  write_reg(mt, MT9F002_MFR_3EB2, 0x0000, 2);
355  write_reg(mt, MT9F002_MFR_3EB4, 0x0000, 2);
356  write_reg(mt, MT9F002_MFR_3EB6, 0x0000, 2);
357  write_reg(mt, MT9F002_MFR_3EB8, 0x0000, 2);
358  write_reg(mt, MT9F002_MFR_3EBA, 0x0000, 2);
359  write_reg(mt, MT9F002_MFR_3EBC, 0x0000, 2);
360  write_reg(mt, MT9F002_MFR_3EBE, 0x0000, 2);
361  write_reg(mt, MT9F002_MFR_3EC0, 0x0000, 2);
362  write_reg(mt, MT9F002_MFR_3EC2, 0x0000, 2);
363  write_reg(mt, MT9F002_MFR_3EC4, 0x0000, 2);
364  write_reg(mt, MT9F002_MFR_3EC6, 0x0000, 2);
365  write_reg(mt, MT9F002_MFR_3EC8, 0x0000, 2);
366  write_reg(mt, MT9F002_MFR_3ECA, 0x0000, 2);
367  write_reg(mt, MT9F002_MFR_3176, 0x4000, 2);
368  write_reg(mt, MT9F002_MFR_317C, 0xA00A, 2);
369  write_reg(mt, MT9F002_MFR_3EE6, 0x0000, 2);
370  write_reg(mt, MT9F002_MFR_3ED8, 0xE0E0, 2);
371  write_reg(mt, MT9F002_MFR_3EE8, 0x0001, 2);
372  write_reg(mt, MT9F002_SMIA_TEST, 0x0005, 2);
373 }
374 
378 static inline void mt9f002_mipi_stage2(struct mt9f002_t *mt)
379 {
380  write_reg(mt, MT9F002_SMIA_TEST, 0x0045, 2);
381 }
382 
386 static inline void mt9f002_mipi_stage3(struct mt9f002_t *mt)
387 {
388  write_reg(mt, MT9F002_EXTRA_DELAY , 0x0000, 2);
389  write_reg(mt, MT9F002_RESET_REGISTER , 0x0118, 2);
390  write_reg(mt, MT9F002_MFR_3EDC, 0x68CF, 2);
391  write_reg(mt, MT9F002_MFR_3EE2, 0xE363, 2);
392 }
393 
397 static inline void mt9f002_parallel_stage1(struct mt9f002_t *mt)
398 {
399  write_reg(mt, MT9F002_RESET_REGISTER , 0x0010, 2);
400  write_reg(mt, MT9F002_GLOBAL_GAIN , 0x1430, 2);
401  write_reg(mt, MT9F002_RESET_REGISTER , 0x0010, 2);
402  write_reg(mt, MT9F002_RESET_REGISTER , 0x0010, 2);
403  write_reg(mt, MT9F002_RESET_REGISTER , 0x0010, 2);
404  write_reg(mt, MT9F002_DAC_LD_14_15 , 0xE525, 2);
405  write_reg(mt, MT9F002_CTX_CONTROL_REG, 0x0000, 2);
406  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xF873, 2);
407  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x08AA, 2);
408  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x3219, 2);
409  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x3219, 2);
410  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x3219, 2);
411  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x3200, 2);
412  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x3200, 2);
413  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x3200, 2);
414  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x3200, 2);
415  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x3200, 2);
416  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x1769, 2);
417  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xA6F3, 2);
418  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xA6F3, 2);
419  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xA6F3, 2);
420  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xA6F3, 2);
421  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xA6F3, 2);
422  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xA6F3, 2);
423  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xA6F3, 2);
424  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xAFF3, 2);
425  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xFA64, 2);
426  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xFA64, 2);
427  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xFA64, 2);
428  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xF164, 2);
429  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xFA64, 2);
430  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xFA64, 2);
431  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xFA64, 2);
432  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xF164, 2);
433  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x276E, 2);
434  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x18CF, 2);
435  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x18CF, 2);
436  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x18CF, 2);
437  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x28CF, 2);
438  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x18CF, 2);
439  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x18CF, 2);
440  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x18CF, 2);
441  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x18CF, 2);
442  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x2363, 2);
443  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x2363, 2);
444  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x2352, 2);
445  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x2363, 2);
446  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x2363, 2);
447  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x2363, 2);
448  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x2352, 2);
449  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x2352, 2);
450  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xA394, 2);
451  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xA394, 2);
452  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x8F8F, 2);
453  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xA3D4, 2);
454  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xA394, 2);
455  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xA394, 2);
456  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x8F8F, 2);
457  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x8FCF, 2);
458  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xDC23, 2);
459  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xDC63, 2);
460  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xDC63, 2);
461  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xDC23, 2);
462  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xDC23, 2);
463  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xDC63, 2);
464  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xDC63, 2);
465  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0xDC23, 2);
466  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x0F73, 2);
467  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x85C0, 2);
468  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x85C0, 2);
469  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x85C0, 2);
470  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x85C0, 2);
471  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x85C0, 2);
472  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x85C0, 2);
473  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x85C0, 2);
474  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x85C4, 2);
475  write_reg(mt, MT9F002_CTX_WR_DATA_REG, 0x0000, 2);
476  write_reg(mt, MT9F002_ANALOG_CONTROL4, 0x8000, 2);
477  write_reg(mt, MT9F002_DAC_LD_14_15 , 0xE525, 2);
478  write_reg(mt, MT9F002_DATA_PEDESTAL_ , 0x00A8, 2);
479  write_reg(mt, MT9F002_RESET_REGISTER , 0x0090, 2);
480  write_reg(mt, MT9F002_SERIAL_FORMAT , 0x0301, 2);
481  write_reg(mt, MT9F002_RESET_REGISTER , 0x1090, 2);
482  write_reg(mt, MT9F002_SMIA_TEST , 0x0845, 2);
483  write_reg(mt, MT9F002_RESET_REGISTER , 0x1080, 2);
484  write_reg(mt, MT9F002_DATAPATH_SELECT, 0xD880, 2);
485  write_reg(mt, MT9F002_RESET_REGISTER , 0x9080, 2);
486  write_reg(mt, MT9F002_DATAPATH_SELECT, 0xD880, 2);
487  write_reg(mt, MT9F002_RESET_REGISTER , 0x10C8, 2);
488  write_reg(mt, MT9F002_DATAPATH_SELECT, 0xD880, 2);
489 }
490 
494 static inline void mt9f002_parallel_stage2(struct mt9f002_t *mt)
495 {
496  write_reg(mt, MT9F002_ANALOG_CONTROL4, 0x8000, 2);
497  write_reg(mt, MT9F002_READ_MODE, 0x0041, 2);
498 
499  write_reg(mt, MT9F002_READ_MODE , 0x04C3, 2);
500  write_reg(mt, MT9F002_READ_MODE , 0x04C3, 2);
501  write_reg(mt, MT9F002_ANALOG_CONTROL5 , 0x0000, 2);
502  write_reg(mt, MT9F002_ANALOG_CONTROL5 , 0x0000, 2);
503  write_reg(mt, MT9F002_ANALOG_CONTROL5 , 0x0000, 2);
504  write_reg(mt, MT9F002_ANALOG_CONTROL5 , 0x0000, 2);
505  write_reg(mt, MT9F002_DAC_LD_28_29 , 0x0047, 2);
506  write_reg(mt, MT9F002_COLUMN_CORRECTION , 0xB080, 2);
507  write_reg(mt, MT9F002_COLUMN_CORRECTION , 0xB100, 2);
508  write_reg(mt, MT9F002_DARK_CONTROL3 , 0x0020, 2);
509  write_reg(mt, MT9F002_DAC_LD_24_25 , 0x6349, 2);
510  write_reg(mt, MT9F002_ANALOG_CONTROL7 , 0x800A, 2);
511  write_reg(mt, MT9F002_RESET_REGISTER , 0x90C8, 2);
512  write_reg(mt, MT9F002_CTX_CONTROL_REG , 0x8005, 2);
513  write_reg(mt, MT9F002_ANALOG_CONTROL7 , 0x800A, 2);
514  write_reg(mt, MT9F002_DAC_LD_28_29 , 0x0047, 2);
515  write_reg(mt, MT9F002_DAC_LD_30_31 , 0x15F0, 2);
516  write_reg(mt, MT9F002_DAC_LD_30_31 , 0x15F0, 2);
517  write_reg(mt, MT9F002_DAC_LD_30_31 , 0x15F0, 2);
518  write_reg(mt, MT9F002_DAC_LD_28_29 , 0x0047, 2);
519  write_reg(mt, MT9F002_DAC_LD_28_29 , 0x0047, 2);
520  write_reg(mt, MT9F002_RESET_REGISTER , 0x10C8, 2);
521  //write_reg(mt, MT9F002_RESET_REGISTER , 0x14C8, 2); // reset bad frame
522  write_reg(mt, MT9F002_COARSE_INTEGRATION_TIME, 0x08C3, 2);
523  write_reg(mt, MT9F002_DIGITAL_TEST , 0x0000, 2);
524  //write_reg(mt, MT9F002_DATAPATH_SELECT , 0xd881, 2); // permanent line valid
525  write_reg(mt, MT9F002_DATAPATH_SELECT , 0xd880, 2);
526  write_reg(mt, MT9F002_READ_MODE , 0x0041, 2);
527  write_reg(mt, MT9F002_X_ODD_INC , 0x0001, 2);
528  write_reg(mt, MT9F002_Y_ODD_INC , 0x0001, 2);
529  write_reg(mt, MT9F002_MASK_CORRUPTED_FRAMES , 0x0001, 1); // 0 output corrupted frame, 1 mask them
530 }
531 
535 static inline void mt9f002_set_pll(struct mt9f002_t *mt)
536 {
537  // Update registers
538  write_reg(mt, MT9F002_VT_PIX_CLK_DIV , mt->vt_pix_clk_div, 2);
539  write_reg(mt, MT9F002_VT_SYS_CLK_DIV , mt->vt_sys_clk_div, 2);
540  write_reg(mt, MT9F002_PRE_PLL_CLK_DIV, mt->pre_pll_clk_div, 2);
541  write_reg(mt, MT9F002_PLL_MULTIPLIER , mt->pll_multiplier, 2);
542  write_reg(mt, MT9F002_OP_PIX_CLK_DIV , mt->op_pix_clk_div, 2);
543  write_reg(mt, MT9F002_OP_SYS_CLK_DIV , mt->op_sys_clk_div, 2);
544 
545  uint16_t smia = read_reg(mt, MT9F002_SMIA_TEST, 2);
546  write_reg(mt, MT9F002_SMIA_TEST, (smia & 0xFFBF) | (mt->shift_vt_pix_clk_div<<6), 2); // shift_vt_pix_clk_div
547 
548  uint16_t row_speed = read_reg(mt, MT9F002_ROW_SPEED, 2);
549  row_speed = (row_speed & 0xFFF8) | (mt->rowSpeed_2_0 & 0x07); // rowSpeed_2_0
550  row_speed = (row_speed & 0xF8FF) | ((mt->row_speed_10_8 & 0x07)<<8); // row_speed_10_8
551  row_speed = (row_speed&(~0x70)) | (0x2<<4); // Change opclk_delay
552  write_reg(mt, MT9F002_ROW_SPEED, row_speed, 2);
553 
554  // Compute clocks
555  mt->vt_pix_clk = mt->input_clk_freq * (float)mt->pll_multiplier * (float)(1+mt->shift_vt_pix_clk_div)
556  /((float)mt->pre_pll_clk_div * (float)mt->vt_sys_clk_div * (float)mt->vt_pix_clk_div);
557  mt->op_pix_clk = mt->input_clk_freq * (float)mt->pll_multiplier
558  /((float)mt->pre_pll_clk_div * (float)mt->op_sys_clk_div * (float)mt->op_pix_clk_div);
559 }
560 
565 static void mt9f002_set_blanking(struct mt9f002_t *mt)
566 {
567  /* Read some config values in order to calculate blanking configuration */
568  uint16_t min_line_blanking_pck = read_reg(mt, MT9F002_MIN_LINE_BLANKING_PCK, 2);
569  uint16_t x_odd_inc = read_reg(mt, MT9F002_X_ODD_INC, 2);
570  uint16_t min_frame_blanking_lines = read_reg(mt, MT9F002_MIN_FRAME_BLANKING_LINES, 2);
571  uint16_t min_line_length_pck = read_reg(mt, MT9F002_MIN_LINE_LENGTH_PCK, 2);
572 
573  /* Calculate minimum line length */
574  float subsampling_factor = (float)(1 + x_odd_inc) / 2.0f; // See page 52
575  uint16_t min_line_length = MAX(min_line_length_pck, mt->scaled_width/subsampling_factor + min_line_blanking_pck); // EQ 9
576  min_line_length = MAX(min_line_length, (mt->scaled_width-1 + x_odd_inc) / subsampling_factor/2 + min_line_blanking_pck);
577  if (mt->interface == MT9F002_MIPI ||
578  mt->interface == MT9F002_HiSPi) {
579  min_line_length = MAX(min_line_length, ((uint16_t)((float)mt->scaled_width * mt->vt_pix_clk / mt->op_pix_clk)/2) + 0x005E); // 2 lanes, pll clocks
580  }
581  else {
582  min_line_length = MAX(min_line_length, ((uint16_t)((float)mt->scaled_width * mt->vt_pix_clk / mt->op_pix_clk)) + 0x005E); // pll clocks
583  }
584 
585  /* Do some magic to get it to work with P7 ISP (with horizontal blanking) */
586  uint32_t clkRatio_num = mt->op_sys_clk_div * mt->op_pix_clk_div * mt->row_speed_10_8 * (1 + mt->shift_vt_pix_clk_div);
587  uint32_t clkRatio_den = mt->vt_sys_clk_div * mt->vt_pix_clk_div;
588 
589  /* Divide by the GCD to find smallest ratio */
590  uint32_t clkRatio_gcd = int32_gcd(clkRatio_num, clkRatio_den);
591  clkRatio_num = clkRatio_num / clkRatio_gcd;
592  clkRatio_den = clkRatio_den / clkRatio_gcd;
593 
594  /* Calculate minimum horizontal blanking, since fpga line_length must be divideable by 2 */
595  uint32_t min_horizontal_blanking = clkRatio_num;
596  if((clkRatio_den % 2) != 0) {
597  min_horizontal_blanking = 2 * clkRatio_num;
598  }
599 
600  /* Fix fpga correction based on min horizontal blanking */
601  if ((min_line_length % min_horizontal_blanking) != 0) {
602  min_line_length += min_horizontal_blanking - (min_line_length % min_horizontal_blanking);
603  }
604 
605  /* Calculate minimum frame length lines */
606  uint16_t min_frame_length = (mt->scaled_height) / subsampling_factor + min_frame_blanking_lines; // (EQ 10)
607 
608  /* Calculate FPS we get using these minimums (Maximum FPS) */
609  mt->line_length = min_line_length;
610  mt->frame_length = min_frame_length;
611  mt->real_fps = mt->vt_pix_clk * 1000000 / (float)(mt->line_length * mt->frame_length);
612 
613  /* Check if we need to downscale the FPS and bruteforce better solution */
614  if(mt->target_fps < mt->real_fps) {
615  float min_fps_err = fabs(mt->target_fps - mt->real_fps);
616  float new_fps = mt->real_fps;
617 
618  // Go through all possible line lengths
619  for(uint16_t ll = min_line_length; ll <= MT9F002_LINE_LENGTH_MAX; ll += min_horizontal_blanking) {
620  // Go through all possible frame lengths
621  for(uint16_t fl = min_frame_length; fl < MT9F002_FRAME_LENGTH_MAX; ++fl) {
622  new_fps = mt->vt_pix_clk * 1000000 / (float)(ll * fl);
623 
624  // Calculate FPS error and save if it is better
625  float fps_err = fabs(mt->target_fps - new_fps);
626  if(fps_err < min_fps_err) {
627  min_fps_err = fps_err;
628  mt->line_length = ll;
629  mt->frame_length = fl;
630  mt->real_fps = new_fps;
631  }
632 
633  // Stop searching if FPS is lower or equal
634  if(mt->target_fps > new_fps) {
635  break;
636  }
637  }
638 
639  // Calculate if next step is still needed (since we only need to go one step below target_fps)
640  new_fps = mt->vt_pix_clk * 1000000 / (float)(ll * min_frame_length);
641 
642  // Stop searching if FPS is lower or equal
643  if(mt->target_fps > new_fps) {
644  break;
645  }
646  }
647  }
648 
649  /* Actually set the calculated values */
650  write_reg(mt, MT9F002_LINE_LENGTH_PCK, mt->line_length, 2);
651  write_reg(mt, MT9F002_FRAME_LENGTH_LINES, mt->frame_length, 2);
652 }
653 
658 static void mt9f002_set_exposure(struct mt9f002_t *mt)
659 {
660  /* Fetch minimum and maximum integration times */
661  uint16_t coarse_integration_min = read_reg(mt, MT9F002_COARSE_INTEGRATION_TIME_MIN, 2);
662  uint16_t coarse_integration_max = mt->frame_length - read_reg(mt, MT9F002_COARSE_INTEGRATION_TIME_MAX_MARGIN, 2);
663  uint16_t fine_integration_min = read_reg(mt, MT9F002_FINE_INTEGRATION_TIME_MIN, 2);
664  uint16_t fine_integration_max = mt->line_length - read_reg(mt, MT9F002_FINE_INTEGRATION_TIME_MAX_MARGIN, 2);
665 
666  /* Compute fine and coarse integration time */
667  uint32_t integration = mt->target_exposure * mt->vt_pix_clk * 1000;
668  uint16_t coarse_integration = integration / mt->line_length;
669  uint16_t fine_integration = integration % mt->line_length;
670 
671  /* Make sure fine integration is inside bounds */
672  if(fine_integration_min > fine_integration || fine_integration > fine_integration_max)
673  {
674  int32_t upper_coarse_integration = coarse_integration + 1;
675  int32_t upper_fine_integration = fine_integration_min;
676 
677  int32_t lower_coarse_integration = coarse_integration - 1;
678  int32_t lower_fine_integration = fine_integration_max;
679 
680  // Check if lower case is invalid (take upper coarse)
681  if(lower_coarse_integration < coarse_integration_min) {
682  coarse_integration = upper_coarse_integration;
683  fine_integration = upper_fine_integration;
684  }
685  // Check if upper case is invalid (take lower coarse)
686  else if(upper_coarse_integration > coarse_integration_max) {
687  coarse_integration = lower_coarse_integration;
688  fine_integration = lower_fine_integration;
689  }
690  // Both are good
691  else {
692  // Calculate error to decide which is better
693  int32_t upper_error = abs((mt->line_length * upper_coarse_integration + upper_fine_integration) - integration);
694  int32_t lower_error = abs((mt->line_length * lower_coarse_integration + lower_fine_integration) - integration);
695 
696  if(upper_error < lower_error) {
697  coarse_integration = upper_coarse_integration;
698  fine_integration = upper_fine_integration;
699  }
700  else {
701  coarse_integration = lower_coarse_integration;
702  fine_integration = lower_fine_integration;
703  }
704  }
705  }
706 
707  /* Fix saturations */
708  Bound(fine_integration, fine_integration_min, fine_integration_max);
709  Bound(coarse_integration, coarse_integration_min, coarse_integration_max);
710 
711  /* Set the registers */
712  mt->real_exposure = (float)(coarse_integration * mt->line_length + fine_integration) / (mt->vt_pix_clk * 1000);
713  write_reg(mt, MT9F002_COARSE_INTEGRATION_TIME, coarse_integration, 2);
714  write_reg(mt, MT9F002_FINE_INTEGRATION_TIME_, fine_integration, 2);
715 }
716 
720 static uint16_t mt9f002_calc_gain(float gain) {
721  // Check if gain is valid
722  if(gain < 1.0) {
723  gain = 1.0;
724  }
725 
726  // Calculation of colamp, analg3 and digital gain based on table 19 p56
727  uint8_t colamp_gain, analog_gain3, digital_gain;
728  if (gain < 1.50)
729  {
730  // This is not recommended
731  colamp_gain = 0;
732  analog_gain3 = 0;
733  digital_gain = 1;
734  }
735  else if (gain < 3.0)
736  {
737  colamp_gain = 1;
738  analog_gain3 = 0;
739  digital_gain = 1;
740  }
741  else if (gain < 6.0)
742  {
743  colamp_gain = 2;
744  analog_gain3 = 0;
745  digital_gain = 1;
746  }
747  else if (gain < 16.0)
748  {
749  colamp_gain = 3;
750  analog_gain3 = 0;
751  digital_gain = 1;
752  }
753  else if (gain < 32.0)
754  {
755  colamp_gain = 3;
756  analog_gain3 = 0;
757  digital_gain = 2;
758  }
759  else
760  {
761  colamp_gain = 3;
762  analog_gain3 = 0;
763  digital_gain = 4;
764  }
765 
766  // Calculate gain 2 (fine gain)
767  uint16_t analog_gain2 = gain / (float)digital_gain / (float)(1<<colamp_gain) / (float)(1<<analog_gain3) * 64.0;
768  Bound(analog_gain2, 1, 127);
769 
770  return (analog_gain2 & 0x7F) | ((analog_gain3 & 0x7) << 7) | ((colamp_gain & 0x3) << 10) | ((digital_gain & 0xF) << 12);
771 }
772 
776 static void mt9f002_set_gains(struct mt9f002_t *mt)
777 {
778  write_reg(mt, MT9F002_GREEN1_GAIN, mt9f002_calc_gain(mt->gain_green1), 2);
779  write_reg(mt, MT9F002_BLUE_GAIN, mt9f002_calc_gain(mt->gain_blue), 2);
780  write_reg(mt, MT9F002_RED_GAIN, mt9f002_calc_gain(mt->gain_red), 2);
781  write_reg(mt, MT9F002_GREEN2_GAIN, mt9f002_calc_gain(mt->gain_green2), 2);
782 }
783 
788 void mt9f002_init(struct mt9f002_t *mt)
789 {
790  /* Reset the device */
791  //TODO???
792 
793  /* Setup i2c transaction */
794  mt->i2c_trans.status = I2CTransDone;
795 
796  /* Software reset */
797  write_reg(mt, MT9F002_SOFTWARE_RESET, 0x1, 1);
798  usleep(1000000); // Wait for one second
799 
800  /* Based on the interface configure stage 1 */
801  if(mt->interface == MT9F002_MIPI || mt->interface == MT9F002_HiSPi) {
802  mt9f002_mipi_stage1(mt);
803  }
804  else {
805  mt9f002_parallel_stage1(mt);
806  }
807 
808  /* Set the PLL based on Input clock and wanted clock frequency */
809  mt9f002_set_pll(mt);
810 
811  /* Based on the interface configure stage 2 */
812  if(mt->interface == MT9F002_MIPI || mt->interface == MT9F002_HiSPi) {
813  mt9f002_mipi_stage2(mt);
814  }
815  else {
816  mt9f002_parallel_stage2(mt);
817  }
818 
819  /* Set output resolution */
820  write_reg(mt, MT9F002_X_OUTPUT_SIZE, mt->output_width, 2);
821  write_reg(mt, MT9F002_Y_OUTPUT_SIZE, mt->output_height, 2);
822 
823  /* Set scaling */
824  uint16_t scaleFactor = ceil((float)MT9F002_SCALER_N / mt->output_scaler);
825  mt->output_scaler = (float)MT9F002_SCALER_N / scaleFactor;
826  mt->scaled_width = ceil((float)mt->output_width / mt->output_scaler);
827  mt->scaled_height = ceil((float)mt->output_height / mt->output_scaler);
828  if (mt->output_scaler != 1.0)
829  {
830  write_reg(mt, MT9F002_SCALING_MODE, 2, 2); // Vertical and horizontal scaling
831  write_reg(mt, MT9F002_SCALE_M, scaleFactor, 2);
832  }
833 
834  /* Set position (based on offset) */
835  write_reg(mt, MT9F002_X_ADDR_START, mt->offset_x , 2);
836  write_reg(mt, MT9F002_X_ADDR_END , mt->offset_x + mt->scaled_width - 1, 2);
837  write_reg(mt, MT9F002_Y_ADDR_START, mt->offset_y, 2);
838  write_reg(mt, MT9F002_Y_ADDR_END , mt->offset_y + mt->scaled_height - 1, 2);
839 
840  /* Update blanking (based on FPS) */
841  mt9f002_set_blanking(mt);
842 
843  /* Update exposure (based on target_exposure) */
844  mt9f002_set_exposure(mt);
845 
846  /* Update gains for the different pixel colors */
847  mt9f002_set_gains(mt);
848 
849  /* Based on the interface configure stage 3 */
850  if(mt->interface == MT9F002_MIPI || mt->interface == MT9F002_HiSPi) {
851  mt9f002_mipi_stage3(mt);
852  }
853 
854  /* Turn the stream on */
855  write_reg(mt, MT9F002_MODE_SELECT, 0x01, 1);
856 }
MT9F002_DAC_LD_30_31
#define MT9F002_DAC_LD_30_31
Definition: mt9f002_regs.h:622
MT9F002_MFR_3E16
#define MT9F002_MFR_3E16
Definition: mt9f002_regs.h:521
MT9F002_MFR_3E04
#define MT9F002_MFR_3E04
Definition: mt9f002_regs.h:512
mt9f002_set_exposure
static void mt9f002_set_exposure(struct mt9f002_t *mt)
Set the exposure configuration Depends on the blanking (and therefore the FPS)
Definition: mt9f002.c:658
MT9F002_MFR_3E3E
#define MT9F002_MFR_3E3E
Definition: mt9f002_regs.h:541
mt9f002_parallel_stage2
static void mt9f002_parallel_stage2(struct mt9f002_t *mt)
Configure stage 2 for parallel connection.
Definition: mt9f002.c:494
MT9F002_SOFTWARE_RESET
#define MT9F002_SOFTWARE_RESET
Definition: mt9f002_regs.h:54
uint16_t
unsigned short uint16_t
Definition: types.h:16
MT9F002_MFR_3D88
#define MT9F002_MFR_3D88
Definition: mt9f002_regs.h:450
MT9F002_MFR_3E4A
#define MT9F002_MFR_3E4A
Definition: mt9f002_regs.h:547
MT9F002_MFR_3E26
#define MT9F002_MFR_3E26
Definition: mt9f002_regs.h:529
MT9F002_MFR_3E8A
#define MT9F002_MFR_3E8A
Definition: mt9f002_regs.h:579
MT9F002_MFR_317C
#define MT9F002_MFR_317C
Definition: mt9f002_regs.h:613
MT9F002_MFR_3E32
#define MT9F002_MFR_3E32
Definition: mt9f002_regs.h:535
MT9F002_MFR_3D3A
#define MT9F002_MFR_3D3A
Definition: mt9f002_regs.h:411
MT9F002_MFR_3E8C
#define MT9F002_MFR_3E8C
Definition: mt9f002_regs.h:580
MT9F002_FINE_INTEGRATION_TIME_MIN
#define MT9F002_FINE_INTEGRATION_TIME_MIN
Definition: mt9f002_regs.h:107
MT9F002_MFR_3D32
#define MT9F002_MFR_3D32
Definition: mt9f002_regs.h:407
MT9F002_X_ADDR_END
#define MT9F002_X_ADDR_END
Definition: mt9f002_regs.h:82
MT9F002_MFR_3D14
#define MT9F002_MFR_3D14
Definition: mt9f002_regs.h:392
MT9F002_MFR_3E66
#define MT9F002_MFR_3E66
Definition: mt9f002_regs.h:561
MT9F002_MFR_3DC8
#define MT9F002_MFR_3DC8
Definition: mt9f002_regs.h:482
MT9F002_MFR_3E0E
#define MT9F002_MFR_3E0E
Definition: mt9f002_regs.h:517
MT9F002_MFR_3EC4
#define MT9F002_MFR_3EC4
Definition: mt9f002_regs.h:608
MT9F002_MFR_3E94
#define MT9F002_MFR_3E94
Definition: mt9f002_regs.h:584
MT9F002_MFR_3D7C
#define MT9F002_MFR_3D7C
Definition: mt9f002_regs.h:444
MT9F002_FINE_INTEGRATION_TIME_
#define MT9F002_FINE_INTEGRATION_TIME_
Definition: mt9f002_regs.h:177
MT9F002_MFR_3E7C
#define MT9F002_MFR_3E7C
Definition: mt9f002_regs.h:572
MT9F002_MFR_3E8E
#define MT9F002_MFR_3E8E
Definition: mt9f002_regs.h:581
MT9F002_MFR_3E1C
#define MT9F002_MFR_3E1C
Definition: mt9f002_regs.h:524
MT9F002_MFR_3DC4
#define MT9F002_MFR_3DC4
Definition: mt9f002_regs.h:480
i2c_transaction::buf
volatile uint8_t buf[I2C_BUF_LEN]
Transaction buffer With I2C_BUF_LEN number of bytes.
Definition: i2c.h:122
MT9F002_MFR_3EB4
#define MT9F002_MFR_3EB4
Definition: mt9f002_regs.h:600
MT9F002_LINE_LENGTH_PCK
#define MT9F002_LINE_LENGTH_PCK
Definition: mt9f002_regs.h:79
MT9F002_MFR_3EBC
#define MT9F002_MFR_3EBC
Definition: mt9f002_regs.h:604
MT9F002_MASK_CORRUPTED_FRAMES
#define MT9F002_MASK_CORRUPTED_FRAMES
Definition: mt9f002_regs.h:56
MT9F002_MFR_3E46
#define MT9F002_MFR_3E46
Definition: mt9f002_regs.h:545
MT9F002_CTX_WR_DATA_REG
#define MT9F002_CTX_WR_DATA_REG
Definition: mt9f002_regs.h:235
MT9F002_MFR_3EAE
#define MT9F002_MFR_3EAE
Definition: mt9f002_regs.h:597
MT9F002_MFR_3E6A
#define MT9F002_MFR_3E6A
Definition: mt9f002_regs.h:563
MT9F002_MIN_FRAME_BLANKING_LINES
#define MT9F002_MIN_FRAME_BLANKING_LINES
Definition: mt9f002_regs.h:136
MT9F002_MFR_3E4C
#define MT9F002_MFR_3E4C
Definition: mt9f002_regs.h:548
mt9f002_t::output_height
uint16_t output_height
Output height.
Definition: mt9f002.h:69
MT9F002_LINE_LENGTH_MAX
#define MT9F002_LINE_LENGTH_MAX
Definition: mt9f002_regs.h:7
mt9f002_t::op_sys_clk_div
uint16_t op_sys_clk_div
Fixed PLL config from calculator tool.
Definition: mt9f002.h:49
MT9F002_MFR_3D86
#define MT9F002_MFR_3D86
Definition: mt9f002_regs.h:449
video_config_t::output_size
struct img_size_t output_size
Output image size.
Definition: video_device.h:45
MT9F002_TARGET_FPS
#define MT9F002_TARGET_FPS
Definition: bebop.h:79
mt9f002_t::rowSpeed_2_0
uint8_t rowSpeed_2_0
Fixed PLL config from calculator tool.
Definition: mt9f002.h:51
MT9F002_MFR_3DF8
#define MT9F002_MFR_3DF8
Definition: mt9f002_regs.h:506
MT9F002_MFR_3EB8
#define MT9F002_MFR_3EB8
Definition: mt9f002_regs.h:602
MT9F002_MFR_3D20
#define MT9F002_MFR_3D20
Definition: mt9f002_regs.h:398
MT9F002_MFR_3DB8
#define MT9F002_MFR_3DB8
Definition: mt9f002_regs.h:474
mt9f002_t::vt_pix_clk_div
uint16_t vt_pix_clk_div
Fixed PLL config from calculator tool.
Definition: mt9f002.h:44
MT9F002_MFR_3D46
#define MT9F002_MFR_3D46
Definition: mt9f002_regs.h:417
MT9F002_MFR_3DDA
#define MT9F002_MFR_3DDA
Definition: mt9f002_regs.h:491
MT9F002_MFR_3DCC
#define MT9F002_MFR_3DCC
Definition: mt9f002_regs.h:484
MT9F002_MFR_3D18
#define MT9F002_MFR_3D18
Definition: mt9f002_regs.h:394
MT9F002_MFR_3D2C
#define MT9F002_MFR_3D2C
Definition: mt9f002_regs.h:404
MT9F002_DAC_LD_14_15
#define MT9F002_DAC_LD_14_15
Definition: mt9f002_regs.h:619
MT9F002_MFR_3E7A
#define MT9F002_MFR_3E7A
Definition: mt9f002_regs.h:571
MT9F002_MFR_3E72
#define MT9F002_MFR_3E72
Definition: mt9f002_regs.h:567
MT9F002_MFR_3DB0
#define MT9F002_MFR_3DB0
Definition: mt9f002_regs.h:470
MT9F002_MFR_3D7A
#define MT9F002_MFR_3D7A
Definition: mt9f002_regs.h:443
MT9F002_MFR_3D6A
#define MT9F002_MFR_3D6A
Definition: mt9f002_regs.h:435
mt9f002_t::pll_multiplier
uint16_t pll_multiplier
Fixed PLL config from calculator tool.
Definition: mt9f002.h:47
MT9F002_SCALING_MODE
#define MT9F002_SCALING_MODE
Definition: mt9f002_regs.h:90
MT9F002_MFR_3D9A
#define MT9F002_MFR_3D9A
Definition: mt9f002_regs.h:459
MT9F002_MFR_3D38
#define MT9F002_MFR_3D38
Definition: mt9f002_regs.h:410
MT9F002_MFR_3EE6
#define MT9F002_MFR_3EE6
Definition: mt9f002_regs.h:614
mt9f002_t::scaled_width
uint16_t scaled_width
Width after corrected scaling.
Definition: mt9f002.h:71
mt9f002_mipi_stage1
static void mt9f002_mipi_stage1(struct mt9f002_t *mt)
Configure stage 1 for both MiPi and HiSPi connection.
Definition: mt9f002.c:121
MT9F002_MFR_3DDE
#define MT9F002_MFR_3DDE
Definition: mt9f002_regs.h:493
MT9F002_MFR_3E3C
#define MT9F002_MFR_3E3C
Definition: mt9f002_regs.h:540
MT9F002_MFR_3DD6
#define MT9F002_MFR_3DD6
Definition: mt9f002_regs.h:489
MT9F002_FINE_INTEGRATION_TIME_MAX_MARGIN
#define MT9F002_FINE_INTEGRATION_TIME_MAX_MARGIN
Definition: mt9f002_regs.h:108
MT9F002_BLUE_GAIN
#define MT9F002_BLUE_GAIN
Definition: mt9f002_regs.h:205
MT9F002_MFR_3DA0
#define MT9F002_MFR_3DA0
Definition: mt9f002_regs.h:462
MT9F002_X_ODD_INC
#define MT9F002_X_ODD_INC
Definition: mt9f002_regs.h:87
MT9F002_MFR_3D64
#define MT9F002_MFR_3D64
Definition: mt9f002_regs.h:432
MT9F002_MFR_3D60
#define MT9F002_MFR_3D60
Definition: mt9f002_regs.h:430
MT9F002_MFR_3D4E
#define MT9F002_MFR_3D4E
Definition: mt9f002_regs.h:421
MT9F002_MFR_3DAE
#define MT9F002_MFR_3DAE
Definition: mt9f002_regs.h:469
MT9F002_MFR_3E28
#define MT9F002_MFR_3E28
Definition: mt9f002_regs.h:530
MT9F002_MFR_3E48
#define MT9F002_MFR_3E48
Definition: mt9f002_regs.h:546
MT9F002_MFR_3E38
#define MT9F002_MFR_3E38
Definition: mt9f002_regs.h:538
MT9F002_ADDRESS
#define MT9F002_ADDRESS
Definition: mt9f002_regs.h:4
MT9F002_MFR_3D96
#define MT9F002_MFR_3D96
Definition: mt9f002_regs.h:457
MT9F002_MFR_3E6C
#define MT9F002_MFR_3E6C
Definition: mt9f002_regs.h:564
MT9F002_OUTPUT_WIDTH
#define MT9F002_OUTPUT_WIDTH
Definition: bebop.h:36
MT9F002_COARSE_INTEGRATION_TIME_MIN
#define MT9F002_COARSE_INTEGRATION_TIME_MIN
Definition: mt9f002_regs.h:105
MT9F002_DIGITAL_TEST
#define MT9F002_DIGITAL_TEST
Definition: mt9f002_regs.h:226
MT9F002_MFR_3D24
#define MT9F002_MFR_3D24
Definition: mt9f002_regs.h:400
MT9F002_MFR_3DC0
#define MT9F002_MFR_3DC0
Definition: mt9f002_regs.h:478
MT9F002_ANALOG_CONTROL4
#define MT9F002_ANALOG_CONTROL4
Definition: mt9f002_regs.h:248
MT9F002_MFR_3E9C
#define MT9F002_MFR_3E9C
Definition: mt9f002_regs.h:588
MT9F002_DAC_LD_28_29
#define MT9F002_DAC_LD_28_29
Definition: mt9f002_regs.h:621
MT9F002_MFR_3E86
#define MT9F002_MFR_3E86
Definition: mt9f002_regs.h:577
read_reg
static uint32_t read_reg(struct mt9f002_t *mt, uint16_t addr, uint8_t len)
Read multiple bytes from a register.
Definition: mt9f002.c:102
mt9f002_t::gain_blue
float gain_blue
Gain for the Blue pixels [1.5 -> 63.50].
Definition: mt9f002.h:64
MT9F002_READ_MODE
#define MT9F002_READ_MODE
Definition: mt9f002_regs.h:201
MT9F002_CTX_CONTROL_REG
#define MT9F002_CTX_CONTROL_REG
Definition: mt9f002_regs.h:234
MT9F002_MFR_3D7E
#define MT9F002_MFR_3D7E
Definition: mt9f002_regs.h:445
MT9F002_MFR_3EE2
#define MT9F002_MFR_3EE2
Definition: mt9f002_regs.h:617
MT9F002_MFR_3D1A
#define MT9F002_MFR_3D1A
Definition: mt9f002_regs.h:395
MT9F002_MFR_3E5A
#define MT9F002_MFR_3E5A
Definition: mt9f002_regs.h:555
MT9F002_MFR_3E92
#define MT9F002_MFR_3E92
Definition: mt9f002_regs.h:583
MT9F002_MFR_3DF4
#define MT9F002_MFR_3DF4
Definition: mt9f002_regs.h:504
MT9F002_VT_PIX_CLK_DIV
#define MT9F002_VT_PIX_CLK_DIV
Definition: mt9f002_regs.h:72
mt9f002_t::offset_x
uint16_t offset_x
Offset from left in pixels.
Definition: mt9f002.h:73
MT9F002_MFR_3D1C
#define MT9F002_MFR_3D1C
Definition: mt9f002_regs.h:396
MT9F002_MFR_3DAC
#define MT9F002_MFR_3DAC
Definition: mt9f002_regs.h:468
MT9F002_MFR_3DD4
#define MT9F002_MFR_3DD4
Definition: mt9f002_regs.h:488
MT9F002_MFR_3E5E
#define MT9F002_MFR_3E5E
Definition: mt9f002_regs.h:557
MT9F002_MFR_3EBA
#define MT9F002_MFR_3EBA
Definition: mt9f002_regs.h:603
MT9F002_HiSPi
HiSPi type connection.
Definition: mt9f002.h:36
MT9F002_MFR_3DA6
#define MT9F002_MFR_3DA6
Definition: mt9f002_regs.h:465
MT9F002_MFR_3D44
#define MT9F002_MFR_3D44
Definition: mt9f002_regs.h:416
MT9F002_MFR_3E2C
#define MT9F002_MFR_3E2C
Definition: mt9f002_regs.h:532
MT9F002_MFR_3E40
#define MT9F002_MFR_3E40
Definition: mt9f002_regs.h:542
mt9f002_t::vt_sys_clk_div
uint16_t vt_sys_clk_div
Fixed PLL config from calculator tool.
Definition: mt9f002.h:45
MT9F002_MFR_3E62
#define MT9F002_MFR_3E62
Definition: mt9f002_regs.h:559
MT9F002_MFR_3E34
#define MT9F002_MFR_3E34
Definition: mt9f002_regs.h:536
MT9F002_MFR_3E54
#define MT9F002_MFR_3E54
Definition: mt9f002_regs.h:552
MT9F002_MFR_3E0A
#define MT9F002_MFR_3E0A
Definition: mt9f002_regs.h:515
MT9F002_MFR_3D9E
#define MT9F002_MFR_3D9E
Definition: mt9f002_regs.h:461
MT9F002_MFR_3D28
#define MT9F002_MFR_3D28
Definition: mt9f002_regs.h:402
MT9F002_OP_SYS_CLK_DIV
#define MT9F002_OP_SYS_CLK_DIV
Definition: mt9f002_regs.h:77
MT9F002_SCALER_N
#define MT9F002_SCALER_N
Definition: mt9f002_regs.h:6
MT9F002_MFR_3D0E
#define MT9F002_MFR_3D0E
Definition: mt9f002_regs.h:389
MT9F002_DAC_LD_24_25
#define MT9F002_DAC_LD_24_25
Definition: mt9f002_regs.h:620
MT9F002_MFR_3E64
#define MT9F002_MFR_3E64
Definition: mt9f002_regs.h:560
MT9F002_SERIAL_FORMAT
#define MT9F002_SERIAL_FORMAT
Definition: mt9f002_regs.h:258
MT9F002_MIN_LINE_LENGTH_PCK
#define MT9F002_MIN_LINE_LENGTH_PCK
Definition: mt9f002_regs.h:133
MT9F002_MFR_3EDC
#define MT9F002_MFR_3EDC
Definition: mt9f002_regs.h:616
MT9F002_DATA_PEDESTAL_
#define MT9F002_DATA_PEDESTAL_
Definition: mt9f002_regs.h:183
MT9F002_ANALOG_CONTROL5
#define MT9F002_ANALOG_CONTROL5
Definition: mt9f002_regs.h:249
MT9F002_MFR_3E56
#define MT9F002_MFR_3E56
Definition: mt9f002_regs.h:553
mt9f002_init
void mt9f002_init(struct mt9f002_t *mt)
Initialisation of the Aptina MT9F002 CMOS sensor (front camera)
Definition: mt9f002.c:788
MT9F002_MFR_3D48
#define MT9F002_MFR_3D48
Definition: mt9f002_regs.h:418
MT9F002_MFR_3DEC
#define MT9F002_MFR_3DEC
Definition: mt9f002_regs.h:500
MT9F002_MFR_3D78
#define MT9F002_MFR_3D78
Definition: mt9f002_regs.h:442
MT9F002_MFR_3DFA
#define MT9F002_MFR_3DFA
Definition: mt9f002_regs.h:507
MT9F002_MFR_3D8E
#define MT9F002_MFR_3D8E
Definition: mt9f002_regs.h:453
MT9F002_Y_OUTPUT_SIZE
#define MT9F002_Y_OUTPUT_SIZE
Definition: mt9f002_regs.h:85
MT9F002_MFR_3DC2
#define MT9F002_MFR_3DC2
Definition: mt9f002_regs.h:479
MT9F002_MFR_3EC8
#define MT9F002_MFR_3EC8
Definition: mt9f002_regs.h:610
MT9F002_MFR_3D40
#define MT9F002_MFR_3D40
Definition: mt9f002_regs.h:414
MT9F002_MFR_3DB6
#define MT9F002_MFR_3DB6
Definition: mt9f002_regs.h:473
MT9F002_MFR_3D66
#define MT9F002_MFR_3D66
Definition: mt9f002_regs.h:433
mt9f002_regs.h
MAX
#define MAX(x, y)
Definition: mt9f002.c:41
mt9f002_t::output_scaler
float output_scaler
Output scale.
Definition: mt9f002.h:70
MT9F002_MFR_3E22
#define MT9F002_MFR_3E22
Definition: mt9f002_regs.h:527
mt9f002_t::shift_vt_pix_clk_div
uint8_t shift_vt_pix_clk_div
Fixed PLL config from calculator tool.
Definition: mt9f002.h:50
MT9F002_MFR_3E60
#define MT9F002_MFR_3E60
Definition: mt9f002_regs.h:558
MT9F002_MFR_3D50
#define MT9F002_MFR_3D50
Definition: mt9f002_regs.h:422
MT9F002_MFR_3EB0
#define MT9F002_MFR_3EB0
Definition: mt9f002_regs.h:598
MT9F002_COARSE_INTEGRATION_TIME
#define MT9F002_COARSE_INTEGRATION_TIME
Definition: mt9f002_regs.h:62
MT9F002_MFR_3DA2
#define MT9F002_MFR_3DA2
Definition: mt9f002_regs.h:463
mt9f002_t::row_speed_10_8
uint8_t row_speed_10_8
Fixed PLL config from calculator tool.
Definition: mt9f002.h:52
MT9F002_MFR_3D94
#define MT9F002_MFR_3D94
Definition: mt9f002_regs.h:456
MT9F002_MFR_3E98
#define MT9F002_MFR_3E98
Definition: mt9f002_regs.h:586
MT9F002_MFR_3DFC
#define MT9F002_MFR_3DFC
Definition: mt9f002_regs.h:508
MT9F002_MFR_3E2A
#define MT9F002_MFR_3E2A
Definition: mt9f002_regs.h:531
MT9F002_MFR_3DA4
#define MT9F002_MFR_3DA4
Definition: mt9f002_regs.h:464
I2CTransDone
transaction set to done by user level
Definition: i2c.h:59
MT9F002_MFR_3D4C
#define MT9F002_MFR_3D4C
Definition: mt9f002_regs.h:420
mt9f002_t::interface
enum mt9f002_interface interface
Interface used to connect.
Definition: mt9f002.h:42
MT9F002_MFR_3D52
#define MT9F002_MFR_3D52
Definition: mt9f002_regs.h:423
MT9F002_GREEN1_GAIN
#define MT9F002_GREEN1_GAIN
Definition: mt9f002_regs.h:204
mt9f002_mipi_stage3
static void mt9f002_mipi_stage3(struct mt9f002_t *mt)
Configure stage 3 for both MiPi and HiSPi connection.
Definition: mt9f002.c:386
MT9F002_MFR_3DB4
#define MT9F002_MFR_3DB4
Definition: mt9f002_regs.h:472
MT9F002_MFR_3D90
#define MT9F002_MFR_3D90
Definition: mt9f002_regs.h:454
MT9F002_MFR_3D98
#define MT9F002_MFR_3D98
Definition: mt9f002_regs.h:458
MT9F002_MFR_3DDC
#define MT9F002_MFR_3DDC
Definition: mt9f002_regs.h:492
mt9f002_calc_gain
static uint16_t mt9f002_calc_gain(float gain)
Calculate the gain based on value of 1.0 -> 63.50.
Definition: mt9f002.c:720
mt9f002_t::line_length
uint16_t line_length
Calculated line length of blanking.
Definition: mt9f002.h:55
MT9F002_MFR_3D68
#define MT9F002_MFR_3D68
Definition: mt9f002_regs.h:434
mt9f002_t::real_fps
float real_fps
Real calculated FPS.
Definition: mt9f002.h:59
MT9F002_MFR_3E6E
#define MT9F002_MFR_3E6E
Definition: mt9f002_regs.h:565
MT9F002_DATAPATH_SELECT
#define MT9F002_DATAPATH_SELECT
Definition: mt9f002_regs.h:211
MT9F002_OUTPUT_HEIGHT
#define MT9F002_OUTPUT_HEIGHT
Definition: bebop.h:32
mt9f002_set_gains
static void mt9f002_set_gains(struct mt9f002_t *mt)
Sets the GreenR, Blue, Red and GreenB gains.
Definition: mt9f002.c:776
MT9F002_RESET_REGISTER
#define MT9F002_RESET_REGISTER
Definition: mt9f002_regs.h:180
MT9F002_MFR_3DE6
#define MT9F002_MFR_3DE6
Definition: mt9f002_regs.h:497
mt9f002_parallel_stage1
static void mt9f002_parallel_stage1(struct mt9f002_t *mt)
Configure stage 1 for parallel connection.
Definition: mt9f002.c:397
MT9F002_MFR_3E96
#define MT9F002_MFR_3E96
Definition: mt9f002_regs.h:585
MT9F002_MFR_3D3E
#define MT9F002_MFR_3D3E
Definition: mt9f002_regs.h:413
MT9F002_MFR_3DBA
#define MT9F002_MFR_3DBA
Definition: mt9f002_regs.h:475
MT9F002_MFR_3DB2
#define MT9F002_MFR_3DB2
Definition: mt9f002_regs.h:471
val
uint16_t val[TCOUPLE_NB]
Definition: temp_tcouple_adc.c:49
MT9F002_MFR_3E12
#define MT9F002_MFR_3E12
Definition: mt9f002_regs.h:519
MT9F002_MFR_3D62
#define MT9F002_MFR_3D62
Definition: mt9f002_regs.h:431
uint32_t
unsigned long uint32_t
Definition: types.h:18
mt9f002_set_pll
static void mt9f002_set_pll(struct mt9f002_t *mt)
Set the PLL registers based on config.
Definition: mt9f002.c:535
MT9F002_MFR_3EA2
#define MT9F002_MFR_3EA2
Definition: mt9f002_regs.h:591
MT9F002_MFR_3D8A
#define MT9F002_MFR_3D8A
Definition: mt9f002_regs.h:451
mt9f002_t::gain_green1
float gain_green1
Gain for the GreenR pixels [1.5 -> 63.50].
Definition: mt9f002.h:63
MT9F002_ANALOG_CONTROL7
#define MT9F002_ANALOG_CONTROL7
Definition: mt9f002_regs.h:250
mt9f002_t::output_width
uint16_t output_width
Output width.
Definition: mt9f002.h:68
MT9F002_MFR_3DFE
#define MT9F002_MFR_3DFE
Definition: mt9f002_regs.h:509
MT9F002_MFR_3E24
#define MT9F002_MFR_3E24
Definition: mt9f002_regs.h:528
MT9F002_MFR_3DAA
#define MT9F002_MFR_3DAA
Definition: mt9f002_regs.h:467
MT9F002_MFR_3E80
#define MT9F002_MFR_3E80
Definition: mt9f002_regs.h:574
MT9F002_MFR_3DE4
#define MT9F002_MFR_3DE4
Definition: mt9f002_regs.h:496
MT9F002_MFR_3EB2
#define MT9F002_MFR_3EB2
Definition: mt9f002_regs.h:599
MT9F002_MFR_3D12
#define MT9F002_MFR_3D12
Definition: mt9f002_regs.h:391
MT9F002_FRAME_LENGTH_LINES
#define MT9F002_FRAME_LENGTH_LINES
Definition: mt9f002_regs.h:78
write_reg
static void write_reg(struct mt9f002_t *mt, uint16_t addr, uint32_t val, uint8_t len)
Write multiple bytes to a single register.
Definition: mt9f002.c:72
MT9F002_MFR_3DE8
#define MT9F002_MFR_3DE8
Definition: mt9f002_regs.h:498
MT9F002_SCALE_M
#define MT9F002_SCALE_M
Definition: mt9f002_regs.h:92
MT9F002_MFR_3EB6
#define MT9F002_MFR_3EB6
Definition: mt9f002_regs.h:601
MT9F002_MFR_3DEA
#define MT9F002_MFR_3DEA
Definition: mt9f002_regs.h:499
MT9F002_MFR_3E90
#define MT9F002_MFR_3E90
Definition: mt9f002_regs.h:582
MT9F002_MFR_3E20
#define MT9F002_MFR_3E20
Definition: mt9f002_regs.h:526
mt9f002_t::vt_pix_clk
float vt_pix_clk
Calculated based on PLL.
Definition: mt9f002.h:53
MT9F002_MFR_3E9A
#define MT9F002_MFR_3E9A
Definition: mt9f002_regs.h:587
MT9F002_MFR_3E58
#define MT9F002_MFR_3E58
Definition: mt9f002_regs.h:554
MT9F002_MFR_3D26
#define MT9F002_MFR_3D26
Definition: mt9f002_regs.h:401
mt9f002_t::target_fps
float target_fps
FPS wanted.
Definition: mt9f002.h:58
MT9F002_X_OUTPUT_SIZE
#define MT9F002_X_OUTPUT_SIZE
Definition: mt9f002_regs.h:84
MT9F002_COLUMN_CORRECTION
#define MT9F002_COLUMN_CORRECTION
Definition: mt9f002_regs.h:233
MT9F002_MFR_3E76
#define MT9F002_MFR_3E76
Definition: mt9f002_regs.h:569
MT9F002_DARK_CONTROL3
#define MT9F002_DARK_CONTROL3
Definition: mt9f002_regs.h:237
MT9F002_MFR_3EAA
#define MT9F002_MFR_3EAA
Definition: mt9f002_regs.h:595
MT9F002_MFR_3D74
#define MT9F002_MFR_3D74
Definition: mt9f002_regs.h:440
MT9F002_Y_ADDR_END
#define MT9F002_Y_ADDR_END
Definition: mt9f002_regs.h:83
MT9F002_MFR_3D10
#define MT9F002_MFR_3D10
Definition: mt9f002_regs.h:390
MT9F002_MFR_3DBC
#define MT9F002_MFR_3DBC
Definition: mt9f002_regs.h:476
MT9F002_EXTRA_DELAY
#define MT9F002_EXTRA_DELAY
Definition: mt9f002_regs.h:179
MT9F002_MFR_3E08
#define MT9F002_MFR_3E08
Definition: mt9f002_regs.h:514
MT9F002_MFR_3E5C
#define MT9F002_MFR_3E5C
Definition: mt9f002_regs.h:556
mt9f002_t::gain_red
float gain_red
Gain for the Red pixels [1.5 -> 63.50].
Definition: mt9f002.h:65
MT9F002_MFR_3D84
#define MT9F002_MFR_3D84
Definition: mt9f002_regs.h:448
MT9F002_MFR_3D0C
#define MT9F002_MFR_3D0C
Definition: mt9f002_regs.h:388
i2c_transceive
bool i2c_transceive(struct i2c_periph *p, struct i2c_transaction *t, uint8_t s_addr, uint8_t len_w, uint16_t len_r)
Submit a write/read transaction.
Definition: i2c.c:278
MT9F002_MFR_3D06
#define MT9F002_MFR_3D06
Definition: mt9f002_regs.h:385
MT9F002_MFR_3E0C
#define MT9F002_MFR_3E0C
Definition: mt9f002_regs.h:516
i2c_transaction::status
enum I2CTransactionStatus status
Transaction status.
Definition: i2c.h:126
MT9F002_MFR_3DD2
#define MT9F002_MFR_3DD2
Definition: mt9f002_regs.h:487
MT9F002_MFR_3E52
#define MT9F002_MFR_3E52
Definition: mt9f002_regs.h:551
MT9F002_MFR_3D1E
#define MT9F002_MFR_3D1E
Definition: mt9f002_regs.h:397
MT9F002_MFR_3D58
#define MT9F002_MFR_3D58
Definition: mt9f002_regs.h:426
mt9f002_t
Definition: mt9f002.h:41
i2c_transmit
bool i2c_transmit(struct i2c_periph *p, struct i2c_transaction *t, uint8_t s_addr, uint8_t len)
Submit a write only transaction.
Definition: i2c.c:258
MT9F002_COARSE_INTEGRATION_TIME_MAX_MARGIN
#define MT9F002_COARSE_INTEGRATION_TIME_MAX_MARGIN
Definition: mt9f002_regs.h:106
int32_t
signed long int32_t
Definition: types.h:19
MT9F002_MFR_3EC6
#define MT9F002_MFR_3EC6
Definition: mt9f002_regs.h:609
MT9F002_MFR_3D92
#define MT9F002_MFR_3D92
Definition: mt9f002_regs.h:455
MT9F002_MFR_3E3A
#define MT9F002_MFR_3E3A
Definition: mt9f002_regs.h:539
MT9F002_MFR_3D4A
#define MT9F002_MFR_3D4A
Definition: mt9f002_regs.h:419
mt9f002_t::i2c_periph
struct i2c_periph * i2c_periph
I2C peripheral used to communicate over.
Definition: mt9f002.h:76
mt9f002_t::gain_green2
float gain_green2
Gain for the GreenB pixels [1.5 -> 63.50].
Definition: mt9f002.h:66
MT9F002_MFR_3D5C
#define MT9F002_MFR_3D5C
Definition: mt9f002_regs.h:428
MT9F002_VT_SYS_CLK_DIV
#define MT9F002_VT_SYS_CLK_DIV
Definition: mt9f002_regs.h:73
MT9F002_MFR_3DBE
#define MT9F002_MFR_3DBE
Definition: mt9f002_regs.h:477
mt9f002.h
Initialization and configuration of the MT9F002 CMOS Chip.
MT9F002_MFR_3E50
#define MT9F002_MFR_3E50
Definition: mt9f002_regs.h:550
MT9F002_MODE_SELECT
#define MT9F002_MODE_SELECT
Definition: mt9f002_regs.h:52
mt9f002_t::offset_y
uint16_t offset_y
Offset from top in pixels.
Definition: mt9f002.h:74
MT9F002_OP_PIX_CLK_DIV
#define MT9F002_OP_PIX_CLK_DIV
Definition: mt9f002_regs.h:76
mt9f002_t::real_exposure
float real_exposure
Real exposure time in ms.
Definition: mt9f002.h:61
MT9F002_MFR_3D54
#define MT9F002_MFR_3D54
Definition: mt9f002_regs.h:424
MT9F002_MFR_3DE2
#define MT9F002_MFR_3DE2
Definition: mt9f002_regs.h:495
MT9F002_MFR_3E18
#define MT9F002_MFR_3E18
Definition: mt9f002_regs.h:522
MT9F002_MFR_3E42
#define MT9F002_MFR_3E42
Definition: mt9f002_regs.h:543
MT9F002_GREEN2_GAIN
#define MT9F002_GREEN2_GAIN
Definition: mt9f002_regs.h:207
MT9F002_MFR_3ECA
#define MT9F002_MFR_3ECA
Definition: mt9f002_regs.h:611
MT9F002_SMIA_TEST
#define MT9F002_SMIA_TEST
Definition: mt9f002_regs.h:209
MT9F002_MFR_3D8C
#define MT9F002_MFR_3D8C
Definition: mt9f002_regs.h:452
MT9F002_MFR_3EC2
#define MT9F002_MFR_3EC2
Definition: mt9f002_regs.h:607
mt9f002_t::i2c_trans
struct i2c_transaction i2c_trans
I2C transaction for comminication with CMOS chip.
Definition: mt9f002.h:77
MT9F002_MFR_3E1A
#define MT9F002_MFR_3E1A
Definition: mt9f002_regs.h:523
MT9F002_GLOBAL_GAIN
#define MT9F002_GLOBAL_GAIN
Definition: mt9f002_regs.h:208
MT9F002_MFR_3D04
#define MT9F002_MFR_3D04
Definition: mt9f002_regs.h:384
MT9F002_MFR_3E82
#define MT9F002_MFR_3E82
Definition: mt9f002_regs.h:575
MT9F002_MFR_3E44
#define MT9F002_MFR_3E44
Definition: mt9f002_regs.h:544
MT9F002_MFR_3E02
#define MT9F002_MFR_3E02
Definition: mt9f002_regs.h:511
VIDEO_FILTER_ISP
#define VIDEO_FILTER_ISP
Enable ISP.
Definition: video_device.h:35
MT9F002_MFR_3ED8
#define MT9F002_MFR_3ED8
Definition: mt9f002_regs.h:615
MT9F002_MFR_3DF0
#define MT9F002_MFR_3DF0
Definition: mt9f002_regs.h:502
uint8_t
unsigned char uint8_t
Definition: types.h:14
MT9F002_Y_ADDR_START
#define MT9F002_Y_ADDR_START
Definition: mt9f002_regs.h:81
MT9F002_MFR_3D80
#define MT9F002_MFR_3D80
Definition: mt9f002_regs.h:446
MT9F002_MFR_3DC6
#define MT9F002_MFR_3DC6
Definition: mt9f002_regs.h:481
MT9F002_MFR_3E74
#define MT9F002_MFR_3E74
Definition: mt9f002_regs.h:568
MT9F002_MFR_3D6C
#define MT9F002_MFR_3D6C
Definition: mt9f002_regs.h:436
MT9F002_MFR_3D56
#define MT9F002_MFR_3D56
Definition: mt9f002_regs.h:425
MT9F002_MFR_3D2E
#define MT9F002_MFR_3D2E
Definition: mt9f002_regs.h:405
MT9F002_CPP_DATA_FORMAT
#define MT9F002_CPP_DATA_FORMAT
Definition: mt9f002_regs.h:59
MT9F002_MFR_3E10
#define MT9F002_MFR_3E10
Definition: mt9f002_regs.h:518
MT9F002_MFR_3E00
#define MT9F002_MFR_3E00
Definition: mt9f002_regs.h:510
MT9F002_MFR_3DD8
#define MT9F002_MFR_3DD8
Definition: mt9f002_regs.h:490
MT9F002_MFR_3EAC
#define MT9F002_MFR_3EAC
Definition: mt9f002_regs.h:596
MT9F002_MFR_3E36
#define MT9F002_MFR_3E36
Definition: mt9f002_regs.h:537
mt9f002_t::op_pix_clk_div
uint16_t op_pix_clk_div
Fixed PLL config from calculator tool.
Definition: mt9f002.h:48
MT9F002_MFR_3E70
#define MT9F002_MFR_3E70
Definition: mt9f002_regs.h:566
MT9F002_MFR_3EA4
#define MT9F002_MFR_3EA4
Definition: mt9f002_regs.h:592
MT9F002_MFR_3EBE
#define MT9F002_MFR_3EBE
Definition: mt9f002_regs.h:605
MT9F002_MFR_3D76
#define MT9F002_MFR_3D76
Definition: mt9f002_regs.h:441
MT9F002_MFR_3D16
#define MT9F002_MFR_3D16
Definition: mt9f002_regs.h:393
MT9F002_MFR_3EA0
#define MT9F002_MFR_3EA0
Definition: mt9f002_regs.h:590
MT9F002_MFR_3E2E
#define MT9F002_MFR_3E2E
Definition: mt9f002_regs.h:533
MT9F002_MFR_3D08
#define MT9F002_MFR_3D08
Definition: mt9f002_regs.h:386
MT9F002_MFR_3D5E
#define MT9F002_MFR_3D5E
Definition: mt9f002_regs.h:429
MT9F002_PLL_MULTIPLIER
#define MT9F002_PLL_MULTIPLIER
Definition: mt9f002_regs.h:75
MT9F002_MFR_3DF6
#define MT9F002_MFR_3DF6
Definition: mt9f002_regs.h:505
MT9F002_MFR_3D42
#define MT9F002_MFR_3D42
Definition: mt9f002_regs.h:415
mt9f002_t::op_pix_clk
float op_pix_clk
Calculated based on PLL.
Definition: mt9f002.h:54
MT9F002_MFR_3E4E
#define MT9F002_MFR_3E4E
Definition: mt9f002_regs.h:549
MT9F002_Y_ODD_INC
#define MT9F002_Y_ODD_INC
Definition: mt9f002_regs.h:89
MT9F002_MFR_3176
#define MT9F002_MFR_3176
Definition: mt9f002_regs.h:612
mt9f002_t::pre_pll_clk_div
uint16_t pre_pll_clk_div
Fixed PLL config from calculator tool.
Definition: mt9f002.h:46
MT9F002_MFR_3DEE
#define MT9F002_MFR_3DEE
Definition: mt9f002_regs.h:501
MT9F002_MFR_3D30
#define MT9F002_MFR_3D30
Definition: mt9f002_regs.h:406
MT9F002_MFR_3EC0
#define MT9F002_MFR_3EC0
Definition: mt9f002_regs.h:606
MT9F002_MFR_3E68
#define MT9F002_MFR_3E68
Definition: mt9f002_regs.h:562
MT9F002_MFR_3DCA
#define MT9F002_MFR_3DCA
Definition: mt9f002_regs.h:483
MT9F002_MFR_3D70
#define MT9F002_MFR_3D70
Definition: mt9f002_regs.h:438
MT9F002_RED_GAIN
#define MT9F002_RED_GAIN
Definition: mt9f002_regs.h:206
MT9F002_MFR_3D00
#define MT9F002_MFR_3D00
Definition: mt9f002_regs.h:382
mt9f002_set_blanking
static void mt9f002_set_blanking(struct mt9f002_t *mt)
Set the blanking configuration Blanking of the MT9F002 depends on the target FPS. ...
Definition: mt9f002.c:565
MT9F002_MFR_3EE8
#define MT9F002_MFR_3EE8
Definition: mt9f002_regs.h:618
MT9F002_MFR_3D3C
#define MT9F002_MFR_3D3C
Definition: mt9f002_regs.h:412
MT9F002_MFR_3EA6
#define MT9F002_MFR_3EA6
Definition: mt9f002_regs.h:593
MT9F002_MFR_3D0A
#define MT9F002_MFR_3D0A
Definition: mt9f002_regs.h:387
MT9F002_MFR_3DF2
#define MT9F002_MFR_3DF2
Definition: mt9f002_regs.h:503
MT9F002_FRAME_LENGTH_MAX
#define MT9F002_FRAME_LENGTH_MAX
Definition: mt9f002_regs.h:8
MT9F002_MFR_3E78
#define MT9F002_MFR_3E78
Definition: mt9f002_regs.h:570
MT9F002_MFR_3E1E
#define MT9F002_MFR_3E1E
Definition: mt9f002_regs.h:525
MT9F002_MFR_3DE0
#define MT9F002_MFR_3DE0
Definition: mt9f002_regs.h:494
mt9f002_t::scaled_height
uint16_t scaled_height
Height after corrected scaling.
Definition: mt9f002.h:72
MT9F002_MFR_3E7E
#define MT9F002_MFR_3E7E
Definition: mt9f002_regs.h:573
MT9F002_MFR_3E88
#define MT9F002_MFR_3E88
Definition: mt9f002_regs.h:578
MT9F002_MFR_3D5A
#define MT9F002_MFR_3D5A
Definition: mt9f002_regs.h:427
int32_gcd
uint32_t int32_gcd(uint32_t a, uint32_t b)
Definition: pprz_algebra_int.c:52
MT9F002_MFR_3D82
#define MT9F002_MFR_3D82
Definition: mt9f002_regs.h:447
img_size_t::w
uint16_t w
The width.
Definition: image.h:69
MT9F002_MFR_3E84
#define MT9F002_MFR_3E84
Definition: mt9f002_regs.h:576
mt9f002_mipi_stage2
static void mt9f002_mipi_stage2(struct mt9f002_t *mt)
Configure stage 2 for both MiPi and HiSPi connection.
Definition: mt9f002.c:378
MT9F002_MFR_3D72
#define MT9F002_MFR_3D72
Definition: mt9f002_regs.h:439
MT9F002_MFR_3D22
#define MT9F002_MFR_3D22
Definition: mt9f002_regs.h:399
MT9F002_MFR_3DCE
#define MT9F002_MFR_3DCE
Definition: mt9f002_regs.h:485
MT9F002_PRE_PLL_CLK_DIV
#define MT9F002_PRE_PLL_CLK_DIV
Definition: mt9f002_regs.h:74
MT9F002_MFR_3D36
#define MT9F002_MFR_3D36
Definition: mt9f002_regs.h:409
MT9F002_MFR_3E06
#define MT9F002_MFR_3E06
Definition: mt9f002_regs.h:513
MT9F002_MIN_LINE_BLANKING_PCK
#define MT9F002_MIN_LINE_BLANKING_PCK
Definition: mt9f002_regs.h:135
MT9F002_MFR_3D2A
#define MT9F002_MFR_3D2A
Definition: mt9f002_regs.h:403
MT9F002_X_ADDR_START
#define MT9F002_X_ADDR_START
Definition: mt9f002_regs.h:80
MT9F002_ROW_SPEED
#define MT9F002_ROW_SPEED
Definition: mt9f002_regs.h:178
MT9F002_MFR_3E9E
#define MT9F002_MFR_3E9E
Definition: mt9f002_regs.h:589
video_config_t
V4L2 device settings.
Definition: video_device.h:44
mt9f002_t::frame_length
uint16_t frame_length
Calculated frame length of blanking.
Definition: mt9f002.h:56
mt9f002_t::input_clk_freq
float input_clk_freq
Input clock frequency.
Definition: mt9f002.h:43
MT9F002_MFR_3D34
#define MT9F002_MFR_3D34
Definition: mt9f002_regs.h:408
MT9F002_MIPI
MIPI type connection.
Definition: mt9f002.h:35
MT9F002_MFR_3DA8
#define MT9F002_MFR_3DA8
Definition: mt9f002_regs.h:466
MT9F002_MFR_3D02
#define MT9F002_MFR_3D02
Definition: mt9f002_regs.h:383
mt9f002_t::target_exposure
float target_exposure
Target exposure time in ms.
Definition: mt9f002.h:60
MT9F002_MFR_3E14
#define MT9F002_MFR_3E14
Definition: mt9f002_regs.h:520
pprz_algebra_int.h
Paparazzi fixed point algebra.
MT9F002_MFR_3EA8
#define MT9F002_MFR_3EA8
Definition: mt9f002_regs.h:594
MT9F002_MFR_3D6E
#define MT9F002_MFR_3D6E
Definition: mt9f002_regs.h:437
MT9F002_MFR_3E30
#define MT9F002_MFR_3E30
Definition: mt9f002_regs.h:534
MT9F002_MFR_3D9C
#define MT9F002_MFR_3D9C
Definition: mt9f002_regs.h:460
front_camera
struct video_config_t front_camera
Definition: mt9f002.c:44
MT9F002_MFR_3DD0
#define MT9F002_MFR_3DD0
Definition: mt9f002_regs.h:486