hal_stm32_dma.h

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/*
 * Copyright (C) 2019 Alexandre Bustico, Gautier Hattenberger
 *
 * This file is part of paparazzi.
 *
 * paparazzi is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 *
 * paparazzi is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with paparazzi; see the file COPYING.  If not, see
 * <http://www.gnu.org/licenses/>.
 */
 
#pragma once
 
#include <ch.h>
#include <hal.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if !defined(STM32_DMA_USE_WAIT) || defined(__DOXYGEN__)
#define STM32_DMA_USE_WAIT                TRUE
#endif
 
#if !defined(STM32_DMA_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define STM32_DMA_USE_MUTUAL_EXCLUSION    FALSE
#endif
 
#if !defined(STM32_DMA_SUPPORTS_CSELR) || defined(__DOXYGEN__)
#define STM32_DMA_SUPPORTS_CSELR   FALSE
#endif
 
#if !defined(STM32_DMA_SUPPORTS_DMAMUX) || defined(__DOXYGEN__)
#define STM32_DMA_SUPPORTS_DMAMUX  FALSE
#endif
 
#if  !defined(STM32_DMA_DUMMY_MEMORY_AREA_ADDRESS) || defined(__DOXYGEN__)
#define  STM32_DMA_DUMMY_MEMORY_AREA_ADDRESS 0x80000000
#endif   
 
#if  !defined(__DCACHE_PRESENT) 
#define  __DCACHE_PRESENT FALSE
#endif  
 
typedef enum {
  DMA_UNINIT = 0,                           
  DMA_STOP = 1,                             
  DMA_READY = 2,                            
  DMA_ACTIVE = 3,                           
  DMA_COMPLETE = 4,                         
  DMA_ERROR = 5                             
} dmastate_t;
 
typedef enum {
  DMA_ERR_TRANSFER_ERROR   = 1U << 0U,          
  DMA_ERR_DIRECTMODE_ERROR = 1U << 1U,          
  DMA_ERR_FIFO_ERROR       = 1U << 2U,          
  DMA_ERR_FIFO_FULL        = 1U << 3U,          
  DMA_ERR_FIFO_EMPTY       = 1U << 4U,          
} dmaerrormask_t;
 
typedef enum {
  DMA_DIR_P2M = 1,           
  DMA_DIR_M2P = 2,           
  DMA_DIR_M2M = 3,           
} dmadirection_t;
 
typedef enum {
  DMA_ONESHOT = 1,      
  DMA_CONTINUOUS_HALF_BUFFER,       
#if  STM32_DMA_USE_DOUBLE_BUFFER
  DMA_CONTINUOUS_DOUBLE_BUFFER     
#endif
} dmaopmode_t;
 
typedef struct DMADriver DMADriver;
 
typedef void (*dmacallback_t)(DMADriver *dmap, void *buffer, const size_t n);
 
typedef void * (*dmanextcallback_t)(DMADriver *dmap, const size_t n);
 
 
typedef void (*dmaerrorcallback_t)(DMADriver *dmap, dmaerrormask_t err);
 
 
 
/*===========================================================================*/
/* Driver macros.                                                            */
/*===========================================================================*/
#if (STM32_DMA_USE_WAIT == TRUE) || defined(__DOXYGEN__)
#define _dma_reset_i(dmap)                                                  \
  osalThreadResumeI(&(dmap)->thread, MSG_RESET)
 
#define _dma_reset_s(dmap)                                                  \
  osalThreadResumeS(&(dmap)->thread, MSG_RESET)
 
#define _dma_wakeup_isr(dmap) {                                             \
    osalSysLockFromISR();                                                     \
    osalThreadResumeI(&(dmap)->thread, MSG_OK);                               \
    osalSysUnlockFromISR();                                                   \
  }
 
#define _dma_timeout_isr(dmap) {                                            \
    osalSysLockFromISR();                                                     \
    osalThreadResumeI(&(dmap)->thread, MSG_TIMEOUT);                          \
    osalSysUnlockFromISR();                                                   \
  }
#else /* !STM32_DMA_USE_WAIT */
#define _dma_reset_i(dmap)
#define _dma_reset_s(dmap)
#define _dma_wakeup_isr(dmap)
#define _dma_timeout_isr(dmap)
#endif /* !STM32_DMA_USE_WAIT */
 
static inline void _dma_isr_half_code(DMADriver *dmap);
 
 
static inline void _dma_isr_full_code(DMADriver *dmap);
 
 
static inline void _dma_isr_error_code(DMADriver *dmap, dmaerrormask_t err);
 
 
 
 
typedef struct  {
  uint32_t    stream;
 
#if STM32_DMA_SUPPORTS_DMAMUX
  uint32_t    dmamux; // 4 bytes wide for mdma use
#else
#if STM32_DMA_SUPPORTS_CSELR
  union {
    uint8_t   request; // STM terminology for dmaV1
    uint8_t   channel; // ChibiOS terminology for both dmaV1 and dmaV2 (portability)
  };
#else
  uint8_t   channel;
#endif
#endif
 
  bool      inc_peripheral_addr;
 
 
  bool      inc_memory_addr;
 
 
  dmaopmode_t op_mode;
 
 
  dmacallback_t         end_cb;
 
#if STM32_DMA_USE_DOUBLE_BUFFER
  dmanextcallback_t     next_cb;
#endif
 
  dmaerrorcallback_t    error_cb;
#if STM32_DMA_USE_ASYNC_TIMOUT
  sysinterval_t timeout;
#endif
 
 
  dmadirection_t  direction;
 
 
  uint8_t   dma_priority;
 
  uint8_t   irq_priority;
 
  uint8_t   psize; // 1,2,4
 
  uint8_t   msize; // 1,2,4
#if __DCACHE_PRESENT
  union {
    bool    dcache_memory_in_use; // this name was hardly meaningfull
    bool    activate_dcache_sync;
  };
#endif
#if STM32_DMA_ADVANCED
#define STM32_DMA_FIFO_SIZE 16 // hardware specification for dma V2
 
  uint8_t   pburst; // 0(burst disabled), 4, 8, 16
 
  uint8_t   mburst; // 0(burst disabled), 4, 8, 16
 
  uint8_t   fifo;   // 0(fifo disabled), 1, 2, 3, 4 : 25, 50, 75, 100%
 
  bool      periph_inc_size_4; // PINCOS bit
 
  bool      transfert_end_ctrl_by_periph; // PFCTRL bit
#endif
#if STM32_DMA_DRIVER_USER_DATA_FIELD
  void *user_data;
#endif
}  DMAConfig;
 
 
struct DMADriver {
  const stm32_dma_stream_t  *dmastream;
 
  const DMAConfig     *config;
 
#if STM32_DMA_USE_WAIT || defined(__DOXYGEN__)
  thread_reference_t        thread;
#endif
#if STM32_DMA_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
  mutex_t                   mutex;
#endif /* STM32_DMA_USE_MUTUAL_EXCLUSION */
#if STM32_DMA_USE_ASYNC_TIMOUT
  uint8_t       *volatile currPtr;
 
  virtual_timer_t      vt;
#endif
  void           *mem0p;
 
  uint32_t         dmamode;
 
#if __DCACHE_PRESENT
  volatile void          * periphp;
#endif
 
#if STM32_DMA_ADVANCED
  uint32_t         fifomode;
#endif
 
  size_t         size;
 
#if STM32_DMA_USE_DOUBLE_BUFFER
  volatile uint32_t        next_cb_errors;
#endif
 
#if CH_DBG_SYSTEM_STATE_CHECK
  volatile size_t        nbTransferError;
  volatile size_t        nbDirectModeError;
  volatile size_t        nbFifoError;
  volatile size_t        nbFifoFull;
  volatile size_t        nbFifoEmpty;
  volatile dmaerrormask_t      lastError;
#endif
  volatile dmastate_t        state;
 
 
#if STM32_DMA_SUPPORTS_DMAMUX == 0
  uint8_t        controller;
#endif
};
 
 
 
void  dmaObjectInit(DMADriver *dmap);
bool  dmaStart(DMADriver *dmap, const DMAConfig *cfg);
bool  dmaReloadConf(DMADriver *dmap, const DMAConfig *cfg);
void  dmaStop(DMADriver *dmap);
 
#if STM32_DMA_USE_WAIT == TRUE
msg_t dmaTransfertTimeout(DMADriver *dmap, volatile void *periphp, void * mem0p, const size_t size,
       sysinterval_t timeout);
// helper
static inline msg_t dmaTransfert(DMADriver *dmap, volatile void *periphp, void * mem0p, const size_t size)
{
  return dmaTransfertTimeout(dmap, periphp, mem0p, size, TIME_INFINITE);
}
#endif
#if STM32_DMA_USE_MUTUAL_EXCLUSION == TRUE
void dmaAcquireBus(DMADriver *dmap);
void dmaReleaseBus(DMADriver *dmap);
#endif
bool  dmaStartTransfert(DMADriver *dmap, volatile void *periphp, void * mem0p, const size_t size);
void  dmaStopTransfert(DMADriver *dmap);
 
bool  dmaStartTransfertI(DMADriver *dmap, volatile void *periphp, void *mem0p, const size_t size);
void  dmaStopTransfertI(DMADriver *dmap);
uint8_t dmaGetStreamIndex(DMADriver *dmap);
#ifndef DMA_request_TypeDef
void  dmaGetRegisters(DMADriver *dmap, volatile void *periphp, void *mem0p,
          const size_t size,
          DMA_Stream_TypeDef *registers);
#endif
static  inline dmastate_t dmaGetState(DMADriver *dmap) {return dmap->state;}
static  inline size_t dmaGetTransactionCounter(DMADriver *dmap) {return dmaStreamGetTransactionSize(dmap->dmastream);}
 
#if  STM32_DMA_USE_DOUBLE_BUFFER
static  inline dmastate_t dmaGetNextErrors(DMADriver *dmap) {return dmap->next_cb_errors;}
static  inline void dmaClearNextErrors(DMADriver *dmap) {dmap->next_cb_errors = 0U;}
#endif
 
// low level driver
 
bool  dma_lld_start(DMADriver *dmap, bool allocate_stream);
void  dma_lld_stop(DMADriver *dmap);
 
 
bool  dma_lld_start_transfert(DMADriver *dmap, volatile void *periphp, void *mem0p, const size_t size);
 
 
void  dma_lld_stop_transfert(DMADriver *dmap);
 
#if STM32_DMA_USE_ASYNC_TIMOUT
void dma_lld_serve_timeout_interrupt(void *arg);
#endif
 
void* dma_lld_set_next_double_buffer(DMADriver *dmap, void *nextBuffer);
 
#if STM32_DMA_USE_ASYNC_TIMOUT
typedef enum {FROM_TIMOUT_CODE, FROM_HALF_CODE, FROM_FULL_CODE, FROM_NON_CIRCULAR_CODE} CbCallContext;
static inline void async_timout_enabled_call_end_cb(DMADriver *dmap, const CbCallContext context)
{
  uint8_t *const baseAddr = dmap->currPtr;
  const size_t fullSize = dmap->size;
  const size_t halfSize = fullSize / 2;
  size_t rem = 0;
  uint8_t *const basePtr = (uint8_t *) dmap->mem0p;
  uint8_t *const midPtr = ((uint8_t *) dmap->mem0p) + (dmap->config->msize * halfSize);
  uint8_t *const endPtr = ((uint8_t *) dmap->mem0p) + (dmap->config->msize * fullSize);
 
 
  switch (context) {
    case (FROM_HALF_CODE) :
      if (midPtr > baseAddr) {
        rem = (midPtr - baseAddr) / dmap->config->msize;
        dmap->currPtr = midPtr;
      }
      break;
 
    case (FROM_FULL_CODE) :
    case (FROM_NON_CIRCULAR_CODE) :
      rem = (endPtr - baseAddr) / dmap->config->msize;
      dmap->currPtr = basePtr;
      break;
 
    case (FROM_TIMOUT_CODE) : {
      const size_t dmaCNT = dmaStreamGetTransactionSize(dmap->dmastream);
      const size_t index = (baseAddr - basePtr) / dmap->config->msize;
 
      // if following test fail, it's because DMACNT has rollover during the ISR,
      // so that we can safely ignore this TIMOUT event since a fullcode ISR will follow
      // briefly
      if (fullSize >= (dmaCNT + index)) {
        rem = (fullSize - dmaCNT - index);
        dmap->currPtr = baseAddr + (rem * dmap->config->msize);
      }
    }
    break;
  }
 
  if (dmap->config->end_cb != NULL  && (rem > 0)) {
    dmap->config->end_cb(dmap, baseAddr, rem);
  }
}
#endif
 
static inline void _dma_isr_half_code(DMADriver *dmap)
{
#if STM32_DMA_USE_ASYNC_TIMOUT
  if (dmap->config->timeout != TIME_INFINITE) {
    chSysLockFromISR();
    chVTSetI(&dmap->vt, dmap->config->timeout,
             &dma_lld_serve_timeout_interrupt, (void *) dmap);
    chSysUnlockFromISR();
  }
  async_timout_enabled_call_end_cb(dmap, FROM_HALF_CODE);
#else
  if (dmap->config->end_cb != NULL) {
    dmap->config->end_cb(dmap, dmap->mem0p, dmap->size / 2);
  }
#endif
}
 
static inline void _dma_isr_full_code(DMADriver *dmap)
{
  if (dmap->config->op_mode == DMA_CONTINUOUS_HALF_BUFFER) {
#if STM32_DMA_USE_ASYNC_TIMOUT
    if (dmap->config->timeout != TIME_INFINITE) {
      chSysLockFromISR();
      chVTSetI(&dmap->vt, dmap->config->timeout,
               &dma_lld_serve_timeout_interrupt, (void *) dmap);
      chSysUnlockFromISR();
    }
    async_timout_enabled_call_end_cb(dmap, FROM_FULL_CODE);
#else
    /* Callback handling.*/
    if (dmap->config->end_cb != NULL) {
      if (dmap->size > 1) {
        /* Invokes the callback passing the 2nd half of the buffer.*/
        const size_t half_index = dmap->size / 2;
        const uint8_t *byte_array_p = ((uint8_t *) dmap->mem0p) +
                                      dmap->config->msize * half_index;
        dmap->config->end_cb(dmap, (void *) byte_array_p, half_index);
      } else {
        /* Invokes the callback passing the whole buffer.*/
        dmap->config->end_cb(dmap, dmap->mem0p, dmap->size);
      }
    }
#endif
  }
  else if (dmap->config->op_mode == DMA_ONESHOT) {  // not circular
    /* End transfert.*/
#if STM32_DMA_USE_ASYNC_TIMOUT
    if (dmap->config->timeout != TIME_INFINITE) {
      chSysLockFromISR();
      chVTResetI(&dmap->vt);
      chSysUnlockFromISR();
    }
#endif
    dma_lld_stop_transfert(dmap);
    if (dmap->config->end_cb != NULL) {
      dmap->state = DMA_COMPLETE;
      /* Invoke the callback passing the whole buffer.*/
#if STM32_DMA_USE_ASYNC_TIMOUT
      async_timout_enabled_call_end_cb(dmap, FROM_NON_CIRCULAR_CODE);
#else
      dmap->config->end_cb(dmap, dmap->mem0p, dmap->size);
#endif
      if (dmap->state == DMA_COMPLETE) {
        dmap->state = DMA_READY;
      }
    } else {
      dmap->state = DMA_READY;
    }
    _dma_wakeup_isr(dmap);
  }
#if  STM32_DMA_USE_DOUBLE_BUFFER
  else { // CONTINUOUS_DOUBLE_BUFFER
    /* Next buffer handling */
    void* const rawNextBuff =  dmap->config->next_cb(dmap, dmap->size);
    if (rawNextBuff == NULL) 
      dmap->next_cb_errors++;
    void* const nextBuff = rawNextBuff ? rawNextBuff : (void *) STM32_DMA_DUMMY_MEMORY_AREA_ADDRESS;
    void* const memXp = dma_lld_set_next_double_buffer(dmap, nextBuff);
    /* Callback handling.*/
    if ((dmap->config->end_cb != NULL) &&
  (memXp != (void *) STM32_DMA_DUMMY_MEMORY_AREA_ADDRESS)){
      dmap->config->end_cb(dmap, memXp, dmap->size);
    }
  }
#endif
}
 
static inline void _dma_isr_error_code(DMADriver *dmap, dmaerrormask_t err) {
#if CH_DBG_SYSTEM_STATE_CHECK == TRUE
  if (err & DMA_ERR_TRANSFER_ERROR)
    dmap->nbTransferError++;
  if (err & DMA_ERR_DIRECTMODE_ERROR)
    dmap->nbDirectModeError++;
  if (err & DMA_ERR_FIFO_ERROR) {
    dmap->nbFifoError++;
    if (err & DMA_ERR_FIFO_FULL)
       dmap->nbFifoFull++;
    if (err & DMA_ERR_FIFO_EMPTY)
       dmap->nbFifoEmpty++;
  }
  dmap->lastError = err;
#endif
  if (err & (DMA_ERR_TRANSFER_ERROR | DMA_ERR_DIRECTMODE_ERROR))
    dma_lld_stop_transfert(dmap);
  else
    return;
 
  if (dmap->config->error_cb != NULL) {
    dmap->state = DMA_ERROR;
    dmap->config->error_cb(dmap, err);
    if (dmap->state == DMA_ERROR)
      dmap->state = DMA_READY;
  } else {
    dmap->state = DMA_READY;
  }
  _dma_timeout_isr(dmap);
}
#ifndef DMA_request_TypeDef
void  dma_lld_get_registers(DMADriver *dmap, volatile void *periphp,
          void *mem0p, const size_t size,
          DMA_Stream_TypeDef *registers);
#endif
#ifdef __cplusplus
}
#endif