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sc18is600_arch.c
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1 #include "peripherals/sc18is600.h"
2 
3 #include <stm32/rcc.h>
4 #include <stm32/spi.h>
5 #include <stm32/exti.h>
6 #include <stm32/misc.h>
7 #include <stm32/dma.h>
8 #include <stm32/gpio.h>
9 
10 /* commands definition */
11 #define Sc18Is600_Cmd_Write 0x00
12 #define Sc18Is600_Cmd_Read 0x01
13 #define Sc18Is600_Cmd_Read_After_Write 0x02
14 #define Sc18Is600_Cmd_Write_After_Write 0x03
15 #define Sc18Is600_Cmd_Read_Buffer 0x06
16 #define Sc18Is600_Cmd_Write_To_Reg 0x20
17 #define Sc18Is600_Cmd_Read_From_Reg 0x21
18 #define Sc18Is600_Cmd_Power_Down 0x30
19 
20 extern void exti2_irq_handler(void);
21 extern void dma1_c4_irq_handler(void);
22 
23 static inline void sc18is600_setup_SPI_DMA(uint8_t _len);
24 
26 {
27 
28  /* set slave select as output and assert it ( on PB12) */
30  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
31  GPIO_InitTypeDef GPIO_InitStructure;
32  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
33  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
34  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
35  GPIO_Init(GPIOB, &GPIO_InitStructure);
36 
37  /* configure external interrupt exti2 on PD2( data ready ) */
38  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_AFIO, ENABLE);
39  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
40  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
41  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
42  GPIO_Init(GPIOD, &GPIO_InitStructure);
43 
44  EXTI_InitTypeDef EXTI_InitStructure;
45  GPIO_EXTILineConfig(GPIO_PortSourceGPIOD, GPIO_PinSource2);
46  EXTI_InitStructure.EXTI_Line = EXTI_Line2;
47  EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
48  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
49  EXTI_InitStructure.EXTI_LineCmd = ENABLE;
50  EXTI_Init(&EXTI_InitStructure);
51 
52  NVIC_InitTypeDef NVIC_InitStructure;
53  NVIC_InitStructure.NVIC_IRQChannel = EXTI2_IRQn;
54  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
55  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
56  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
57 
58  NVIC_Init(&NVIC_InitStructure);
59 
60  /* Enable DMA1 channel4 IRQ Channel */
61  NVIC_InitTypeDef NVIC_init_struct = {
62  .NVIC_IRQChannel = DMA1_Channel4_IRQn,
63  .NVIC_IRQChannelPreemptionPriority = 0,
64  .NVIC_IRQChannelSubPriority = 0,
65  .NVIC_IRQChannelCmd = ENABLE
66  };
67  NVIC_Init(&NVIC_init_struct);
68  /* Enable SPI2 Periph clock -------------------------------------------------*/
69  RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
70 
71  /* Configure GPIOs: SCK, MISO and MOSI --------------------------------*/
72  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
73  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
74  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
75  GPIO_Init(GPIOB, &GPIO_InitStructure);
76 
77  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO , ENABLE);
78 
79 
80  /* configure SPI */
81  SPI_InitTypeDef SPI_InitStructure;
82  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
83  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
84  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
85  SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
86  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
87  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
88  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_256;
89  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
90  SPI_InitStructure.SPI_CRCPolynomial = 7;
91  SPI_Init(SPI2, &SPI_InitStructure);
92 
93  /* Enable SPI */
94  SPI_Cmd(SPI2, ENABLE);
95 
96  /* Enable SPI_2 DMA clock ---------------------------------------------------*/
97  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
98 
99 }
100 
101 static inline void sc18is600_setup_SPI_DMA(uint8_t _len)
102 {
103  /* SPI2_Rx_DMA_Channel configuration ------------------------------------*/
104  DMA_DeInit(DMA1_Channel4);
105  DMA_InitTypeDef DMA_initStructure_4 = {
106  .DMA_PeripheralBaseAddr = (uint32_t)(SPI2_BASE + 0x0C),
107  .DMA_MemoryBaseAddr = (uint32_t)sc18is600.priv_rx_buf,
108  .DMA_DIR = DMA_DIR_PeripheralSRC,
109  .DMA_BufferSize = _len,
110  .DMA_PeripheralInc = DMA_PeripheralInc_Disable,
111  .DMA_MemoryInc = DMA_MemoryInc_Enable,
112  .DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte,
113  .DMA_MemoryDataSize = DMA_MemoryDataSize_Byte,
114  .DMA_Mode = DMA_Mode_Normal,
115  .DMA_Priority = DMA_Priority_VeryHigh,
116  .DMA_M2M = DMA_M2M_Disable
117  };
118  DMA_Init(DMA1_Channel4, &DMA_initStructure_4);
119  /* SPI2_Tx_DMA_Channel configuration ------------------------------------*/
120  DMA_DeInit(DMA1_Channel5);
121  DMA_InitTypeDef DMA_initStructure_5 = {
122  .DMA_PeripheralBaseAddr = (uint32_t)(SPI2_BASE + 0x0C),
123  .DMA_MemoryBaseAddr = (uint32_t)sc18is600.priv_tx_buf,
124  .DMA_DIR = DMA_DIR_PeripheralDST,
125  .DMA_BufferSize = _len,
126  .DMA_PeripheralInc = DMA_PeripheralInc_Disable,
127  .DMA_MemoryInc = DMA_MemoryInc_Enable,
128  .DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte,
129  .DMA_MemoryDataSize = DMA_MemoryDataSize_Byte,
130  .DMA_Mode = DMA_Mode_Normal,
131  .DMA_Priority = DMA_Priority_Medium,
132  .DMA_M2M = DMA_M2M_Disable
133  };
134  DMA_Init(DMA1_Channel5, &DMA_initStructure_5);
135 
136  /* Enable SPI_2 Rx request */
137  SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Rx, ENABLE);
138  /* Enable DMA1 Channel4 */
139  DMA_Cmd(DMA1_Channel4, ENABLE);
140 
141  /* Enable SPI_2 Tx request */
142  SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, ENABLE);
143  /* Enable DMA1 Channel5 */
144  DMA_Cmd(DMA1_Channel5, ENABLE);
145 
146  /* Enable DMA1 Channel4 Transfer Complete interrupt */
147  DMA_ITConfig(DMA1_Channel4, DMA_IT_TC, ENABLE);
148 }
149 
150 
152 {
153 
156  sc18is600.priv_tx_buf[0] = Sc18Is600_Cmd_Write; // write command
157  sc18is600.priv_tx_buf[1] = len;
158  sc18is600.priv_tx_buf[2] = addr;
159  Sc18Is600Select();
160  sc18is600_setup_SPI_DMA(len + 3);
161 
162 }
163 
165 {
166 
167 }
168 
169 void sc18is600_tranceive(uint8_t addr, uint8_t len_tx, uint8_t len_rx)
170 {
173  sc18is600.rx_len = len_rx;
174  sc18is600.priv_tx_buf[0] = Sc18Is600_Cmd_Read_After_Write; // read after write command
175  sc18is600.priv_tx_buf[1] = len_tx;
176  sc18is600.priv_tx_buf[2] = len_rx;
177  sc18is600.priv_tx_buf[3] = addr;
178  sc18is600.priv_tx_buf[4 + len_tx] = addr;
179  Sc18Is600Select();
180  sc18is600_setup_SPI_DMA(len_tx + 5);
181 }
182 
184 {
187  sc18is600.priv_tx_buf[0] = Sc18Is600_Cmd_Write_To_Reg; // write to register
188  sc18is600.priv_tx_buf[1] = addr;
189  sc18is600.priv_tx_buf[2] = value;
190  Sc18Is600Select();
192 }
193 
194 
196 {
199  sc18is600.priv_tx_buf[0] = Sc18Is600_Cmd_Read_From_Reg; // read from register
200  sc18is600.priv_tx_buf[1] = addr;
201  sc18is600.priv_tx_buf[2] = 0;
202  Sc18Is600Select();
204 }
205 
206 #define ReadI2CStatReg() { \
207  sc18is600.priv_tx_buf[0] = Sc18Is600_Cmd_Read_From_Reg; \
208  sc18is600.priv_tx_buf[1] = Sc18Is600_I2CStat; \
209  sc18is600.priv_tx_buf[2] = 0; \
210  Sc18Is600Select(); \
211  sc18is600_setup_SPI_DMA(3); \
212  }
213 
214 
216 {
217  /* clear EXTI */
218  if (EXTI_GetITStatus(EXTI_Line2) != RESET) {
219  EXTI_ClearITPendingBit(EXTI_Line2);
220  }
221  switch (sc18is600.transaction) {
222  case Sc18Is600Receive:
223  case Sc18Is600Transmit:
224  case Sc18Is600Transcieve:
227  ReadI2CStatReg();
228  }
229  break;
232  // should not happen
233  break;
234  default:
235  break;
236  }
237 
238 }
239 
240 
241 
243 {
244 
245  DMA_ITConfig(DMA1_Channel4, DMA_IT_TC, DISABLE);
246  /* Disable SPI_2 Rx and TX request */
247  SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Rx, DISABLE);
248  SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, DISABLE);
249  /* Disable DMA1 Channel4 and 5 */
250  DMA_Cmd(DMA1_Channel4, DISABLE);
251  DMA_Cmd(DMA1_Channel5, DISABLE);
252 
253  switch (sc18is600.transaction) {
258  break;
259  case Sc18Is600Transmit:
263  } else if (sc18is600.status == Sc18Is600ReadingI2CStat) {
267  }
268  break;
269  case Sc18Is600Receive:
270  case Sc18Is600Transcieve:
274  } else if (sc18is600.status == Sc18Is600ReadingI2CStat) {
277  // debug
278  for (int i = 1; i < sc18is600.rx_len + 1; i++) { sc18is600.priv_tx_buf[i] = 0; }
279  Sc18Is600Select();
281  } else if (sc18is600.status == Sc18Is600ReadingBuffer) {
284  }
285  break;
286  default:
287  break;
288  }
289 
290 }
uint8_t i2c_status
Definition: sc18i600.h:39
void sc18is600_transmit(uint8_t addr, uint8_t len)
#define GPIOB
Definition: gpio_arch.h:35
void sc18is600_arch_init(void)
static void sc18is600_setup_SPI_DMA(uint8_t _len)
void sc18is600_write_to_register(uint8_t addr, uint8_t value)
#define GPIOD
Definition: gpio_arch.h:35
#define Sc18Is600_Cmd_Read_After_Write
unsigned long uint32_t
Definition: types.h:18
#define Sc18Is600_Cmd_Write
struct Sc18Is600 sc18is600
Definition: sc18i600.c:3
unsigned char uint8_t
Definition: types.h:14
uint8_t rx_len
Definition: sc18i600.h:38
void sc18is600_read_from_register(uint8_t addr)
enum Sc18Is600Transaction transaction
Definition: sc18i600.h:35
#define Sc18Is600_Cmd_Read_From_Reg
void exti2_irq_handler(void)
#define Sc18Is600_Cmd_Read_Buffer
#define Sc18Is600Unselect()
Definition: sc18is600_arch.h:4
uint8_t priv_rx_buf[SC18IS600_BUF_LEN]
Definition: sc18i600.h:37
void sc18is600_tranceive(uint8_t addr, uint8_t len_tx, uint8_t len_rx)
void dma1_c4_irq_handler(void)
#define Sc18Is600_Cmd_Write_To_Reg
void sc18is600_receive(uint8_t addr, uint8_t len)
uint8_t priv_tx_buf[SC18IS600_BUF_LEN]
Definition: sc18i600.h:36
#define RESET
Definition: humid_sht.c:62
#define ReadI2CStatReg()
enum Sc18Is600Status status
Definition: sc18i600.h:34
#define Sc18Is600Select()
Definition: sc18is600_arch.h:5