Paparazzi UAS  v5.18.0_stable
Paparazzi is a free software Unmanned Aircraft System.
max11040_hw.c
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2010 Martin Mueller
3  *
4  * This file is part of paparazzi.
5  *
6  * paparazzi is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2, or (at your option)
9  * any later version.
10  *
11  * paparazzi is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with paparazzi; see the file COPYING. If not, write to
18  * the Free Software Foundation, 59 Temple Place - Suite 330,
19  * Boston, MA 02111-1307, USA.
20  *
21  */
22 
30 #include "armVIC.h"
31 #include "max11040_hw.h"
32 #include "adcs/max11040.h"
33 
34 #ifdef LOGGER
35 extern unsigned int getclock(void);
36 #endif
37 
38 volatile uint8_t num_irqs = 0;
39 
40 static void SSP_ISR(void) __attribute__((naked));
41 static void EXTINT_ISR(void) __attribute__((naked));
42 
43 #warning "This driver should be updated to use the new SPI peripheral"
44 
45 #ifndef SPI1_VIC_SLOT
46 #define SPI1_VIC_SLOT 7
47 #endif
48 
49 static void SSP_ISR(void)
50 {
51  int i;
52  ISR_ENTRY();
53 
54  switch (max11040_status) {
55 
56  case MAX11040_RESET: {
57  /* read dummy control byte reply */
58  uint8_t foo __attribute__((unused));
59  foo = SSPDR;
60  foo = SSPDR;
61  /* write configuration register */
62  SSP_Send(0x60); /* wr conf */
63  SSP_Send(0x30); /* adc0: en24bit, xtalen, no faultdis */
64  for (i = 1; i < MAXM_NB_ADCS; i++) {
65  SSP_Send(0x20); /* adcx: en24bit, no xtalen, no faultdis */
66  }
67  max11040_status = MAX11040_CONF;
68  SSP_ClearRti();
69  }
70  break;
71 
72  case MAX11040_CONF: {
73  /* read dummy control byte reply */
74  uint8_t foo __attribute__((unused));
75  foo = SSPDR;
76  for (i = 0; i < MAXM_NB_ADCS; i++) {
77  foo = SSPDR;
78  }
79  /* write sampling instant register */
80  SSP_Send(0x40); /* wr instant */
81  for (i = 0; i < MAXM_NB_ADCS; i++) {
82  SSP_Send(0); /* adcx: no delay */
83  SSP_Send(0);
84  SSP_Send(0);
85  SSP_Send(0);
86  }
87  max11040_status = MAX11040_INSTANT;
88  SSP_ClearRti();
89  }
90  break;
91 
92  case MAX11040_INSTANT: {
93  /* read dummy control byte reply */
94  uint8_t foo __attribute__((unused));
95  foo = SSPDR;
96  for (i = 0; i < MAXM_NB_ADCS; i++) {
97  foo = SSPDR;
98  foo = SSPDR;
99  foo = SSPDR;
100  foo = SSPDR;
101  }
102  /* write data rate control register */
103  SSP_Send(0x50); /* wr rate */
104  SSP_Send(0x26); /* adc: 250.1 sps */
105  SSP_Send(0x00);
106  max11040_status = MAX11040_RATE;
107  SSP_ClearRti();
108  }
109  break;
110 
111  case MAX11040_RATE: {
112  uint8_t foo __attribute__((unused));
113  foo = SSPDR;
114  foo = SSPDR;
115  foo = SSPDR;
116  /* read data register */
117  SSP_Send(0xF0); /* rd data */
118  for (i = 0; i < MAXM_NB_ADCS; i++) {
119  SSP_Send(0x00); /* adcx: data */
120  SSP_Send(0x00);
121  SSP_Send(0x00);
122  SSP_Send(0x00);
123  SSP_Send(0x00);
124  SSP_Send(0x00);
125  SSP_Send(0x00);
126  SSP_Send(0x00);
127  SSP_Send(0x00);
128  SSP_Send(0x00);
129  SSP_Send(0x00);
130  SSP_Send(0x00);
131  }
132  max11040_status = MAX11040_DATA;
133  SSP_ClearRti();
134  }
135  break;
136 
137  case MAX11040_DATA: {
138  uint8_t foo __attribute__((unused));
139  foo = SSPDR;
140  for (i = 0; i < MAXM_NB_ADCS; i++) {
141  foo = SSPDR;
142  foo = SSPDR;
143  foo = SSPDR;
144  foo = SSPDR;
145  foo = SSPDR;
146  foo = SSPDR;
147  foo = SSPDR;
148  foo = SSPDR;
149  foo = SSPDR;
150  foo = SSPDR;
151  foo = SSPDR;
152  foo = SSPDR;
153  }
154 
155  /* read data */
156  /* read data register */
157  SSP_Send(0xF0); /* rd data */
158  for (i = 0; i < MAXM_NB_ADCS; i++) {
159  SSP_Send(0x00); /* adc0: data */
160  SSP_Send(0x00);
161  SSP_Send(0x00);
162  SSP_Send(0x00);
163  SSP_Send(0x00);
164  SSP_Send(0x00);
165  SSP_Send(0x00);
166  SSP_Send(0x00);
167  SSP_Send(0x00);
168  SSP_Send(0x00);
169  SSP_Send(0x00);
170  SSP_Send(0x00);
171  }
172 
173  SSP_ClearRti();
174  }
175  break;
176 
177  case MAX11040_DATA2: {
178  uint8_t foo __attribute__((unused));
179 
180  SSP_ClearRti();
181  SSP_ClearRxi();
182 
183  if (max11040_count <= MAXM_NB_CHAN + 2) {
184  SSP_Send(0x00);
185  SSP_Send(0x00);
186  SSP_Send(0x00);
187  SSP_Send(0x00);
188  SSP_Send(0x00);
189  SSP_Send(0x00);
190  }
191 
192  if (max11040_count == 0) { foo = SSPDR; }
193 
194  max11040_values[max11040_buf_in][max11040_count] = SSPDR << 16;
195  max11040_values[max11040_buf_in][max11040_count] |= SSPDR << 8;
196  max11040_values[max11040_buf_in][max11040_count] |= SSPDR;
197  if (max11040_values[max11040_buf_in][max11040_count] & 0x800000) {
198  max11040_values[max11040_buf_in][max11040_count] |= 0xFF000000;
199  }
200 
201  max11040_count++;
202 
203  max11040_values[max11040_buf_in][max11040_count] = SSPDR << 16;
204  max11040_values[max11040_buf_in][max11040_count] |= SSPDR << 8;
205  max11040_values[max11040_buf_in][max11040_count] |= SSPDR;
206  if (max11040_values[max11040_buf_in][max11040_count] & 0x800000) {
207  max11040_values[max11040_buf_in][max11040_count] |= 0xFF000000;
208  }
209 
210  max11040_count++;
211 
212  if (max11040_count == MAXM_NB_CHAN) {
213  MaxmUnselect();
214  max11040_data = MAX11040_DATA_AVAILABLE;
215  i = max11040_buf_in + 1;
216  if (i >= MAX11040_BUF_SIZE) { i = 0; }
217  if (i != max11040_buf_out) {
218  max11040_buf_in = i;
219  } else {
220  //throw error;
221  }
222  }
223  }
224  break;
225 
226  }
227 
228  VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
229  ISR_EXIT();
230 }
231 
232 void EXTINT_ISR(void)
233 {
234  ISR_ENTRY();
235 
236  if (num_irqs++ == 5) {
237  /* switch SSEL P0.20 to be used as GPIO */
238  PINSEL1 &= ~(3 << 8);
239  IO0DIR |= 1 << 20;
240  max11040_status = MAX11040_DATA2;
241  }
242 
243  if (max11040_status == MAX11040_DATA2) {
244 
245 #ifdef LOGGER
246  max11040_timestamp[max11040_buf_in] = getclock();
247 #endif
248 
249  MaxmSelect();
250 
251  /* read data */
252  SSP_Send(0xF0);
253  SSP_Send(0x00);
254  SSP_Send(0x00);
255  SSP_Send(0x00);
256  SSP_Send(0x00);
257  SSP_Send(0x00);
258  SSP_Send(0x00);
259 
260  max11040_count = 0;
261  }
262 
263  /* clear EINT */
264  SetBit(EXTINT, MAXM_DRDY_EINT);
265 
266  VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
267  ISR_EXIT();
268 }
269 
270 
271 void max11040_hw_init(void)
272 {
273  int i;
274 
275  /* *** configure SPI *** */
276  /* setup pins for SSP (SCK, MISO, MOSI, SSEL) */
277  PINSEL1 |= SSP_PINSEL1_SCK | SSP_PINSEL1_MISO | SSP_PINSEL1_MOSI | SSP_PINSEL1_SSEL;
278 
279  /* setup SSP */
280  SSPCR0 = SSPCR0_VAL;;
281  SSPCR1 = SSPCR1_VAL;
282  SSPCPSR = 0x02;
283 
284  /* initialize interrupt vector */
285  VICIntSelect &= ~VIC_BIT(VIC_SPI1); /* SPI1 selected as IRQ */
286  VICIntEnable = VIC_BIT(VIC_SPI1); /* enable it */
287  _VIC_CNTL(SPI1_VIC_SLOT) = VIC_ENABLE | VIC_SPI1;
288  _VIC_ADDR(SPI1_VIC_SLOT) = (uint32_t)SSP_ISR; /* address of the ISR */
289 
290 
291  /* *** configure DRDY pin*** */
292  /* connected pin to EXINT */
293  MAXM_DRDY_PINSEL |= MAXM_DRDY_PINSEL_VAL << MAXM_DRDY_PINSEL_BIT;
294  SetBit(EXTMODE, MAXM_DRDY_EINT); /* EINT is edge trigered */
295  ClearBit(EXTPOLAR, MAXM_DRDY_EINT); /* EINT is trigered on falling edge */
296  SetBit(EXTINT, MAXM_DRDY_EINT); /* clear pending EINT */
297 
298  /* initialize interrupt vector */
299  VICIntSelect &= ~VIC_BIT(MAXM_DRDY_VIC_IT); /* select EINT as IRQ source */
300  VICIntEnable = VIC_BIT(MAXM_DRDY_VIC_IT); /* enable it */
301  _VIC_CNTL(MAX11040_DRDY_VIC_SLOT) = VIC_ENABLE | MAXM_DRDY_VIC_IT;
302  _VIC_ADDR(MAX11040_DRDY_VIC_SLOT) = (uint32_t)EXTINT_ISR; /* address of the ISR */
303 
304 
305  /* write configuration register */
306  SSP_Send(0x60); /* wr conf */
307  for (i = 0; i < MAXM_NB_ADCS; i++) {
308  SSP_Send(0x40); /* adcx: reset */
309  }
310  SSP_Enable();
311  SSP_ClearRti();
312  SSP_EnableRti();
313 }
314 
max11040_timestamp
volatile uint32_t max11040_timestamp[MAX11040_BUF_SIZE]
Definition: max11040.c:38
SSPCR1
#define SSPCR1
Definition: LPC21xx.h:223
max11040_status
volatile uint8_t max11040_status
Definition: max11040.c:35
max11040_buf_in
volatile uint32_t max11040_buf_in
Definition: max11040.c:40
armVIC.h
VICIntSelect
#define VICIntSelect
Definition: LPC21xx.h:430
VIC_SPI1
#define VIC_SPI1
Definition: lpcVIC.h:81
SSPCR0
#define SSPCR0
Definition: LPC21xx.h:222
EXTMODE
#define EXTMODE
Definition: LPC21xx.h:419
SSP_Send
#define SSP_Send(_a)
Definition: ssp_hw.h:16
SSPCPSR
#define SSPCPSR
Definition: LPC21xx.h:226
uint32_t
unsigned long uint32_t
Definition: types.h:18
SSP_PINSEL1_MOSI
#define SSP_PINSEL1_MOSI
Definition: spi_arch.c:387
MAX11040_DATA_AVAILABLE
#define MAX11040_DATA_AVAILABLE
Definition: max11040.h:29
SSPCR0_VAL
#define SSPCR0_VAL
Definition: spi_slave_hs_arch.c:60
_VIC_ADDR
#define _VIC_ADDR(idx)
Definition: armVIC.h:20
foo
uint16_t foo
Definition: main_demo5.c:59
MAX11040_DATA
#define MAX11040_DATA
Definition: max11040.h:25
MAX11040_BUF_SIZE
#define MAX11040_BUF_SIZE
Definition: max11040.h:9
max11040_hw_init
void max11040_hw_init(void)
Definition: max11040_hw.c:271
max11040.h
SSP_ClearRti
#define SSP_ClearRti()
Definition: max11040_hw.h:53
VIC_BIT
#define VIC_BIT(chan)
Definition: lpcVIC.h:105
EXTINT
#define EXTINT
Definition: LPC21xx.h:417
MAX11040_RESET
#define MAX11040_RESET
Definition: max11040.h:20
MAXM_NB_ADCS
#define MAXM_NB_ADCS
Definition: max11040.h:8
SPI1_VIC_SLOT
#define SPI1_VIC_SLOT
Definition: max11040_hw.c:46
max11040_data
volatile uint8_t max11040_data
Definition: max11040.c:36
MaxmUnselect
#define MaxmUnselect()
Definition: max11040_hw.h:56
uint8_t
unsigned char uint8_t
Definition: types.h:14
MAXM_NB_CHAN
#define MAXM_NB_CHAN
Definition: max11040.h:7
VICVectAddr
#define VICVectAddr
Definition: LPC21xx.h:436
EXTPOLAR
#define EXTPOLAR
Definition: LPC21xx.h:420
num_irqs
volatile uint8_t num_irqs
Definition: max11040_hw.c:38
IO0DIR
#define IO0DIR
Definition: LPC21xx.h:335
SSP_ISR
static void SSP_ISR(void)
Definition: max11040_hw.c:49
max11040_hw.h
MAX11040_RATE
#define MAX11040_RATE
Definition: max11040.h:23
max11040_values
volatile int32_t max11040_values[MAX11040_BUF_SIZE][MAXM_NB_CHAN]
Definition: max11040.c:37
ISR_ENTRY
#define ISR_ENTRY()
Definition: armVIC.h:40
SSP_ClearRxi
#define SSP_ClearRxi()
Definition: max11040_hw.h:47
ISR_EXIT
#define ISR_EXIT()
Definition: armVIC.h:61
MAX11040_INSTANT
#define MAX11040_INSTANT
Definition: max11040.h:22
SSPCR1_VAL
#define SSPCR1_VAL
Definition: spi_slave_hs_arch.c:68
SSP_PINSEL1_MISO
#define SSP_PINSEL1_MISO
Definition: spi_arch.c:386
SSPDR
#define SSPDR
Definition: LPC21xx.h:224
VIC_ENABLE
#define VIC_ENABLE
Definition: lpcVIC.h:102
MAX11040_CONF
#define MAX11040_CONF
Definition: max11040.h:21
SSP_PINSEL1_SSEL
#define SSP_PINSEL1_SSEL
Definition: spi_arch.c:388
VICIntEnable
#define VICIntEnable
Definition: LPC21xx.h:431
SSP_Enable
#define SSP_Enable()
Definition: max11040_hw.h:43
PINSEL1
#define PINSEL1
Definition: LPC21xx.h:348
EXTINT_ISR
static void EXTINT_ISR(void)
Definition: max11040_hw.c:232
max11040_count
volatile uint8_t max11040_count
Definition: max11040.c:39
max11040_buf_out
volatile uint32_t max11040_buf_out
Definition: max11040.c:41
SSP_EnableRti
#define SSP_EnableRti()
Definition: max11040_hw.h:51
MaxmSelect
#define MaxmSelect()
Definition: max11040_hw.h:55
_VIC_CNTL
#define _VIC_CNTL(idx)
Definition: armVIC.h:19
MAX11040_DATA2
#define MAX11040_DATA2
Definition: max11040.h:26
SSP_PINSEL1_SCK
#define SSP_PINSEL1_SCK
Definition: spi_arch.c:385