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ist8310_regs.h
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1 /*
2  * Copyright (C) 2019 Freek van Tienen <freek.v.tienen@gmail.com>
3  *
4  * This file is part of paparazzi.
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20  */
21 
28 #ifndef IST8310_REGS_H
29 #define IST8310_REGS_H
30 
31 #define IST8310_ADDR 0x1C
32 
33 /* IST8310 register address */
34 #define IST8310_REG_WHO_AM_I 0x00
35 #define IST8310_REG_STAT1 0x02
36 #define IST8310_REG_DATA_XL 0x03
37 #define IST8310_REG_DATA_XH 0x04
38 #define IST8310_REG_DATA_YL 0x05
39 #define IST8310_REG_DATA_YM 0x06
40 #define IST8310_REG_DATA_ZL 0x07
41 #define IST8310_REG_DATA_ZM 0x08
42 #define IST8310_REG_STAT2 0x09
43 #define IST8310_REG_CNTL1 0x0A
44 #define IST8310_REG_CNTL2 0x0B
45 #define IST8310_REG_STR 0x0C
46 #define IST8310_REG_TEMPL 0x1C
47 #define IST8310_REG_TEMPH 0x1D
48 #define IST8310_REG_CNTL3 0x41
49 #define IST8310_REG_CNTL4 0x42
50 #define IST8310_REG_Y11L 0x9C
51 #define IST8310_REG_Y11H 0x9D
52 #define IST8310_REG_Y12L 0x9E
53 #define IST8310_REG_Y12H 0x9F
54 #define IST8310_REG_Y13L 0xA0
55 #define IST8310_REG_Y13H 0xA1
56 #define IST8310_REG_Y21L 0xA2
57 #define IST8310_REG_Y21H 0xA3
58 #define IST8310_REG_Y22L 0xA4
59 #define IST8310_REG_Y22H 0xA5
60 #define IST8310_REG_Y23L 0xA6
61 #define IST8310_REG_Y23H 0xA7
62 #define IST8310_REG_Y31L 0xA8
63 #define IST8310_REG_Y31H 0xA9
64 #define IST8310_REG_Y32L 0xAA
65 #define IST8310_REG_Y32H 0xAB
66 #define IST8310_REG_Y33L 0xAC
67 #define IST8310_REG_Y33H 0xAD
68 
69 /* STAT1 register values */
70 #define IST8310_STAT1_DRDY (1 << 0)
71 #define IST8310_STAT1_DOR (1 << 1)
72 
73 /* STAT2 register values */
74 #define IST8310_STAT2_INT (1 << 3)
75 
76 /* CNTL1 register options */
77 #define IST8310_CNTL1_ODR_SINGLE 0x01
78 #define IST8310_CNTL1_ODR_10HZ 0x03
79 #define IST8310_CNTL1_ODR_20HZ 0x05
80 #define IST8310_CNTL1_ODR_50HZ 0x07
81 #define IST8310_CNTL1_ODR_100HZ 0x06
82 
83 /* CNTL2 register settings */
84 #define IST8310_CNTL2_SRST (1 << 0)
85 #define IST8310_CNTL2_DRP (1 << 2)
86 #define IST8310_CNTL2_DREN (1 << 3)
87 
88 /* STR register settings (Self test) */
89 #define IST8310_STR_ENABLE (1 << 6)
90 
91 /* CNTL3 register options (Amount of samples to average) */
92 #define IST8310_CNTL3_SAMPAVG_16 0x24
93 #define IST8310_CNTL3_SAMPAVG_8 0x1B
94 #define IST8310_CNTL3_SAMPAVG_4 0x12
95 #define IST8310_CNTL3_SAMPAVG_2 0x09
96 #define IST8310_CNTL3_SAMPAVG_0 0x00
97 
98 /* CNTL4 register options (Set reset pulse duration) */
99 #define IST8310_CNTL4_SRPD 0xC0
100 
101 #endif /* IST8310_REGS_H */