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lsm303dlhc_regs.h
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1 /*
2  * Copyright (C) 2014 Federico Ruiz Ugalde
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4  * This file is part of paparazzi.
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21 
27 #ifndef LSM303DLHC_REGS_H
28 #define LSM303DLHC_REGS_H
29 
30 /* default I2C address */
31 #define LSM303DLHC_ACC_ADDR 0x32
32 #define LSM303DLHC_MAG_ADDR 0x3C
33 
34 /* Registers */
35 
36 //checked:
37 #define LSM303DLHC_REG_TEMP_OUT_L_M 0x05
38 #define LSM303DLHC_REG_TEMP_OUT_H_M 0x06
39 
40 #define LSM303DLHC_REG_STATUS_REG_M 0x07
41 #define LSM303DLHC_REG_OUT_X_L_M 0x08
42 #define LSM303DLHC_REG_OUT_X_H_M 0x09
43 #define LSM303DLHC_REG_OUT_Y_L_M 0x0A
44 #define LSM303DLHC_REG_OUT_Y_H_M 0x0B
45 #define LSM303DLHC_REG_OUT_Z_L_M 0x0C
46 #define LSM303DLHC_REG_OUT_Z_H_M 0x0D
47 
48 #define LSM303DLHC_REG_WHO_AM_I 0x0F
49 
50 #define LSM303DLHC_REG_INT_CTRL_M 0x12
51 #define LSM303DLHC_REG_INT_SRC_M 0x13
52 #define LSM303DLHC_REG_INT_THS_L_M 0x14
53 #define LSM303DLHC_REG_INT_THS_H_M 0x15
54 #define LSM303DLHC_REG_OFFSET_X_L_M 0x16
55 #define LSM303DLHC_REG_OFFSET_X_H_M 0x17
56 #define LSM303DLHC_REG_OFFSET_Y_L_M 0x18
57 #define LSM303DLHC_REG_OFFSET_Y_H_M 0x19
58 #define LSM303DLHC_REG_OFFSET_Z_L_M 0x1A
59 #define LSM303DLHC_REG_OFFSET_Z_H_M 0x1B
60 #define LSM303DLHC_REG_REFERENCE_X 0x1C
61 #define LSM303DLHC_REG_REFERENCE_Y 0x1D
62 #define LSM303DLHC_REG_REFERENCE_Z 0x1E
63 #define LSM303DLHC_REG_CTRL0 0x1F
64 #define LSM303DLHC_REG_CTRL1 0x20
65 #define LSM303DLHC_REG_CTRL2 0x21
66 #define LSM303DLHC_REG_CTRL3 0x22
67 #define LSM303DLHC_REG_CTRL4 0x23
68 #define LSM303DLHC_REG_CTRL5 0x24
69 #define LSM303DLHC_REG_CTRL6 0x25
70 #define LSM303DLHC_REG_CTRL7 0x26
71 
72 #define LSM303DLHC_REG_STATUS_REG_A 0x27
73 #define LSM303DLHC_REG_OUT_X_L_A 0x28
74 #define LSM303DLHC_REG_OUT_X_H_A 0x29
75 #define LSM303DLHC_REG_OUT_Y_L_A 0x2A
76 #define LSM303DLHC_REG_OUT_Y_H_A 0x2B
77 #define LSM303DLHC_REG_OUT_Z_L_A 0x2C
78 #define LSM303DLHC_REG_OUT_Z_H_A 0x2D
79 
80 #define LSM303DLHC_REG_FIFO_CTRL 0x2E
81 #define LSM303DLHC_REG_FIFO_SRC 0x2F
82 #define LSM303DLHC_REG_INT_CFG 0x30
83 #define LSM303DLHC_REG_INT_SRC1 0x31
84 #define LSM303DLHC_REG_INT_THS1 0x32
85 #define LSM303DLHC_REG_INT_DUR1 0x33
86 #define LSM303DLHC_REG_INT_CFG2 0x34
87 #define LSM303DLHC_REG_INT_SRC2 0x35
88 #define LSM303DLHC_REG_INT_THS2 0x36
89 #define LSM303DLHC_REG_INT_DUR2 0x37
90 #define LSM303DLHC_REG_CLICK_CFG 0x38
91 #define LSM303DLHC_REG_CLICK_SRC 0x39
92 #define LSM303DLHC_REG_CLICK_THS 0x3A
93 #define LSM303DLHC_REG_TIME_LIMIT 0x3B
94 #define LSM303DLHC_REG_TIME_LATENCY 0x3C
95 #define LSM303DLHC_REG_TIME_WINDOW 0x3D
96 #define LSM303DLHC_ACT_THS 0x3E
97 #define LSM303DLHC_ACT_DUR 0x3F
98 
99 #define LSM303DLHC_REG_STATUS_ZYXADA 0x08
100 #define LSM303DLHC_REG_STATUS_ZYXMDA 0x08
101 
102 #define LSM303DLHC_WHO_I_AM 0x49
103 
104 /* Bit definitions */
105 //CTRL1
106 #define LSM303DLHC_Xen (0x01 << 0)
107 #define LSM303DLHC_Yen (0x01 << 1)
108 #define LSM303DLHC_Zen (0x01 << 2)
109 #define LSM303DLHC_BDU (0x01 << 3)
110 #define LSM303DLHC_AODR_MASK (0x0F << 4)
111 
112 //CTRL2
113 #define LSM303DLHC_SIM (0x01 << 0)
114 #define LSM303DLHC_AST (0x01 << 1)
115 #define LSM303DLHC_FS_MASK (0x07 << 3)
116 #define LSM303DLHC_ABW_MASK (0x03 << 6)
117 
118 //CTRL3
119 #define LSM303DLHC_I1_DRDY_A (0x01 << 2)
120 //TODO: more CTRL3 regs
121 
122 //CTRL4
123 #define LSM303DLHC_I2_DRDY_A (0x01 << 3)
124 #define LSM303DLHC_I2_DRDY_M (0x01 << 2)
125 //TODO: more CTRL4 regs
126 
127 //CTRL5
128 #define LSM303DLHC_TEMP_EN (0x01 << 7)
129 #define LSM303DLHC_M_RES (0x07 << 5) // only two modes, so no mask
130 #define LSM303DLHC_M_ODR_MASK (0x15 << 2)
131 #define LSM303DLHC_M_LIR_MASK (0x7 << 0)
132 
133 //CTRL6
134 #define LSM303DLHC_MFS_MASK (0x07 << 5)
135 
136 //CTRL7
137 #define LSM303DLHC_AHPM_MASK (0x07 << 6)
138 #define LSM303DLHC_AFDS (0x01 << 5)
139 #define LSM303DLHC_T_ONLY (0x01 << 4)
140 #define LSM303DLHC_MLP (0x01 << 2)
141 #define LSM303DLHC_MD_MASK (0x07 << 0)
142 
143 #endif // LSM303DLHC_REGS_H