Paparazzi UAS
v7.0_unstable
Paparazzi is a free software Unmanned Aircraft System.
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invensense3_regs.h
Go to the documentation of this file.
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/*
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* Copyright (C) 2022 Freek van Tienen <freek.v.tienen@gmail.com>
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*
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* This file is part of paparazzi.
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*
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* paparazzi is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* paparazzi is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with paparazzi; see the file COPYING. If not, write to
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* the Free Software Foundation, 59 Temple Place - Suite 330,
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* Boston, MA 02111-1307, USA.
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*/
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#ifndef INVENSENSE3_REGS_H
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#define INVENSENSE3_REGS_H
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#define INV3_BANK0 0x00U
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#define INV3_BANK1 0x01U
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#define INV3_BANK2 0x02U
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#define INV3_BANK3 0x03U
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#define INV3REG(b, r) ((((uint16_t)b) << 8)|(r))
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#define INV3_READ_FLAG 0x80
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//Register Map
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#define INV3REG_DEVICE_CONFIG INV3REG(INV3_BANK0,0x11U)
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# define BIT_DEVICE_CONFIG_SOFT_RESET_CONFIG 0x01
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# define BIT_DEVICE_CONFIG_SPI_MODE 0x10
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#define INV3REG_FIFO_CONFIG INV3REG(INV3_BANK0,0x16U)
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# define FIFO_CONFIG_MODE_BYPASS 0x00
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# define FIFO_CONFIG_MODE_STREAM_TO_FIFO 0x01
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# define FIFO_CONFIG_MODE_STOP_ON_FULL 0x02
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# define FIFO_CONFIG_MODE_SHIFT 0x06
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#define INV3REG_TEMP_DATA1 INV3REG(INV3_BANK0,0x1DU)
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#define INV3REG_ACCEL_DATA_X1 INV3REG(INV3_BANK0,0x1FU)
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#define INV3REG_INT_STATUS INV3REG(INV3_BANK0,0x2DU)
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#define INV3REG_FIFO_COUNTH INV3REG(INV3_BANK0,0x2EU)
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#define INV3REG_FIFO_COUNTL INV3REG(INV3_BANK0,0x2FU)
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#define INV3REG_FIFO_DATA INV3REG(INV3_BANK0,0x30U)
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#define INV3REG_SIGNAL_PATH_RESET INV3REG(INV3_BANK0,0x4BU)
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# define BIT_SIGNAL_PATH_RESET_FIFO_FLUSH 0x02
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# define BIT_SIGNAL_PATH_RESET_TMST_STROBE 0x04
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# define BIT_SIGNAL_PATH_RESET_ABORT_AND_RESET 0x08
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# define BIT_SIGNAL_PATH_RESET_DMP_MEM_RESET_EN 0x20
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# define BIT_SIGNAL_PATH_RESET_DMP_INIT_EN 0x40
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#define INV3REG_INTF_CONFIG0 INV3REG(INV3_BANK0,0x4CU)
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# define UI_SIFS_CFG_SPI_DIS 0x02
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# define UI_SIFS_CFG_I2C_DIS 0x03
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# define UI_SIFS_CFG_SHIFT 0x00
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# define SENSOR_DATA_BIG_ENDIAN 0x10
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# define FIFO_COUNT_BIG_ENDIAN 0x20
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# define FIFO_COUNT_REC 0x40
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# define FIFO_HOLD_LAST_DATA_EN 0x80
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#define INV3REG_INTF_CONFIG1 INV3REG(INV3_BANK0,0x4DU)
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#define INV3REG_PWR_MGMT0 INV3REG(INV3_BANK0,0x4EU)
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# define ACCEL_MODE_OFF 0x00
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# define ACCEL_MODE_LN 0x03
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# define ACCEL_MODE_SHIFT 0x00
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# define GYRO_MODE_OFF 0x00
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# define GYRO_MODE_LN 0x03
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# define GYRO_MODE_SHIFT 0x02
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# define BIT_PWR_MGMT_IDLE 0x08
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# define BIT_PWM_MGMT_TEMP_DIS 0x10
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#define INV3REG_GYRO_CONFIG0 INV3REG(INV3_BANK0,0x4FU)
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# define GYRO_ODR_32KHZ 0x01
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# define GYRO_ODR_16KHZ 0x02
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# define GYRO_ODR_8KHZ 0x03
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# define GYRO_ODR_4KHZ 0x04
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# define GYRO_ODR_2KHZ 0x05
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# define GYRO_ODR_1KHZ 0x06
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# define GYRO_ODR_200HZ 0x07
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# define GYRO_ODR_100HZ 0x08
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# define GYRO_ODR_50HZ 0x09
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# define GYRO_ODR_25HZ 0x0A
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# define GYRO_ODR_12_5HZ 0x0B
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# define GYRO_ODR_500HZ 0x0F
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# define GYRO_ODR_SHIFT 0x00
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# define GYRO_FS_SEL_2000DPS 0x00
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# define GYRO_FS_SEL_1000DPS 0x01
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# define GYRO_FS_SEL_500DPS 0x02
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# define GYRO_FS_SEL_250DPS 0x03
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# define GYRO_FS_SEL_125DPS 0x04
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# define GYRO_FS_SEL_62_5DPS 0x05
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# define GYRO_FS_SEL_31_25DPS 0x06
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# define GYRO_FS_SEL_15_625DPS 0x07
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# define GYRO_FS_SEL_SHIFT 0x05
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#define INV3REG_ACCEL_CONFIG0 INV3REG(INV3_BANK0,0x50U)
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# define ACCEL_ODR_32KHZ 0x01
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# define ACCEL_ODR_16KHZ 0x02
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# define ACCEL_ODR_8KHZ 0x03
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# define ACCEL_ODR_4KHZ 0x04
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# define ACCEL_ODR_2KHZ 0x05
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# define ACCEL_ODR_1KHZ 0x06
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# define ACCEL_ODR_200HZ 0x07
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# define ACCEL_ODR_100HZ 0x08
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# define ACCEL_ODR_50HZ 0x09
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# define ACCEL_ODR_25HZ 0x0A
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# define ACCEL_ODR_12_5HZ 0x0B
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# define ACCEL_ODR_6_25HZ 0x0C
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# define ACCEL_ODR_3_125HZ 0x0D
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# define ACCEL_ODR_1_5625HZ 0x0E
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# define ACCEL_ODR_500HZ 0x0F
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# define ACCEL_ODR_SHIFT 0x00
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# define ACCEL_FS_SEL_16G 0x00
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# define ACCEL_FS_SEL_8G 0x01
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# define ACCEL_FS_SEL_4G 0x02
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# define ACCEL_FS_SEL_2G 0x03
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# define ACCEL_FS_SEL_SHIFT 0x05
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#define INV3REG_GYRO_CONFIG1 INV3REG(INV3_BANK0,0x51U)
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#define INV3REG_GYRO_ACCEL_CONFIG0 INV3REG(INV3_BANK0,0x52U)
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#define INV3REG_ACCEL_CONFIG1 INV3REG(INV3_BANK0,0x53U)
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#define INV3REG_TMST_CONFIG INV3REG(INV3_BANK0,0x54U)
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# define BIT_TMST_CONFIG_TMST_EN 0x01
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#define INV3REG_FIFO_CONFIG1 INV3REG(INV3_BANK0,0x5FU)
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# define BIT_FIFO_CONFIG1_ACCEL_EN 0x01
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# define BIT_FIFO_CONFIG1_GYRO_EN 0x02
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# define BIT_FIFO_CONFIG1_TEMP_EN 0x04
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# define BIT_FIFO_CONFIG1_TMST_FSYNC_EN 0x08
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# define BIT_FIFO_CONFIG1_HIRES_EN 0x10
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# define BIT_FIFO_CONFIG1_WM_GT_TH 0x20
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# define BIT_FIFO_CONFIG1_RESUME_PARTIAL_RD 0x40
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#define INV3REG_FIFO_CONFIG2 INV3REG(INV3_BANK0,0x60U)
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#define INV3REG_FIFO_CONFIG3 INV3REG(INV3_BANK0,0x61U)
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#define INV3REG_INT_SOURCE0 INV3REG(INV3_BANK0,0x65U)
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#define INV3REG_INT_SOURCE3 INV3REG(INV3_BANK0,0x68U)
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# define BIT_FIFO_FULL_INT_EN 0x02
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# define BIT_FIFO_THS_INT_EN 0x04
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# define BIT_UI_DRDY_INT_EN 0x08
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#define INV3REG_INT_CONFIG1 INV3REG(INV3_BANK0,0x64U)
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# define BIT_INT_ASYNC_RESET 0x10
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#define INV3REG_WHO_AM_I INV3REG(INV3_BANK0,0x75U)
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#define INV3REG_GYRO_CONFIG_STATIC2 INV3REG(INV3_BANK1,0x0BU)
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# define BIT_GYRO_NF_DIS 0x01
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# define BIT_GYRO_AAF_DIS 0x02
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#define INV3REG_GYRO_CONFIG_STATIC3 INV3REG(INV3_BANK1,0x0CU)
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# define GYRO_AAF_DELT_SHIFT 0x00
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#define INV3REG_GYRO_CONFIG_STATIC4 INV3REG(INV3_BANK1,0x0DU)
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# define GYRO_AAF_DELTSQR_LOW_SHIFT 0x00
//[0:7]
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#define INV3REG_GYRO_CONFIG_STATIC5 INV3REG(INV3_BANK1,0x0EU)
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# define GYRO_AAF_DELTSQR_HIGH_SHIFT 0x00
//[11:8]
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# define GYRO_AAF_BITSHIFT_SHIFT 0x04
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#define INV3REG_GYRO_CONFIG_STATIC6 INV3REG(INV3_BANK1,0x0FU)
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# define GYRO_X_NF_COSWZ_LOW_SHIFT 0x00
//[0:7]
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#define INV3REG_GYRO_CONFIG_STATIC7 INV3REG(INV3_BANK1,0x10U)
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# define GYRO_Y_NF_COSWZ_LOW_SHIFT 0x00
//[0:7]
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#define INV3REG_GYRO_CONFIG_STATIC8 INV3REG(INV3_BANK1,0x11U)
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# define GYRO_Z_NF_COSWZ_LOW_SHIFT 0x00
//[0:7]
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#define INV3REG_GYRO_CONFIG_STATIC9 INV3REG(INV3_BANK1,0x12U)
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# define GYRO_X_NF_COSWZ_HIGH_SHIFT 0x00
//[8]
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# define GYRO_Y_NF_COSWZ_HIGH_SHIFT 0x01
//[8]
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# define GYRO_Z_NF_COSWZ_HIGH_SHIFT 0x02
//[8]
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# define GYRO_X_NF_COSWZ_SEL_SHIFT 0x03
//[0]
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# define GYRO_Y_NF_COSWZ_SEL_SHIFT 0x04
//[0]
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# define GYRO_Z_NF_COSWZ_SEL_SHIFT 0x05
//[0]
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#define INV3REG_GYRO_CONFIG_STATIC10 INV3REG(INV3_BANK1,0x13U)
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# define GYRO_NF_BW_SEL_SHIFT 0x04
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#define INV3REG_ACCEL_CONFIG_STATIC2 INV3REG(INV3_BANK2,0x03U)
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# define ACCEL_AAF_DIS 0x01
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# define ACCEL_AAF_DELT_SHIFT 0x01
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#define INV3REG_ACCEL_CONFIG_STATIC3 INV3REG(INV3_BANK2,0x04U)
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# define ACCEL_AAF_DELTSQR_LOW_SHIFT 0x00
//[0:7]
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#define INV3REG_ACCEL_CONFIG_STATIC4 INV3REG(INV3_BANK2,0x05U)
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# define ACCEL_AAF_DELTSQR_HIGH_SHIFT 0x00
//[11:8]
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# define ACCEL_AAF_BITSHIFT_SHIFT 0x04
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#define INV3REG_BANK_SEL 0x76
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// WHOAMI values
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#define INV3_WHOAMI_ICM40605 0x33
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#define INV3_WHOAMI_ICM40609 0x3b
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#define INV3_WHOAMI_ICM42605 0x42
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#define INV3_WHOAMI_ICM42688 0x47
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#define INV3_WHOAMI_IIM42652 0x6f
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#define INV3_WHOAMI_ICM42670 0x67
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#endif
/* INVENSENSE3_REGS_H */
sw
airborne
peripherals
invensense3_regs.h
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