|
| #define | BOARD_CHIMERA |
| |
| #define | BOARD_NAME "Chimera Autopilot" |
| |
| #define | STM32_LSECLK 32768U |
| |
| #define | STM32_LSEDRV (3U << 3U) |
| |
| #define | STM32_HSECLK 16000000U |
| |
| #define | STM32_VDD 300U |
| |
| #define | STM32F767xx |
| |
| #define | AUX3 0U |
| |
| #define | RC1_UART4_RX 1U |
| |
| #define | AUX2 2U |
| |
| #define | AUX1 3U |
| |
| #define | VBAT_MEAS 4U |
| |
| #define | AUX0 5U |
| |
| #define | SRV0_TIM3_CH1 6U |
| |
| #define | SRV1_TIM3_CH2 7U |
| |
| #define | XB_ASSO 8U |
| |
| #define | USB_VBUS 9U |
| |
| #define | SD_DETECT 10U |
| |
| #define | OTG_FS_DM 11U |
| |
| #define | OTG_FS_DP 12U |
| |
| #define | SWDIO 13U |
| |
| #define | SWCLK 14U |
| |
| #define | SPI1_CS 15U |
| |
| #define | SRV2_TIM3_CH3 0U |
| |
| #define | SRV3_TIM3_CH4 1U |
| |
| #define | RC1 2U |
| |
| #define | SPI1_SCK 3U |
| |
| #define | SPI1_MISO 4U |
| |
| #define | SPI1_MOSI 5U |
| |
| #define | USART1_TX 6U |
| |
| #define | USART1_RX 7U |
| |
| #define | I2C1_SCL 8U |
| |
| #define | I2C1_SDA 9U |
| |
| #define | I2C2_SCL 10U |
| |
| #define | I2C2_SDA 11U |
| |
| #define | LED1 12U |
| |
| #define | LED2 13U |
| |
| #define | DIS_C 14U |
| |
| #define | DIS_DP 15U |
| |
| #define | PC00 0U |
| |
| #define | PC01 1U |
| |
| #define | AUX5 2U |
| |
| #define | AUX4 3U |
| |
| #define | EN_COMP 4U |
| |
| #define | PC05 5U |
| |
| #define | AUX6 6U |
| |
| #define | AUX7 7U |
| |
| #define | SDMMC1_D0 8U |
| |
| #define | SDMMC1_D1 9U |
| |
| #define | SDMMC1_D2 10U |
| |
| #define | SDMMC1_D3 11U |
| |
| #define | SDMMC1_CK 12U |
| |
| #define | PC13 13U |
| |
| #define | OSC32_IN 14U |
| |
| #define | OSC32_OUT 15U |
| |
| #define | CAN1_RX 0U |
| |
| #define | CAN1_TX 1U |
| |
| #define | SDMMC1_CMD 2U |
| |
| #define | USART2_CTS 3U |
| |
| #define | USART2_RTS 4U |
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| #define | USART2_TX 5U |
| |
| #define | USART2_RX 6U |
| |
| #define | IMU_INT 7U |
| |
| #define | USART3_TX 8U |
| |
| #define | USART3_RX 9U |
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| #define | LED3 10U |
| |
| #define | LED4 11U |
| |
| #define | SRV4_TIM4_CH1 12U |
| |
| #define | SRV5_TIM4_CH2 13U |
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| #define | SRV6_TIM4_CH3 14U |
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| #define | SRV7_TIM4_CH4 15U |
| |
| #define | UART8_RX 0U |
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| #define | UART8_TX 1U |
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| #define | DIS_G 2U |
| |
| #define | DIS_F 3U |
| |
| #define | DIS_A 4U |
| |
| #define | DIS_B 5U |
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| #define | APSW 6U |
| |
| #define | RC2_UART7_RX 7U |
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| #define | DIS_E 8U |
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| #define | DIS_D 9U |
| |
| #define | PE10 10U |
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| #define | PE11 11U |
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| #define | PE12 12U |
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| #define | PE13 13U |
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| #define | PE14 14U |
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| #define | XB_RST 15U |
| |
| #define | PF00 0U |
| |
| #define | PF01 1U |
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| #define | PF02 2U |
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| #define | PF03 3U |
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| #define | PF04 4U |
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| #define | PF05 5U |
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| #define | PF06 6U |
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| #define | PF07 7U |
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| #define | PF08 8U |
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| #define | PF09 9U |
| |
| #define | PF10 10U |
| |
| #define | PF11 11U |
| |
| #define | PF12 12U |
| |
| #define | PF13 13U |
| |
| #define | PF14 14U |
| |
| #define | PF15 15U |
| |
| #define | PG00 0U |
| |
| #define | PG01 1U |
| |
| #define | PG02 2U |
| |
| #define | PG03 3U |
| |
| #define | PG04 4U |
| |
| #define | PG05 5U |
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| #define | PG06 6U |
| |
| #define | PG07 7U |
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| #define | PG08 8U |
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| #define | PG09 9U |
| |
| #define | PG10 10U |
| |
| #define | PG11 11U |
| |
| #define | PG12 12U |
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| #define | PG13 13U |
| |
| #define | PG14 14U |
| |
| #define | PG15 15U |
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| #define | OSC_IN 0U |
| |
| #define | OSC_OUT 1U |
| |
| #define | PH02 2U |
| |
| #define | PH03 3U |
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| #define | PH04 4U |
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| #define | PH05 5U |
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| #define | PH06 6U |
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| #define | PH07 7U |
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| #define | PH08 8U |
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| #define | PH09 9U |
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| #define | PH10 10U |
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| #define | PH11 11U |
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| #define | PH12 12U |
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| #define | PH13 13U |
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| #define | PH14 14U |
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| #define | PH15 15U |
| |
| #define | PI00 0U |
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| #define | PI01 1U |
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| #define | PI02 2U |
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| #define | PI03 3U |
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| #define | PI04 4U |
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| #define | PI05 5U |
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| #define | PI06 6U |
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| #define | PI07 7U |
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| #define | PI08 8U |
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| #define | PI09 9U |
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| #define | PI10 10U |
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| #define | PI11 11U |
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| #define | PI12 12U |
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| #define | PI13 13U |
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| #define | PI14 14U |
| |
| #define | PI15 15U |
| |
| #define | PJ00 0U |
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| #define | PJ01 1U |
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| #define | PJ02 2U |
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| #define | PJ03 3U |
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| #define | PJ04 4U |
| |
| #define | PJ05 5U |
| |
| #define | PJ06 6U |
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| #define | PJ07 7U |
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| #define | PJ08 8U |
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| #define | PJ09 9U |
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| #define | PJ10 10U |
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| #define | PJ11 11U |
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| #define | PJ12 12U |
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| #define | PJ13 13U |
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| #define | PJ14 14U |
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| #define | PJ15 15U |
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| #define | PK00 0U |
| |
| #define | PK01 1U |
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| #define | PK02 2U |
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| #define | PK03 3U |
| |
| #define | PK04 4U |
| |
| #define | PK05 5U |
| |
| #define | PK06 6U |
| |
| #define | PK07 7U |
| |
| #define | PK08 8U |
| |
| #define | PK09 9U |
| |
| #define | PK10 10U |
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| #define | PK11 11U |
| |
| #define | PK12 12U |
| |
| #define | PK13 13U |
| |
| #define | PK14 14U |
| |
| #define | PK15 15U |
| |
| #define | LINE_AUX3 PAL_LINE(GPIOA, 0U) |
| |
| #define | LINE_RC1_UART4_RX PAL_LINE(GPIOA, 1U) |
| |
| #define | LINE_AUX2 PAL_LINE(GPIOA, 2U) |
| |
| #define | LINE_AUX1 PAL_LINE(GPIOA, 3U) |
| |
| #define | LINE_VBAT_MEAS PAL_LINE(GPIOA, 4U) |
| |
| #define | LINE_AUX0 PAL_LINE(GPIOA, 5U) |
| |
| #define | LINE_SRV0_TIM3_CH1 PAL_LINE(GPIOA, 6U) |
| |
| #define | LINE_SRV1_TIM3_CH2 PAL_LINE(GPIOA, 7U) |
| |
| #define | LINE_XB_ASSO PAL_LINE(GPIOA, 8U) |
| |
| #define | LINE_USB_VBUS PAL_LINE(GPIOA, 9U) |
| |
| #define | LINE_SD_DETECT PAL_LINE(GPIOA, 10U) |
| |
| #define | LINE_OTG_FS_DM PAL_LINE(GPIOA, 11U) |
| |
| #define | LINE_OTG_FS_DP PAL_LINE(GPIOA, 12U) |
| |
| #define | LINE_SWDIO PAL_LINE(GPIOA, 13U) |
| |
| #define | LINE_SWCLK PAL_LINE(GPIOA, 14U) |
| |
| #define | LINE_SPI1_CS PAL_LINE(GPIOA, 15U) |
| |
| #define | LINE_SRV2_TIM3_CH3 PAL_LINE(GPIOB, 0U) |
| |
| #define | LINE_SRV3_TIM3_CH4 PAL_LINE(GPIOB, 1U) |
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| #define | LINE_RC1 PAL_LINE(GPIOB, 2U) |
| |
| #define | LINE_SPI1_SCK PAL_LINE(GPIOB, 3U) |
| |
| #define | LINE_SPI1_MISO PAL_LINE(GPIOB, 4U) |
| |
| #define | LINE_SPI1_MOSI PAL_LINE(GPIOB, 5U) |
| |
| #define | LINE_USART1_TX PAL_LINE(GPIOB, 6U) |
| |
| #define | LINE_USART1_RX PAL_LINE(GPIOB, 7U) |
| |
| #define | LINE_I2C1_SCL PAL_LINE(GPIOB, 8U) |
| |
| #define | LINE_I2C1_SDA PAL_LINE(GPIOB, 9U) |
| |
| #define | LINE_I2C2_SCL PAL_LINE(GPIOB, 10U) |
| |
| #define | LINE_I2C2_SDA PAL_LINE(GPIOB, 11U) |
| |
| #define | LINE_LED1 PAL_LINE(GPIOB, 12U) |
| |
| #define | LINE_LED2 PAL_LINE(GPIOB, 13U) |
| |
| #define | LINE_DIS_C PAL_LINE(GPIOB, 14U) |
| |
| #define | LINE_DIS_DP PAL_LINE(GPIOB, 15U) |
| |
| #define | LINE_AUX5 PAL_LINE(GPIOC, 2U) |
| |
| #define | LINE_AUX4 PAL_LINE(GPIOC, 3U) |
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| #define | LINE_EN_COMP PAL_LINE(GPIOC, 4U) |
| |
| #define | LINE_AUX6 PAL_LINE(GPIOC, 6U) |
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| #define | LINE_AUX7 PAL_LINE(GPIOC, 7U) |
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| #define | LINE_SDMMC1_D0 PAL_LINE(GPIOC, 8U) |
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| #define | LINE_SDMMC1_D1 PAL_LINE(GPIOC, 9U) |
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| #define | LINE_SDMMC1_D2 PAL_LINE(GPIOC, 10U) |
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| #define | LINE_SDMMC1_D3 PAL_LINE(GPIOC, 11U) |
| |
| #define | LINE_SDMMC1_CK PAL_LINE(GPIOC, 12U) |
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| #define | LINE_OSC32_IN PAL_LINE(GPIOC, 14U) |
| |
| #define | LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) |
| |
| #define | LINE_CAN1_RX PAL_LINE(GPIOD, 0U) |
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| #define | LINE_CAN1_TX PAL_LINE(GPIOD, 1U) |
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| #define | LINE_SDMMC1_CMD PAL_LINE(GPIOD, 2U) |
| |
| #define | LINE_USART2_CTS PAL_LINE(GPIOD, 3U) |
| |
| #define | LINE_USART2_RTS PAL_LINE(GPIOD, 4U) |
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| #define | LINE_USART2_TX PAL_LINE(GPIOD, 5U) |
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| #define | LINE_USART2_RX PAL_LINE(GPIOD, 6U) |
| |
| #define | LINE_IMU_INT PAL_LINE(GPIOD, 7U) |
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| #define | LINE_USART3_TX PAL_LINE(GPIOD, 8U) |
| |
| #define | LINE_USART3_RX PAL_LINE(GPIOD, 9U) |
| |
| #define | LINE_LED3 PAL_LINE(GPIOD, 10U) |
| |
| #define | LINE_LED4 PAL_LINE(GPIOD, 11U) |
| |
| #define | LINE_SRV4_TIM4_CH1 PAL_LINE(GPIOD, 12U) |
| |
| #define | LINE_SRV5_TIM4_CH2 PAL_LINE(GPIOD, 13U) |
| |
| #define | LINE_SRV6_TIM4_CH3 PAL_LINE(GPIOD, 14U) |
| |
| #define | LINE_SRV7_TIM4_CH4 PAL_LINE(GPIOD, 15U) |
| |
| #define | LINE_UART8_RX PAL_LINE(GPIOE, 0U) |
| |
| #define | LINE_UART8_TX PAL_LINE(GPIOE, 1U) |
| |
| #define | LINE_DIS_G PAL_LINE(GPIOE, 2U) |
| |
| #define | LINE_DIS_F PAL_LINE(GPIOE, 3U) |
| |
| #define | LINE_DIS_A PAL_LINE(GPIOE, 4U) |
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| #define | LINE_DIS_B PAL_LINE(GPIOE, 5U) |
| |
| #define | LINE_APSW PAL_LINE(GPIOE, 6U) |
| |
| #define | LINE_RC2_UART7_RX PAL_LINE(GPIOE, 7U) |
| |
| #define | LINE_DIS_E PAL_LINE(GPIOE, 8U) |
| |
| #define | LINE_DIS_D PAL_LINE(GPIOE, 9U) |
| |
| #define | LINE_XB_RST PAL_LINE(GPIOE, 15U) |
| |
| #define | LINE_OSC_IN PAL_LINE(GPIOH, 0U) |
| |
| #define | LINE_OSC_OUT PAL_LINE(GPIOH, 1U) |
| |
| #define | PIN_MODE_INPUT(n) (0U << ((n) * 2U)) |
| |
| #define | PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) |
| |
| #define | PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) |
| |
| #define | PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) |
| |
| #define | PIN_ODR_LEVEL_LOW(n) (0U << (n)) |
| |
| #define | PIN_ODR_LEVEL_HIGH(n) (1U << (n)) |
| |
| #define | PIN_OTYPE_PUSHPULL(n) (0U << (n)) |
| |
| #define | PIN_OTYPE_OPENDRAIN(n) (1U << (n)) |
| |
| #define | PIN_OSPEED_SPEED_VERYLOW(n) (0U << ((n) * 2U)) |
| |
| #define | PIN_OSPEED_SPEED_LOW(n) (1U << ((n) * 2U)) |
| |
| #define | PIN_OSPEED_SPEED_MEDIUM(n) (2U << ((n) * 2U)) |
| |
| #define | PIN_OSPEED_SPEED_HIGH(n) (3U << ((n) * 2U)) |
| |
| #define | PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) |
| |
| #define | PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) |
| |
| #define | PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) |
| |
| #define | PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) |
| |
| #define | VAL_GPIOA_MODER |
| |
| #define | VAL_GPIOA_OTYPER |
| |
| #define | VAL_GPIOA_OSPEEDR |
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| #define | VAL_GPIOA_PUPDR |
| |
| #define | VAL_GPIOA_ODR |
| |
| #define | VAL_GPIOA_AFRL |
| |
| #define | VAL_GPIOA_AFRH |
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| #define | VAL_GPIOB_MODER |
| |
| #define | VAL_GPIOB_OTYPER |
| |
| #define | VAL_GPIOB_OSPEEDR |
| |
| #define | VAL_GPIOB_PUPDR |
| |
| #define | VAL_GPIOB_ODR |
| |
| #define | VAL_GPIOB_AFRL |
| |
| #define | VAL_GPIOB_AFRH |
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| #define | VAL_GPIOC_MODER |
| |
| #define | VAL_GPIOC_OTYPER |
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| #define | VAL_GPIOC_OSPEEDR |
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| #define | VAL_GPIOC_PUPDR |
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| #define | VAL_GPIOC_ODR |
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| #define | VAL_GPIOC_AFRL |
| |
| #define | VAL_GPIOC_AFRH |
| |
| #define | VAL_GPIOD_MODER |
| |
| #define | VAL_GPIOD_OTYPER |
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| #define | VAL_GPIOD_OSPEEDR |
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| #define | VAL_GPIOD_PUPDR |
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| #define | VAL_GPIOD_ODR |
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| #define | VAL_GPIOD_AFRL |
| |
| #define | VAL_GPIOD_AFRH |
| |
| #define | VAL_GPIOE_MODER |
| |
| #define | VAL_GPIOE_OTYPER |
| |
| #define | VAL_GPIOE_OSPEEDR |
| |
| #define | VAL_GPIOE_PUPDR |
| |
| #define | VAL_GPIOE_ODR |
| |
| #define | VAL_GPIOE_AFRL |
| |
| #define | VAL_GPIOE_AFRH |
| |
| #define | VAL_GPIOF_MODER |
| |
| #define | VAL_GPIOF_OTYPER |
| |
| #define | VAL_GPIOF_OSPEEDR |
| |
| #define | VAL_GPIOF_PUPDR |
| |
| #define | VAL_GPIOF_ODR |
| |
| #define | VAL_GPIOF_AFRL |
| |
| #define | VAL_GPIOF_AFRH |
| |
| #define | VAL_GPIOG_MODER |
| |
| #define | VAL_GPIOG_OTYPER |
| |
| #define | VAL_GPIOG_OSPEEDR |
| |
| #define | VAL_GPIOG_PUPDR |
| |
| #define | VAL_GPIOG_ODR |
| |
| #define | VAL_GPIOG_AFRL |
| |
| #define | VAL_GPIOG_AFRH |
| |
| #define | VAL_GPIOH_MODER |
| |
| #define | VAL_GPIOH_OTYPER |
| |
| #define | VAL_GPIOH_OSPEEDR |
| |
| #define | VAL_GPIOH_PUPDR |
| |
| #define | VAL_GPIOH_ODR |
| |
| #define | VAL_GPIOH_AFRL |
| |
| #define | VAL_GPIOH_AFRH |
| |
| #define | VAL_GPIOI_MODER |
| |
| #define | VAL_GPIOI_OTYPER |
| |
| #define | VAL_GPIOI_OSPEEDR |
| |
| #define | VAL_GPIOI_PUPDR |
| |
| #define | VAL_GPIOI_ODR |
| |
| #define | VAL_GPIOI_AFRL |
| |
| #define | VAL_GPIOI_AFRH |
| |
| #define | VAL_GPIOJ_MODER |
| |
| #define | VAL_GPIOJ_OTYPER |
| |
| #define | VAL_GPIOJ_OSPEEDR |
| |
| #define | VAL_GPIOJ_PUPDR |
| |
| #define | VAL_GPIOJ_ODR |
| |
| #define | VAL_GPIOJ_AFRL |
| |
| #define | VAL_GPIOJ_AFRH |
| |
| #define | VAL_GPIOK_MODER |
| |
| #define | VAL_GPIOK_OTYPER |
| |
| #define | VAL_GPIOK_OSPEEDR |
| |
| #define | VAL_GPIOK_PUPDR |
| |
| #define | VAL_GPIOK_ODR |
| |
| #define | VAL_GPIOK_AFRL |
| |
| #define | VAL_GPIOK_AFRH |
| |
| #define | AF_OTG_FS_DM 10U |
| |
| #define | AF_LINE_OTG_FS_DM 10U |
| |
| #define | AF_OTG_FS_DP 10U |
| |
| #define | AF_LINE_OTG_FS_DP 10U |
| |
| #define | AF_SWDIO 0U |
| |
| #define | AF_LINE_SWDIO 0U |
| |
| #define | AF_SWCLK 0U |
| |
| #define | AF_LINE_SWCLK 0U |
| |
| #define | AF_SPI1_SCK 5U |
| |
| #define | AF_LINE_SPI1_SCK 5U |
| |
| #define | AF_SPI1_MISO 5U |
| |
| #define | AF_LINE_SPI1_MISO 5U |
| |
| #define | AF_SPI1_MOSI 5U |
| |
| #define | AF_LINE_SPI1_MOSI 5U |
| |
| #define | AF_USART1_TX 7U |
| |
| #define | AF_LINE_USART1_TX 7U |
| |
| #define | AF_USART1_RX 7U |
| |
| #define | AF_LINE_USART1_RX 7U |
| |
| #define | AF_I2C1_SCL 4U |
| |
| #define | AF_LINE_I2C1_SCL 4U |
| |
| #define | AF_I2C1_SDA 4U |
| |
| #define | AF_LINE_I2C1_SDA 4U |
| |
| #define | AF_I2C2_SCL 4U |
| |
| #define | AF_LINE_I2C2_SCL 4U |
| |
| #define | AF_I2C2_SDA 4U |
| |
| #define | AF_LINE_I2C2_SDA 4U |
| |
| #define | AF_SDMMC1_D0 12U |
| |
| #define | AF_LINE_SDMMC1_D0 12U |
| |
| #define | AF_SDMMC1_D1 12U |
| |
| #define | AF_LINE_SDMMC1_D1 12U |
| |
| #define | AF_SDMMC1_D2 12U |
| |
| #define | AF_LINE_SDMMC1_D2 12U |
| |
| #define | AF_SDMMC1_D3 12U |
| |
| #define | AF_LINE_SDMMC1_D3 12U |
| |
| #define | AF_SDMMC1_CK 12U |
| |
| #define | AF_LINE_SDMMC1_CK 12U |
| |
| #define | AF_OSC32_IN 0U |
| |
| #define | AF_LINE_OSC32_IN 0U |
| |
| #define | AF_OSC32_OUT 0U |
| |
| #define | AF_LINE_OSC32_OUT 0U |
| |
| #define | AF_CAN1_RX 9U |
| |
| #define | AF_LINE_CAN1_RX 9U |
| |
| #define | AF_CAN1_TX 9U |
| |
| #define | AF_LINE_CAN1_TX 9U |
| |
| #define | AF_SDMMC1_CMD 12U |
| |
| #define | AF_LINE_SDMMC1_CMD 12U |
| |
| #define | AF_USART3_TX 7U |
| |
| #define | AF_LINE_USART3_TX 7U |
| |
| #define | AF_USART3_RX 7U |
| |
| #define | AF_LINE_USART3_RX 7U |
| |
| #define | AF_UART8_RX 8U |
| |
| #define | AF_LINE_UART8_RX 8U |
| |
| #define | AF_UART8_TX 8U |
| |
| #define | AF_LINE_UART8_TX 8U |
| |
| #define | AF_OSC_IN 0U |
| |
| #define | AF_LINE_OSC_IN 0U |
| |
| #define | AF_OSC_OUT 0U |
| |
| #define | AF_LINE_OSC_OUT 0U |
| |
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1.8.17 