Paparazzi UAS  v7.0_unstable
Paparazzi is a free software Unmanned Aircraft System.
mcuconf_board.h
Go to the documentation of this file.
1 /*
2  ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
3 
4  Licensed under the Apache License, Version 2.0 (the "License");
5  you may not use this file except in compliance with the License.
6  You may obtain a copy of the License at
7 
8  http://www.apache.org/licenses/LICENSE-2.0
9 
10  Unless required by applicable law or agreed to in writing, software
11  distributed under the License is distributed on an "AS IS" BASIS,
12  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  See the License for the specific language governing permissions and
14  limitations under the License.
15 */
16 
17 #ifndef MCUCONF_H
18 #define MCUCONF_H
19 
20 /*
21  * STM32H7xx drivers configuration.
22  * The following settings override the default settings present in
23  * the various device driver implementation headers.
24  * Note that the settings for each driver only have effect if the whole
25  * driver is enabled in halconf.h.
26  *
27  * IRQ priorities:
28  * 15...0 Lowest...Highest.
29  *
30  * DMA priorities:
31  * 0...3 Lowest...Highest.
32  */
33 
34 #define STM32H7xx_MCUCONF
35 #define STM32H742_MCUCONF
36 #define STM32H743_MCUCONF
37 #define STM32H753_MCUCONF
38 #define STM32H745_MCUCONF
39 #define STM32H755_MCUCONF
40 #define STM32H747_MCUCONF
41 #define STM32H757_MCUCONF
42 #define STM32H750_MCUCONF
43 
44 /*
45  * General settings.
46  */
47 #define STM32_NO_INIT FALSE
48 #define STM32_TARGET_CORE 1
49 
50 /*
51  * Memory attributes settings.
52  */
53 // nocache regions are configured in mcu_arch.c because we need to configure 3 regions.
54 // This ChibiOS configuration can only configure 1 nocache region.
55 #define STM32_NOCACHE_ENABLE FALSE
56 
57 
58 /*
59  * PWR system settings.
60  * Reading STM32 Reference Manual is required, settings in PWR_CR3 are
61  * very critical.
62  * Register constants are taken from the ST header.
63  */
64 #define STM32_VOS STM32_VOS_SCALE1
65 #define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)
66 #define STM32_PWR_CR2 (PWR_CR2_BREN)
67 #define STM32_PWR_CR3 (PWR_CR3_LDOEN | PWR_CR3_USB33DEN)
68 #define STM32_PWR_CPUCR 0
69 
70 /*
71  * Clock tree static settings.
72  * Reading STM32 Reference Manual is required.
73  */
74 #define STM32_HSI_ENABLED TRUE
75 #define STM32_LSI_ENABLED TRUE
76 #define STM32_CSI_ENABLED TRUE
77 #define STM32_HSI48_ENABLED TRUE
78 #define STM32_HSE_ENABLED TRUE
79 #define STM32_LSE_ENABLED FALSE
80 #define STM32_HSIDIV STM32_HSIDIV_DIV1
81 
82 /*
83  * PLLs static settings.
84  * Reading STM32 Reference Manual is required.
85  */
86 #define STM32_PLLSRC STM32_PLLSRC_HSE_CK
87 #define STM32_PLLCFGR_MASK ~0
88 #define STM32_PLL1_ENABLED TRUE
89 #define STM32_PLL1_P_ENABLED TRUE
90 #define STM32_PLL1_Q_ENABLED TRUE
91 #define STM32_PLL1_R_ENABLED TRUE
92 #define STM32_PLL1_DIVM_VALUE 4
93 #define STM32_PLL1_DIVN_VALUE 480
94 #define STM32_PLL1_FRACN_VALUE 0
95 #define STM32_PLL1_DIVP_VALUE 2
96 #define STM32_PLL1_DIVQ_VALUE 20
97 #define STM32_PLL1_DIVR_VALUE 8
98 #define STM32_PLL2_ENABLED TRUE
99 #define STM32_PLL2_P_ENABLED TRUE
100 #define STM32_PLL2_Q_ENABLED TRUE
101 #define STM32_PLL2_R_ENABLED TRUE
102 #define STM32_PLL2_DIVM_VALUE 4
103 #define STM32_PLL2_DIVN_VALUE 400
104 #define STM32_PLL2_FRACN_VALUE 0
105 #define STM32_PLL2_DIVP_VALUE 40
106 #define STM32_PLL2_DIVQ_VALUE 8
107 #define STM32_PLL2_DIVR_VALUE 8
108 #define STM32_PLL3_ENABLED TRUE
109 #define STM32_PLL3_P_ENABLED TRUE
110 #define STM32_PLL3_Q_ENABLED TRUE
111 #define STM32_PLL3_R_ENABLED TRUE
112 #define STM32_PLL3_DIVM_VALUE 4
113 #define STM32_PLL3_DIVN_VALUE 400
114 #define STM32_PLL3_FRACN_VALUE 0
115 #define STM32_PLL3_DIVP_VALUE 8
116 #define STM32_PLL3_DIVQ_VALUE 8
117 #define STM32_PLL3_DIVR_VALUE 8
118 
119 /*
120  * Core clocks dynamic settings (can be changed at runtime).
121  * Reading STM32 Reference Manual is required.
122  */
123 #define STM32_SW STM32_SW_PLL1_P_CK
124 
125 #if HAL_USE_RTC
126 #define STM32_RTCSEL STM32_RTCSEL_LSI_CK
127 #else
128 #define STM32_RTCSEL STM32_RTCSEL_NOCLK
129 #endif
130 
131 #define STM32_D1CPRE STM32_D1CPRE_DIV1
132 #define STM32_D1HPRE STM32_D1HPRE_DIV4
133 #define STM32_D1PPRE3 STM32_D1PPRE3_DIV1
134 #define STM32_D2PPRE1 STM32_D2PPRE1_DIV1
135 #define STM32_D2PPRE2 STM32_D2PPRE2_DIV1
136 #define STM32_D3PPRE4 STM32_D3PPRE4_DIV1
137 
138 /*
139  * Peripherals clocks static settings.
140  * Reading STM32 Reference Manual is required.
141  */
142 #define STM32_MCO1SEL STM32_MCO1SEL_HSI_CK
143 #define STM32_MCO1PRE_VALUE 4
144 #define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK
145 #define STM32_MCO2PRE_VALUE 4
146 #define STM32_TIMPRE_ENABLE TRUE
147 #define STM32_HRTIMSEL 0
148 #define STM32_STOPKERWUCK 0
149 #define STM32_STOPWUCK 0
150 #define STM32_RTCPRE_VALUE 8
151 #define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK
152 #define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK
153 #define STM32_QSPISEL STM32_QSPISEL_HCLK
154 #define STM32_FMCSEL STM32_QSPISEL_HCLK
155 #define STM32_SWPSEL STM32_SWPSEL_PCLK1
156 #define STM32_FDCANSEL STM32_FDCANSEL_HSE_CK
157 #define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2
158 #define STM32_SPDIFSEL STM32_SPDIFSEL_PLL1_Q_CK
159 #define STM32_SPI45SEL STM32_SPI45SEL_PCLK2
160 #define STM32_SPI123SEL STM32_SPI123SEL_PLL1_Q_CK
161 #define STM32_SAI23SEL STM32_SAI23SEL_PLL1_Q_CK
162 #define STM32_SAI1SEL STM32_SAI1SEL_PLL1_Q_CK
163 #define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
164 #define STM32_CECSEL STM32_CECSEL_LSE_CK
165 #define STM32_USBSEL STM32_USBSEL_PLL1_Q_CK
166 #define STM32_I2C123SEL STM32_I2C123SEL_PCLK1
167 #define STM32_RNGSEL STM32_RNGSEL_HSI48_CK
168 #define STM32_USART16SEL STM32_USART16SEL_PCLK2
169 #define STM32_USART234578SEL STM32_USART234578SEL_PCLK1
170 #define STM32_SPI6SEL STM32_SPI6SEL_PCLK4
171 #define STM32_SAI4BSEL STM32_SAI4BSEL_PLL1_Q_CK
172 #define STM32_SAI4ASEL STM32_SAI4ASEL_PLL1_Q_CK
173 #define STM32_ADCSEL STM32_ADCSEL_PLL2_P_CK
174 #define STM32_LPTIM345SEL STM32_LPTIM345SEL_PCLK4
175 #define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK4
176 #define STM32_I2C4SEL STM32_I2C4SEL_PCLK4
177 #define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK4
178 
179 /*
180  * IRQ system settings.
181  */
182 #define STM32_IRQ_EXTI0_PRIORITY 6
183 #define STM32_IRQ_EXTI1_PRIORITY 6
184 #define STM32_IRQ_EXTI2_PRIORITY 6
185 #define STM32_IRQ_EXTI3_PRIORITY 6
186 #define STM32_IRQ_EXTI4_PRIORITY 6
187 #define STM32_IRQ_EXTI5_9_PRIORITY 6
188 #define STM32_IRQ_EXTI10_15_PRIORITY 6
189 #define STM32_IRQ_EXTI16_PRIORITY 6
190 #define STM32_IRQ_EXTI17_PRIORITY 6
191 #define STM32_IRQ_EXTI18_PRIORITY 6
192 #define STM32_IRQ_EXTI19_PRIORITY 6
193 #define STM32_IRQ_EXTI20_21_PRIORITY 6
194 
195 #define STM32_IRQ_FDCAN1_PRIORITY 10
196 #define STM32_IRQ_FDCAN2_PRIORITY 10
197 
198 #define STM32_IRQ_MDMA_PRIORITY 9
199 
200 #define STM32_IRQ_QUADSPI1_PRIORITY 10
201 
202 #define STM32_IRQ_SDMMC1_PRIORITY 9
203 #define STM32_IRQ_SDMMC2_PRIORITY 9
204 
205 #define STM32_IRQ_TIM1_UP_PRIORITY 7
206 #define STM32_IRQ_TIM1_CC_PRIORITY 7
207 #define STM32_IRQ_TIM2_PRIORITY 7
208 #define STM32_IRQ_TIM3_PRIORITY 7
209 #define STM32_IRQ_TIM4_PRIORITY 7
210 #define STM32_IRQ_TIM5_PRIORITY 7
211 #define STM32_IRQ_TIM6_PRIORITY 7
212 #define STM32_IRQ_TIM7_PRIORITY 7
213 #define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7
214 #define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7
215 #define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7
216 #define STM32_IRQ_TIM8_CC_PRIORITY 7
217 #define STM32_IRQ_TIM15_PRIORITY 7
218 #define STM32_IRQ_TIM16_PRIORITY 7
219 #define STM32_IRQ_TIM17_PRIORITY 7
220 
221 #define STM32_IRQ_USART1_PRIORITY 12
222 #define STM32_IRQ_USART2_PRIORITY 12
223 #define STM32_IRQ_USART3_PRIORITY 12
224 #define STM32_IRQ_UART4_PRIORITY 12
225 #define STM32_IRQ_UART5_PRIORITY 12
226 #define STM32_IRQ_USART6_PRIORITY 12
227 #define STM32_IRQ_UART7_PRIORITY 12
228 #define STM32_IRQ_UART8_PRIORITY 12
229 #define STM32_IRQ_LPUART1_PRIORITY 12
230 
231 /*
232  * ADC driver system settings.
233  */
234 #define STM32_ADC_DUAL_MODE FALSE
235 #define STM32_ADC_SAMPLES_SIZE 16
236 #define STM32_ADC_USE_ADC12 TRUE
237 #define STM32_ADC_USE_ADC3 TRUE
238 #define STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY
239 #define STM32_ADC_ADC3_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
240 #define STM32_ADC_ADC12_DMA_PRIORITY 2
241 #define STM32_ADC_ADC3_DMA_PRIORITY 2
242 #define STM32_ADC_ADC12_IRQ_PRIORITY 5
243 #define STM32_ADC_ADC3_IRQ_PRIORITY 5
244 #define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
245 #define STM32_ADC_ADC3_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4
246 
247 /*
248  * CAN driver system settings.
249  */
250 
251 #if USE_CAN1
252 #define STM32_CAN_USE_FDCAN1 TRUE
253 #else
254 #define STM32_CAN_USE_FDCAN1 FALSE
255 #endif
256 #define STM32_CAN_USE_FDCAN2 FALSE
257 /*
258  * DAC driver system settings.
259  */
260 #define STM32_DAC_DUAL_MODE FALSE
261 #define STM32_DAC_USE_DAC1_CH1 FALSE
262 #define STM32_DAC_USE_DAC1_CH2 FALSE
263 #define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
264 #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
265 #define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
266 #define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
267 #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
268 #define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
269 
270 /*
271  * GPT driver system settings.
272  */
273 #define STM32_GPT_USE_TIM1 FALSE
274 #define STM32_GPT_USE_TIM2 FALSE
275 #define STM32_GPT_USE_TIM3 FALSE
276 #define STM32_GPT_USE_TIM4 FALSE
277 #if USE_GPT5
278 #define STM32_GPT_USE_TIM5 TRUE
279 #else
280 #define STM32_GPT_USE_TIM5 FALSE
281 #endif
282 #define STM32_GPT_USE_TIM6 TRUE
283 #if USE_GPT7
284 #define STM32_GPT_USE_TIM7 TRUE
285 #else
286 #define STM32_GPT_USE_TIM7 FALSE
287 #endif
288 #if USE_GPT8
289 #define STM32_GPT_USE_TIM8 TRUE
290 #else
291 #define STM32_GPT_USE_TIM8 FALSE
292 #endif
293 #if USE_GPT12
294 #define STM32_GPT_USE_TIM12 TRUE
295 #else
296 #define STM32_GPT_USE_TIM12 FALSE
297 #endif
298 #if USE_GPT13
299 #define STM32_GPT_USE_TIM13 TRUE
300 #else
301 #define STM32_GPT_USE_TIM13 FALSE
302 #endif
303 #define STM32_GPT_USE_TIM14 FALSE
304 #define STM32_GPT_USE_TIM15 FALSE
305 #define STM32_GPT_USE_TIM16 FALSE
306 #define STM32_GPT_USE_TIM17 FALSE
307 
308 /*
309  * I2C driver system settings.
310  */
311 #define STM32_I2C_USE_I2C1 FALSE
312 #if USE_I2C2
313 #define STM32_I2C_USE_I2C2 TRUE
314 #else
315 #define STM32_I2C_USE_I2C2 FALSE
316 #endif
317 #define STM32_I2C_USE_I2C3 FALSE
318 #if USE_I2C4
319 #define STM32_I2C_USE_I2C4 TRUE
320 #else
321 #define STM32_I2C_USE_I2C4 FALSE
322 #endif
323 #define STM32_I2C_BUSY_TIMEOUT 50
324 #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
325 #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
326 #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
327 #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
328 #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
329 #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
330 #define STM32_I2C_I2C4_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
331 #define STM32_I2C_I2C4_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
332 #define STM32_I2C_I2C1_IRQ_PRIORITY 5
333 #define STM32_I2C_I2C2_IRQ_PRIORITY 5
334 #define STM32_I2C_I2C3_IRQ_PRIORITY 5
335 #define STM32_I2C_I2C4_IRQ_PRIORITY 5
336 #define STM32_I2C_I2C1_DMA_PRIORITY 3
337 #define STM32_I2C_I2C2_DMA_PRIORITY 3
338 #define STM32_I2C_I2C3_DMA_PRIORITY 3
339 #define STM32_I2C_I2C4_DMA_PRIORITY 3
340 #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
341 
342 /*
343  * ICU driver system settings.
344  */
345 #define STM32_ICU_USE_TIM1 TRUE
346 #define STM32_ICU_USE_TIM2 FALSE
347 #define STM32_ICU_USE_TIM3 FALSE
348 #define STM32_ICU_USE_TIM4 FALSE
349 #define STM32_ICU_USE_TIM5 FALSE
350 #define STM32_ICU_USE_TIM8 FALSE
351 #define STM32_ICU_USE_TIM12 FALSE
352 #define STM32_ICU_USE_TIM13 FALSE
353 #define STM32_ICU_USE_TIM14 FALSE
354 #define STM32_ICU_USE_TIM15 FALSE
355 #define STM32_ICU_USE_TIM16 FALSE
356 #define STM32_ICU_USE_TIM17 FALSE
357 
358 /*
359  * MAC driver system settings.
360  */
361 #define STM32_MAC_TRANSMIT_BUFFERS 2
362 #define STM32_MAC_RECEIVE_BUFFERS 4
363 #define STM32_MAC_BUFFERS_SIZE 1522
364 #define STM32_MAC_PHY_TIMEOUT 100
365 #define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
366 #define STM32_MAC_ETH1_IRQ_PRIORITY 13
367 #define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
368 
369 /*
370  * PWM driver system settings.
371  */
372 #ifndef STM32_PWM_USE_TIM1
373 #define STM32_PWM_USE_TIM1 TRUE
374 #endif
375 #ifndef STM32_PWM_USE_TIM2
376 #define STM32_PWM_USE_TIM2 FALSE
377 #endif
378 #ifndef STM32_PWM_USE_TIM3
379 #define STM32_PWM_USE_TIM3 TRUE
380 #endif
381 #ifndef STM32_PWM_USE_TIM4
382 #define STM32_PWM_USE_TIM4 TRUE
383 #endif
384 #define STM32_PWM_USE_TIM5 FALSE
385 #define STM32_PWM_USE_TIM8 FALSE
386 #define STM32_PWM_USE_TIM12 FALSE
387 #define STM32_PWM_USE_TIM13 FALSE
388 #define STM32_PWM_USE_TIM14 FALSE
389 #ifndef STM32_PWM_USE_TIM15
390 #define STM32_PWM_USE_TIM15 FALSE
391 #endif
392 #define STM32_PWM_USE_TIM16 FALSE
393 #define STM32_PWM_USE_TIM17 FALSE
394 
395 /*
396  * RTC driver system settings.
397  */
398 #define STM32_RTC_PRESA_VALUE 32
399 #define STM32_RTC_PRESS_VALUE 1024
400 #define STM32_RTC_CR_INIT 0
401 #define STM32_RTC_TAMPCR_INIT 0
402 
403 /*
404  * SDC driver system settings.
405  */
406 #define STM32_SDC_USE_SDMMC1 TRUE
407 #define STM32_SDC_USE_SDMMC2 FALSE
408 #define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE
409 #define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000000
410 #define STM32_SDC_SDMMC_READ_TIMEOUT 1000000
411 #define STM32_SDC_SDMMC_CLOCK_DELAY 10
412 #define STM32_SDC_SDMMC_PWRSAV TRUE
413 
414 /*
415  * SERIAL driver system settings.
416  */
417 #define STM32_SERIAL_USE_USART1 TRUE // enabled by default for dshot telemetry
418 #if USE_UART2
419 #define STM32_SERIAL_USE_USART2 TRUE
420 #else
421 #define STM32_SERIAL_USE_USART2 FALSE
422 #endif
423 #if USE_UART3
424 #define STM32_SERIAL_USE_USART3 TRUE
425 #else
426 #define STM32_SERIAL_USE_USART3 FALSE
427 #endif
428 #define STM32_SERIAL_USE_UART4 FALSE
429 #define STM32_SERIAL_USE_UART5 FALSE
430 #define STM32_SERIAL_USE_USART6 FALSE
431 #if USE_UART7
432 #define STM32_SERIAL_USE_UART7 TRUE
433 #else
434 #define STM32_SERIAL_USE_UART7 FALSE
435 #endif
436 #if USE_UART8
437 #define STM32_SERIAL_USE_UART8 TRUE
438 #else
439 #define STM32_SERIAL_USE_UART8 FALSE
440 #endif
441 #define STM32_SERIAL_USE_LPUART1 FALSE
442 
443 /*
444  * SIO driver system settings.
445  */
446 #define STM32_SIO_USE_USART1 FALSE
447 #define STM32_SIO_USE_USART2 FALSE
448 #define STM32_SIO_USE_USART3 FALSE
449 #define STM32_SIO_USE_UART4 FALSE
450 #define STM32_SIO_USE_UART5 FALSE
451 #define STM32_SIO_USE_USART6 FALSE
452 #define STM32_SIO_USE_UART7 FALSE
453 #define STM32_SIO_USE_UART8 FALSE
454 #define STM32_SIO_USE_LPUART1 FALSE
455 
456 /*
457  * SPI driver system settings.
458  */
459 #define STM32_SPI_USE_SPI1 FALSE
460 #if USE_SPI2
461 #define STM32_SPI_USE_SPI2 TRUE
462 #else
463 #define STM32_SPI_USE_SPI2 FALSE
464 #endif
465 #define STM32_SPI_USE_SPI3 FALSE
466 #define STM32_SPI_USE_SPI4 FALSE
467 #define STM32_SPI_USE_SPI5 FALSE
468 #if USE_SPI6
469 #define STM32_SPI_USE_SPI6 TRUE
470 #else
471 #define STM32_SPI_USE_SPI6 FALSE
472 #endif
473 #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
474 #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
475 #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
476 #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
477 #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
478 #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
479 #define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
480 #define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
481 #define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
482 #define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
483 #define STM32_SPI_SPI6_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
484 #define STM32_SPI_SPI6_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY
485 #define STM32_SPI_SPI1_DMA_PRIORITY 1
486 #define STM32_SPI_SPI2_DMA_PRIORITY 1
487 #define STM32_SPI_SPI3_DMA_PRIORITY 1
488 #define STM32_SPI_SPI4_DMA_PRIORITY 1
489 #define STM32_SPI_SPI5_DMA_PRIORITY 1
490 #define STM32_SPI_SPI6_DMA_PRIORITY 1
491 #define STM32_SPI_SPI1_IRQ_PRIORITY 10
492 #define STM32_SPI_SPI2_IRQ_PRIORITY 10
493 #define STM32_SPI_SPI3_IRQ_PRIORITY 10
494 #define STM32_SPI_SPI4_IRQ_PRIORITY 10
495 #define STM32_SPI_SPI5_IRQ_PRIORITY 10
496 #define STM32_SPI_SPI6_IRQ_PRIORITY 10
497 #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
498 
499 /*
500  * ST driver system settings.
501  */
502 #define STM32_ST_IRQ_PRIORITY 8
503 #define STM32_ST_USE_TIMER 2
504 
505 /*
506  * TRNG driver system settings.
507  */
508 #define STM32_TRNG_USE_RNG1 FALSE
509 
510 /*
511  * UART driver system settings.
512  */
513 #define STM32_UART_USE_USART1 FALSE
514 #define STM32_UART_USE_USART2 TRUE
515 #define STM32_UART_USE_USART3 FALSE
516 #define STM32_UART_USE_UART4 FALSE
517 #define STM32_UART_USE_UART5 FALSE
518 #define STM32_UART_USE_USART6 FALSE
519 #define STM32_UART_USE_UART7 FALSE
520 #define STM32_UART_USE_UART8 FALSE
521 #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
522 #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
523 #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
524 #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
525 #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
526 #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
527 #define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
528 #define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
529 #define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
530 #define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
531 #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
532 #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
533 #define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
534 #define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
535 #define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
536 #define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
537 #define STM32_UART_USART1_DMA_PRIORITY 0
538 #define STM32_UART_USART2_DMA_PRIORITY 0
539 #define STM32_UART_USART3_DMA_PRIORITY 0
540 #define STM32_UART_UART4_DMA_PRIORITY 0
541 #define STM32_UART_UART5_DMA_PRIORITY 0
542 #define STM32_UART_USART6_DMA_PRIORITY 0
543 #define STM32_UART_UART7_DMA_PRIORITY 0
544 #define STM32_UART_UART8_DMA_PRIORITY 0
545 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
546 
547 /*
548  * USB driver system settings.
549  */
550 #define STM32_USB_USE_OTG1 TRUE
551 #define STM32_USB_USE_OTG2 FALSE
552 #define STM32_USB_OTG1_IRQ_PRIORITY 14
553 #define STM32_USB_OTG2_IRQ_PRIORITY 14
554 #define STM32_USB_OTG1_RX_FIFO_SIZE 512
555 #define STM32_USB_OTG2_RX_FIFO_SIZE 1024
556 #define STM32_USB_HOST_WAKEUP_DURATION 2
557 
558 /*
559  * WDG driver system settings.
560  */
561 #define STM32_WDG_USE_IWDG FALSE
562 
563 /*
564  * WSPI driver system settings.
565  */
566 #define STM32_WSPI_USE_QUADSPI1 FALSE
567 #define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
568 #define STM32_WSPI_SET_CR_SSHIFT TRUE
569 #define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
570 #define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
571 #define STM32_WSPI_MDMA_ERROR_HOOK(wspip) osalSysHalt("MDMA failure")
572 
573 /*
574  sdlog message buffer and queue configuration
575  */
576 #define SDLOG_QUEUE_BUCKETS 1024
577 #define SDLOG_MAX_MESSAGE_LEN 300
578 #define SDLOG_NUM_FILES 2
579 #define SDLOG_ALL_BUFFERS_SIZE (SDLOG_NUM_FILES*16*1024)
580 
581 // #define CH_HEAP_SIZE (32*1024)
582 // #define CH_HEAP_USE_TLSF 0 // if 0 or undef, chAlloc will be used
583 // #define CONSOLE_DEV_SD SD3
584 
585 #define HAL_USE_RTC TRUE
586 
587 #endif /* MCUCONF_H */