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#define | STM32_ENFORCE_H7_REV_XY |
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#define | STM32H7xx_MCUCONF |
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#define | STM32H742_MCUCONF |
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#define | STM32H743_MCUCONF |
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#define | STM32H753_MCUCONF |
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#define | STM32H745_MCUCONF |
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#define | STM32H755_MCUCONF |
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#define | STM32H747_MCUCONF |
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#define | STM32H757_MCUCONF |
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#define | STM32_NO_INIT FALSE |
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#define | STM32_TARGET_CORE 1 |
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#define | STM32_NOCACHE_ENABLE TRUE |
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#define | STM32_NOCACHE_MPU_REGION MPU_REGION_6 |
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#define | STM32_NOCACHE_RBAR 0x24000000U |
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#define | STM32_NOCACHE_RASR MPU_RASR_SIZE_64K |
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#define | STM32_VOS STM32_VOS_SCALE1 |
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#define | STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0) |
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#define | STM32_PWR_CR2 (PWR_CR2_BREN) |
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#define | STM32_PWR_CR3 (PWR_CR3_LDOEN | PWR_CR3_USB33DEN) |
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#define | STM32_PWR_CPUCR 0 |
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#define | STM32_HSI_ENABLED FALSE |
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#define | STM32_LSI_ENABLED FALSE |
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#define | STM32_CSI_ENABLED FALSE |
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#define | STM32_HSI48_ENABLED TRUE |
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#define | STM32_HSE_ENABLED TRUE |
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#define | STM32_LSE_ENABLED FALSE |
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#define | STM32_HSIDIV STM32_HSIDIV_DIV1 |
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#define | STM32_PLLSRC STM32_PLLSRC_HSE_CK |
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#define | STM32_PLLCFGR_MASK ~0 |
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#define | STM32_PLL1_ENABLED TRUE |
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#define | STM32_PLL1_P_ENABLED TRUE |
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#define | STM32_PLL1_Q_ENABLED TRUE |
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#define | STM32_PLL1_R_ENABLED TRUE |
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#define | STM32_PLL1_DIVM_VALUE 3 |
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#define | STM32_PLL1_DIVN_VALUE 100 |
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#define | STM32_PLL1_FRACN_VALUE 0 |
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#define | STM32_PLL1_DIVP_VALUE 2 |
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#define | STM32_PLL1_DIVQ_VALUE 10 |
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#define | STM32_PLL1_DIVR_VALUE 2 |
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#define | STM32_PLL2_ENABLED TRUE |
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#define | STM32_PLL2_P_ENABLED TRUE |
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#define | STM32_PLL2_Q_ENABLED TRUE |
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#define | STM32_PLL2_R_ENABLED TRUE |
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#define | STM32_PLL2_DIVM_VALUE 2 |
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#define | STM32_PLL2_DIVN_VALUE 30 |
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#define | STM32_PLL2_FRACN_VALUE 0 |
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#define | STM32_PLL2_DIVP_VALUE 2 |
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#define | STM32_PLL2_DIVQ_VALUE 5 |
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#define | STM32_PLL2_DIVR_VALUE 1 |
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#define | STM32_PLL3_ENABLED TRUE |
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#define | STM32_PLL3_P_ENABLED TRUE |
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#define | STM32_PLL3_Q_ENABLED TRUE |
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#define | STM32_PLL3_R_ENABLED TRUE |
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#define | STM32_PLL3_DIVM_VALUE 6 |
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#define | STM32_PLL3_DIVN_VALUE 72 |
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#define | STM32_PLL3_FRACN_VALUE 0 |
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#define | STM32_PLL3_DIVP_VALUE 2 |
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#define | STM32_PLL3_DIVQ_VALUE 6 |
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#define | STM32_PLL3_DIVR_VALUE 9 |
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#define | STM32_SW STM32_SW_PLL1_P_CK |
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#define | STM32_RTCSEL STM32_RTCSEL_NOCLK |
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#define | STM32_D1CPRE STM32_D1CPRE_DIV1 |
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#define | STM32_D1HPRE STM32_D1HPRE_DIV2 |
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#define | STM32_D1PPRE3 STM32_D1PPRE3_DIV2 |
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#define | STM32_D2PPRE1 STM32_D2PPRE1_DIV2 |
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#define | STM32_D2PPRE2 STM32_D2PPRE2_DIV2 |
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#define | STM32_D3PPRE4 STM32_D3PPRE4_DIV2 |
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#define | STM32_MCO1SEL STM32_MCO1SEL_HSE_CK |
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#define | STM32_MCO1PRE_VALUE 4 |
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#define | STM32_MCO2SEL STM32_MCO2SEL_SYS_CK |
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#define | STM32_MCO2PRE_VALUE 4 |
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#define | STM32_TIMPRE_ENABLE TRUE |
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#define | STM32_HRTIMSEL 0 |
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#define | STM32_STOPKERWUCK 0 |
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#define | STM32_STOPWUCK 0 |
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#define | STM32_RTCPRE_VALUE 8 |
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#define | STM32_CKPERSEL STM32_CKPERSEL_HSE_CK |
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#define | STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK |
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#define | STM32_QSPISEL STM32_QSPISEL_PLL2_R_CK |
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#define | STM32_FMCSEL STM32_FMCSEL_HCLK |
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#define | STM32_SWPSEL STM32_SWPSEL_PCLK1 |
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#define | STM32_FDCANSEL STM32_FDCANSEL_PLL1_Q_CK |
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#define | STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2 |
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#define | STM32_SPDIFSEL STM32_SPDIFSEL_PLL1_Q_CK |
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#define | STM32_SPI45SEL STM32_SPI45SEL_PCLK2 |
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#define | STM32_SPI123SEL STM32_SPI123SEL_PLL1_Q_CK |
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#define | STM32_SAI23SEL STM32_SAI23SEL_PLL1_Q_CK |
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#define | STM32_SAI1SEL STM32_SAI1SEL_PLL1_Q_CK |
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#define | STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 |
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#define | STM32_CECSEL STM32_CECSEL_DISABLE |
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#define | STM32_USBSEL STM32_USBSEL_PLL3_Q_CK |
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#define | STM32_I2C123SEL STM32_I2C123SEL_PLL3_R_CK |
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#define | STM32_RNGSEL STM32_RNGSEL_HSI48_CK |
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#define | STM32_USART16SEL STM32_USART16SEL_PCLK2 |
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#define | STM32_USART234578SEL STM32_USART234578SEL_PCLK1 |
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#define | STM32_SPI6SEL STM32_SPI6SEL_PCLK4 |
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#define | STM32_SAI4BSEL STM32_SAI4BSEL_PLL1_Q_CK |
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#define | STM32_SAI4ASEL STM32_SAI4ASEL_PLL1_Q_CK |
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#define | STM32_ADCSEL STM32_ADCSEL_PLL3_R_CK |
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#define | STM32_LPTIM345SEL STM32_LPTIM345SEL_PCLK4 |
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#define | STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK4 |
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#define | STM32_I2C4SEL STM32_I2C4SEL_PLL3_R_CK |
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#define | STM32_LPUART1SEL STM32_LPUART1SEL_PCLK4 |
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#define | STM32_IRQ_EXTI0_PRIORITY 6 |
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#define | STM32_IRQ_EXTI1_PRIORITY 6 |
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#define | STM32_IRQ_EXTI2_PRIORITY 6 |
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#define | STM32_IRQ_EXTI3_PRIORITY 6 |
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#define | STM32_IRQ_EXTI4_PRIORITY 6 |
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#define | STM32_IRQ_EXTI5_9_PRIORITY 6 |
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#define | STM32_IRQ_EXTI10_15_PRIORITY 6 |
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#define | STM32_IRQ_EXTI16_PRIORITY 6 |
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#define | STM32_IRQ_EXTI17_PRIORITY 15 |
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#define | STM32_IRQ_EXTI18_PRIORITY 6 |
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#define | STM32_IRQ_EXTI19_PRIORITY 6 |
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#define | STM32_IRQ_EXTI20_21_PRIORITY 6 |
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#define | STM32_IRQ_FDCAN1_PRIORITY 10 |
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#define | STM32_IRQ_FDCAN2_PRIORITY 10 |
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#define | STM32_IRQ_MDMA_PRIORITY 9 |
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#define | STM32_IRQ_QUADSPI1_PRIORITY 10 |
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#define | STM32_IRQ_SDMMC1_PRIORITY 9 |
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#define | STM32_IRQ_SDMMC2_PRIORITY 9 |
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#define | STM32_IRQ_TIM1_UP_PRIORITY 7 |
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#define | STM32_IRQ_TIM1_CC_PRIORITY 7 |
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#define | STM32_IRQ_TIM2_PRIORITY 7 |
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#define | STM32_IRQ_TIM3_PRIORITY 7 |
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#define | STM32_IRQ_TIM4_PRIORITY 7 |
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#define | STM32_IRQ_TIM5_PRIORITY 7 |
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#define | STM32_IRQ_TIM6_PRIORITY 7 |
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#define | STM32_IRQ_TIM7_PRIORITY 7 |
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#define | STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7 |
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#define | STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7 |
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#define | STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7 |
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#define | STM32_IRQ_TIM8_CC_PRIORITY 7 |
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#define | STM32_IRQ_TIM15_PRIORITY 7 |
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#define | STM32_IRQ_TIM16_PRIORITY 7 |
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#define | STM32_IRQ_TIM17_PRIORITY 7 |
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#define | STM32_IRQ_USART1_PRIORITY 12 |
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#define | STM32_IRQ_USART2_PRIORITY 12 |
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#define | STM32_IRQ_USART3_PRIORITY 12 |
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#define | STM32_IRQ_UART4_PRIORITY 12 |
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#define | STM32_IRQ_UART5_PRIORITY 12 |
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#define | STM32_IRQ_USART6_PRIORITY 12 |
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#define | STM32_IRQ_UART7_PRIORITY 12 |
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#define | STM32_IRQ_UART8_PRIORITY 12 |
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#define | STM32_IRQ_LPUART1_PRIORITY 12 |
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#define | STM32_ADC_DUAL_MODE FALSE |
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#define | STM32_ADC_SAMPLES_SIZE 16 |
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#define | STM32_ADC_USE_ADC12 TRUE |
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#define | STM32_ADC_USE_ADC3 TRUE |
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#define | STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_ADC_ADC3_BDMA_STREAM 7 |
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#define | STM32_ADC_ADC12_DMA_PRIORITY 2 |
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#define | STM32_ADC_ADC3_DMA_PRIORITY 2 |
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#define | STM32_ADC_ADC12_IRQ_PRIORITY 5 |
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#define | STM32_ADC_ADC3_IRQ_PRIORITY 5 |
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#define | STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_ADCCK |
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#define | STM32_ADC_ADC3_CLOCK_MODE ADC_CCR_CKMODE_ADCCK |
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#define | STM32_CAN_USE_FDCAN1 FALSE |
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#define | STM32_CAN_USE_FDCAN2 FALSE |
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#define | STM32_CAN_USE_FDCAN3 FALSE |
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#define | STM32_DAC_DUAL_MODE FALSE |
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#define | STM32_DAC_USE_DAC1_CH1 FALSE |
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#define | STM32_DAC_USE_DAC1_CH2 FALSE |
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#define | STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 |
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#define | STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 |
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#define | STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 |
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#define | STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 |
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#define | STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_GPT_USE_TIM1 FALSE |
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#define | STM32_GPT_USE_TIM2 FALSE |
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#define | STM32_GPT_USE_TIM3 FALSE |
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#define | STM32_GPT_USE_TIM4 FALSE |
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#define | STM32_GPT_USE_TIM5 FALSE |
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#define | STM32_GPT_USE_TIM6 FALSE |
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#define | STM32_GPT_USE_TIM7 FALSE |
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#define | STM32_GPT_USE_TIM8 FALSE |
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#define | STM32_GPT_USE_TIM12 FALSE |
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#define | STM32_GPT_USE_TIM13 FALSE |
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#define | STM32_GPT_USE_TIM14 FALSE |
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#define | STM32_GPT_USE_TIM15 FALSE |
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#define | STM32_GPT_USE_TIM16 FALSE |
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#define | STM32_GPT_USE_TIM17 FALSE |
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#define | STM32_I2C_USE_I2C1 FALSE |
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#define | STM32_I2C_USE_I2C2 FALSE |
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#define | STM32_I2C_USE_I2C3 FALSE |
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#define | STM32_I2C_USE_I2C4 FALSE |
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#define | STM32_I2C_ISR_LIMIT 6 |
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#define | STM32_I2C_BUSY_TIMEOUT 0 |
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#define | STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_I2C_I2C4_RX_BDMA_STREAM 1 |
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#define | STM32_I2C_I2C4_TX_BDMA_STREAM 2 |
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#define | STM32_I2C_I2C1_IRQ_PRIORITY 5 |
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#define | STM32_I2C_I2C2_IRQ_PRIORITY 5 |
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#define | STM32_I2C_I2C3_IRQ_PRIORITY 5 |
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#define | STM32_I2C_I2C4_IRQ_PRIORITY 5 |
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#define | STM32_I2C_I2C1_DMA_PRIORITY 3 |
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#define | STM32_I2C_I2C2_DMA_PRIORITY 3 |
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#define | STM32_I2C_I2C3_DMA_PRIORITY 3 |
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#define | STM32_I2C_I2C4_DMA_PRIORITY 3 |
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#define | STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") |
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#define | STM32_ICU_USE_TIM1 FALSE |
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#define | STM32_ICU_USE_TIM2 FALSE |
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#define | STM32_ICU_USE_TIM3 FALSE |
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#define | STM32_ICU_USE_TIM4 FALSE |
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#define | STM32_ICU_USE_TIM5 FALSE |
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#define | STM32_ICU_USE_TIM8 FALSE |
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#define | STM32_ICU_USE_TIM12 FALSE |
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#define | STM32_ICU_USE_TIM13 FALSE |
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#define | STM32_ICU_USE_TIM14 FALSE |
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#define | STM32_ICU_USE_TIM15 FALSE |
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#define | STM32_ICU_USE_TIM16 FALSE |
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#define | STM32_ICU_USE_TIM17 FALSE |
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#define | STM32_MAC_TRANSMIT_BUFFERS 2 |
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#define | STM32_MAC_RECEIVE_BUFFERS 4 |
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#define | STM32_MAC_BUFFERS_SIZE 1522 |
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#define | STM32_MAC_PHY_TIMEOUT 100 |
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#define | STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE |
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#define | STM32_MAC_ETH1_IRQ_PRIORITY 13 |
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#define | STM32_MAC_IP_CHECKSUM_OFFLOAD 0 |
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#define | STM32_PWM_USE_ADVANCED FALSE |
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#define | STM32_PWM_USE_TIM1 TRUE |
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#define | STM32_PWM_USE_TIM2 FALSE |
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#define | STM32_PWM_USE_TIM3 FALSE |
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#define | STM32_PWM_USE_TIM4 TRUE |
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#define | STM32_PWM_USE_TIM5 FALSE |
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#define | STM32_PWM_USE_TIM8 FALSE |
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#define | STM32_PWM_USE_TIM9 FALSE |
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#define | STM32_PWM_USE_TIM10 FALSE |
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#define | STM32_PWM_USE_TIM11 FALSE |
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#define | STM32_PWM_USE_TIM12 FALSE |
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#define | STM32_PWM_USE_TIM13 FALSE |
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#define | STM32_PWM_USE_TIM14 FALSE |
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#define | STM32_PWM_USE_TIM15 FALSE |
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#define | STM32_PWM_USE_TIM16 FALSE |
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#define | STM32_PWM_USE_TIM17 FALSE |
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#define | STM32_RTC_PRESA_VALUE 32 |
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#define | STM32_RTC_PRESS_VALUE 1024 |
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#define | STM32_RTC_CR_INIT 0 |
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#define | STM32_RTC_TAMPCR_INIT 0 |
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#define | STM32_SDMMC_MAXCLK 200000000 |
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#define | STM32_SDC_USE_SDMMC1 TRUE |
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#define | STM32_SDC_USE_SDMMC2 FALSE |
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#define | STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE |
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#define | STM32_SDC_SDMMC_WRITE_TIMEOUT 6000000 |
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#define | STM32_SDC_SDMMC_READ_TIMEOUT 6000000 |
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#define | STM32_SDC_SDMMC_CLOCK_DELAY 20 |
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#define | STM32_SDC_SDMMC_PWRSAV TRUE |
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#define | STM32_SDC_FORCE_25MHZ TRUE |
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#define | STM32_SERIAL_USE_USART1 FALSE |
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#define | STM32_SERIAL_USE_USART2 FALSE |
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#define | STM32_SERIAL_USE_USART3 FALSE |
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#define | STM32_SERIAL_USE_UART4 FALSE |
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#define | STM32_SERIAL_USE_UART5 FALSE |
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#define | STM32_SERIAL_USE_USART6 FALSE |
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#define | STM32_SERIAL_USE_UART7 FALSE |
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#define | STM32_SERIAL_USE_UART8 FALSE |
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#define | STM32_SERIAL_USE_LPUART1 FALSE |
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#define | STM32_SPI_USE_SPI1 TRUE |
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#define | STM32_SPI_USE_SPI2 TRUE |
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#define | STM32_SPI_USE_SPI3 FALSE |
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#define | STM32_SPI_USE_SPI4 FALSE |
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#define | STM32_SPI_USE_SPI5 FALSE |
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#define | STM32_SPI_USE_SPI6 FALSE |
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#define | STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_SPI_SPI1_DMA_PRIORITY 1 |
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#define | STM32_SPI_SPI2_DMA_PRIORITY 1 |
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#define | STM32_SPI_SPI3_DMA_PRIORITY 1 |
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#define | STM32_SPI_SPI4_DMA_PRIORITY 1 |
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#define | STM32_SPI_SPI5_DMA_PRIORITY 1 |
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#define | STM32_SPI_SPI6_DMA_PRIORITY 1 |
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#define | STM32_SPI_SPI1_IRQ_PRIORITY 10 |
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#define | STM32_SPI_SPI2_IRQ_PRIORITY 10 |
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#define | STM32_SPI_SPI3_IRQ_PRIORITY 10 |
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#define | STM32_SPI_SPI4_IRQ_PRIORITY 10 |
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#define | STM32_SPI_SPI5_IRQ_PRIORITY 10 |
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#define | STM32_SPI_SPI6_IRQ_PRIORITY 10 |
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#define | STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") |
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#define | STM32_ST_IRQ_PRIORITY 8 |
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#define | STM32_ST_USE_TIMER 5 |
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#define | STM32_TRNG_USE_RNG1 FALSE |
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#define | STM32_UART_USE_USART1 FALSE |
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#define | STM32_UART_USE_USART2 FALSE |
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#define | STM32_UART_USE_USART3 FALSE |
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#define | STM32_UART_USE_UART4 FALSE |
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#define | STM32_UART_USE_UART5 FALSE |
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#define | STM32_UART_USE_USART6 FALSE |
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#define | STM32_UART_USE_UART7 FALSE |
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#define | STM32_UART_USE_UART8 FALSE |
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#define | STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY |
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#define | STM32_UART_USART1_DMA_PRIORITY 1 |
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#define | STM32_UART_USART2_DMA_PRIORITY 0 |
|
#define | STM32_UART_USART3_DMA_PRIORITY 0 |
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#define | STM32_UART_UART4_DMA_PRIORITY 0 |
|
#define | STM32_UART_UART5_DMA_PRIORITY 0 |
|
#define | STM32_UART_USART6_DMA_PRIORITY 0 |
|
#define | STM32_UART_UART7_DMA_PRIORITY 0 |
|
#define | STM32_UART_UART8_DMA_PRIORITY 0 |
|
#define | STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") |
|
#define | STM32_USB_USE_OTG1 TRUE |
|
#define | STM32_USB_USE_OTG2 FALSE |
|
#define | STM32_USB_OTG1_IRQ_PRIORITY 14 |
|
#define | STM32_USB_OTG2_IRQ_PRIORITY 14 |
|
#define | STM32_USB_OTG1_RX_FIFO_SIZE 512 |
|
#define | STM32_USB_OTG2_RX_FIFO_SIZE 512 |
|
#define | STM32_USB_HOST_WAKEUP_DURATION 2 |
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#define | STM32_WDG_USE_IWDG FALSE |
|
#define | STM32_WSPI_USE_QUADSPI1 FALSE |
|
#define | STM32_WSPI_QUADSPI1_PRESCALER_VALUE ((STM32_QSPICLK / HAL_QSPI1_CLK) - 1) |
|
#define | STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY |
|
#define | STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1 |
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#define | STM32_WSPI_MDMA_ERROR_HOOK(wspip) osalSysHalt("MDMA failure") |
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#define | SDLOG_QUEUE_BUCKETS 1024 |
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#define | SDLOG_MAX_MESSAGE_LEN 300 |
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#define | SDLOG_NUM_FILES 2 |
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#define | SDLOG_ALL_BUFFERS_SIZE (SDLOG_NUM_FILES*16*1024) |
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