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mcuconf.h
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1 /*
2  ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
3 
4  Licensed under the Apache License, Version 2.0 (the "License");
5  you may not use this file except in compliance with the License.
6  You may obtain a copy of the License at
7 
8  http://www.apache.org/licenses/LICENSE-2.0
9 
10  Unless required by applicable law or agreed to in writing, software
11  distributed under the License is distributed on an "AS IS" BASIS,
12  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  See the License for the specific language governing permissions and
14  limitations under the License.
15 */
16 
17 #ifndef _MCUCONF_H_
18 #define _MCUCONF_H_
19 
20 /*
21  * STM32F4xx drivers configuration.
22  * The following settings override the default settings present in
23  * the various device driver implementation headers.
24  * Note that the settings for each driver only have effect if the whole
25  * driver is enabled in halconf.h.
26  *
27  * IRQ priorities:
28  * 15...0 Lowest...Highest.
29  *
30  * DMA priorities:
31  * 0...3 Lowest...Highest.
32  */
33 
34 #define STM32F7xx_MCUCONF
35 
36 /*
37  * HAL driver system settings.
38  */
39 #define STM32_NO_INIT FALSE
40 #define STM32_PVD_ENABLE FALSE
41 #define STM32_PLS STM32_PLS_LEV0
42 #define STM32_BKPRAM_ENABLE FALSE
43 #define STM32_HSI_ENABLED TRUE
44 #define STM32_LSI_ENABLED FALSE
45 #define STM32_HSE_ENABLED TRUE
46 #if HAL_USE_RTC // disable LSE init if not needed to start faster
47 #define STM32_LSE_ENABLED TRUE
48 #else
49 #define STM32_LSE_ENABLED FALSE
50 #endif
51 #define STM32_CLOCK48_REQUIRED TRUE
52 #define STM32_SW STM32_SW_PLL
53 #define STM32_PLLSRC STM32_PLLSRC_HSE
54 #define STM32_PLLM_VALUE 16
55 #define STM32_PLLN_VALUE 432
56 #define STM32_PLLP_VALUE 2
57 #define STM32_PLLQ_VALUE 9
58 #define STM32_HPRE STM32_HPRE_DIV1
59 #define STM32_PPRE1 STM32_PPRE1_DIV4
60 #define STM32_PPRE2 STM32_PPRE2_DIV2
61 #if HAL_USE_RTC
62 #define STM32_RTCSEL STM32_RTCSEL_LSE
63 #else
64 #define STM32_RTCSEL STM32_RTCSEL_NOCLOCK
65 #endif
66 #define STM32_RTCPRE_VALUE 25
67 #define STM32_MCO1SEL STM32_MCO1SEL_HSE
68 #define STM32_MCO1PRE STM32_MCO1PRE_DIV1
69 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
70 #define STM32_MCO2PRE STM32_MCO2PRE_DIV4
71 #define STM32_I2SSRC STM32_I2SSRC_PLLI2S
72 #define STM32_PLLI2SN_VALUE 192
73 #define STM32_PLLI2SP_VALUE 4
74 #define STM32_PLLI2SQ_VALUE 4
75 #define STM32_PLLI2SR_VALUE 4
76 #define STM32_PLLSAIN_VALUE 192
77 #define STM32_PLLSAIP_VALUE 4
78 #define STM32_PLLSAIQ_VALUE 4
79 #define STM32_PLLSAIR_VALUE 4
80 #define STM32_PLLSAIDIVR_VALUE 2
81 #define STM32_SAI1SEL STM32_SAI1SEL_OFF
82 #define STM32_SAI2SEL STM32_SAI2SEL_OFF
83 #define STM32_USART1SEL STM32_USART1SEL_PCLK2
84 #define STM32_USART2SEL STM32_USART2SEL_PCLK1
85 #define STM32_USART3SEL STM32_USART3SEL_PCLK1
86 #define STM32_UART4SEL STM32_UART4SEL_PCLK1
87 #define STM32_UART5SEL STM32_UART5SEL_PCLK1
88 #define STM32_USART6SEL STM32_USART6SEL_PCLK2
89 #define STM32_UART7SEL STM32_UART7SEL_PCLK1
90 #define STM32_UART8SEL STM32_UART8SEL_PCLK1
91 #define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 // STM32_I2C1SEL_SYSCLK
92 #define STM32_I2C2SEL STM32_I2C2SEL_PCLK1
93 #define STM32_I2C3SEL STM32_I2C3SEL_PCLK1
94 #define STM32_I2C4SEL STM32_I2C4SEL_PCLK1
95 #define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
96 #define STM32_CECSEL STM32_CECSEL_LSE
97 #define STM32_CK48MSEL STM32_CK48MSEL_PLL
98 #define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
99 #define STM32_SRAM2_NOCACHE FALSE
100 
101 /*
102  * ADC driver system settings.
103  */
104 #define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
105 #define STM32_ADC_USE_ADC1 TRUE
106 #define STM32_ADC_USE_ADC2 FALSE
107 #define STM32_ADC_USE_ADC3 FALSE
108 #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
109 #define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
110 #define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
111 #define STM32_ADC_ADC1_DMA_PRIORITY 2
112 #define STM32_ADC_ADC2_DMA_PRIORITY 2
113 #define STM32_ADC_ADC3_DMA_PRIORITY 2
114 #define STM32_ADC_IRQ_PRIORITY 6
115 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
116 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
117 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
118 
119 /*
120  * CAN driver system settings.
121  */
122 #if USE_CAN1
123 #define STM32_CAN_USE_CAN1 TRUE
124 #else
125 #define STM32_CAN_USE_CAN1 FALSE
126 #endif
127 #if USE_CAN2
128 #define STM32_CAN_USE_CAN2 TRUE
129 #else
130 #define STM32_CAN_USE_CAN2 FALSE
131 #endif
132 #define STM32_CAN_CAN1_IRQ_PRIORITY 11
133 #define STM32_CAN_CAN2_IRQ_PRIORITY 11
134 
135 /*
136  * DAC driver system settings.
137  */
138 #define STM32_DAC_DUAL_MODE FALSE
139 #define STM32_DAC_USE_DAC1_CH1 FALSE
140 #if USE_DAC1
141 #define STM32_DAC_USE_DAC1_CH2 TRUE
142 #else
143 #define STM32_DAC_USE_DAC1_CH2 FALSE
144 #endif
145 #define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
146 #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
147 #define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
148 #define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
149 //#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
150 #define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
151 
152 /*
153  * EXT driver system settings.
154  */
155 #define STM32_EXT_EXTI0_IRQ_PRIORITY 6
156 #define STM32_EXT_EXTI1_IRQ_PRIORITY 6
157 #define STM32_EXT_EXTI2_IRQ_PRIORITY 6
158 #define STM32_EXT_EXTI3_IRQ_PRIORITY 6
159 #define STM32_EXT_EXTI4_IRQ_PRIORITY 6
160 #define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
161 #define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
162 #define STM32_EXT_EXTI16_IRQ_PRIORITY 6
163 #define STM32_EXT_EXTI17_IRQ_PRIORITY 15
164 #define STM32_EXT_EXTI18_IRQ_PRIORITY 6
165 #define STM32_EXT_EXTI19_IRQ_PRIORITY 6
166 #define STM32_EXT_EXTI20_IRQ_PRIORITY 6
167 #define STM32_EXT_EXTI21_IRQ_PRIORITY 15
168 #define STM32_EXT_EXTI22_IRQ_PRIORITY 15
169 
170 /*
171  * GPT driver system settings.
172  */
173 #define STM32_GPT_USE_TIM1 FALSE
174 #define STM32_GPT_USE_TIM2 FALSE // keep free if in tickless mode
175 #define STM32_GPT_USE_TIM3 FALSE
176 #define STM32_GPT_USE_TIM4 FALSE
177 #define STM32_GPT_USE_TIM5 FALSE
178 #define STM32_GPT_USE_TIM6 FALSE
179 #define STM32_GPT_USE_TIM7 FALSE
180 #define STM32_GPT_USE_TIM8 FALSE
181 #define STM32_GPT_USE_TIM9 FALSE
182 #define STM32_GPT_USE_TIM11 FALSE
183 #define STM32_GPT_USE_TIM12 FALSE
184 #define STM32_GPT_USE_TIM14 FALSE
185 #define STM32_GPT_TIM1_IRQ_PRIORITY 7
186 #define STM32_GPT_TIM2_IRQ_PRIORITY 7
187 #define STM32_GPT_TIM3_IRQ_PRIORITY 7
188 #define STM32_GPT_TIM4_IRQ_PRIORITY 7
189 #define STM32_GPT_TIM5_IRQ_PRIORITY 7
190 #define STM32_GPT_TIM6_IRQ_PRIORITY 7
191 #define STM32_GPT_TIM7_IRQ_PRIORITY 7
192 #define STM32_GPT_TIM8_IRQ_PRIORITY 7
193 #define STM32_GPT_TIM9_IRQ_PRIORITY 7
194 #define STM32_GPT_TIM11_IRQ_PRIORITY 7
195 #define STM32_GPT_TIM12_IRQ_PRIORITY 7
196 #define STM32_GPT_TIM14_IRQ_PRIORITY 7
197 
198 /*
199  * I2C driver system settings.
200  */
201 #if USE_I2C1
202 #define STM32_I2C_USE_I2C1 TRUE
203 #else
204 #define STM32_I2C_USE_I2C1 FALSE
205 #endif
206 #if USE_I2C2 // CAN or I2C2 because of dma conflict
207 #define STM32_I2C_USE_I2C2 TRUE
208 #else
209 #define STM32_I2C_USE_I2C2 FALSE
210 #endif
211 #define STM32_I2C_USE_I2C3 FALSE
212 #define STM32_I2C_USE_I2C4 FALSE
213 #define STM32_I2C_BUSY_TIMEOUT 50
214 #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
215 #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
216 #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
217 #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
218 //#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
219 //#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
220 //#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
221 //#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
222 #define STM32_I2C_I2C1_IRQ_PRIORITY 5
223 #define STM32_I2C_I2C2_IRQ_PRIORITY 5
224 #define STM32_I2C_I2C3_IRQ_PRIORITY 5
225 #define STM32_I2C_I2C4_IRQ_PRIORITY 5
226 #define STM32_I2C_I2C1_DMA_PRIORITY 3
227 #define STM32_I2C_I2C2_DMA_PRIORITY 3
228 #define STM32_I2C_I2C3_DMA_PRIORITY 3
229 #define STM32_I2C_I2C4_DMA_PRIORITY 3
230 #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
231 
232 /*
233  * ICU driver system settings.
234  */
235 #define STM32_ICU_USE_TIM1 FALSE
236 #ifdef USE_PWM_INPUT1
237 #define STM32_ICU_USE_TIM2 TRUE
238 #else
239 #define STM32_ICU_USE_TIM2 FALSE // keep free if in tickless mode
240 #endif
241 #define STM32_ICU_USE_TIM3 FALSE
242 #define STM32_ICU_USE_TIM4 FALSE
243 #if RADIO_CONTROL_TYPE_PPM
244 #define STM32_ICU_USE_TIM5 TRUE
245 #else
246 #define STM32_ICU_USE_TIM5 FALSE
247 #endif
248 #ifdef USE_PWM_INPUT2
249 #define STM32_ICU_USE_TIM8 TRUE
250 #else
251 #define STM32_ICU_USE_TIM8 FALSE
252 #endif
253 #define STM32_ICU_USE_TIM9 FALSE
254 #define STM32_ICU_TIM1_IRQ_PRIORITY 7
255 #define STM32_ICU_TIM2_IRQ_PRIORITY 7
256 #define STM32_ICU_TIM3_IRQ_PRIORITY 7
257 #define STM32_ICU_TIM4_IRQ_PRIORITY 7
258 #define STM32_ICU_TIM5_IRQ_PRIORITY 7
259 #define STM32_ICU_TIM8_IRQ_PRIORITY 7
260 #define STM32_ICU_TIM9_IRQ_PRIORITY 7
261 
262 /*
263  * MAC driver system settings.
264  */
265 #define STM32_MAC_TRANSMIT_BUFFERS 2
266 #define STM32_MAC_RECEIVE_BUFFERS 4
267 #define STM32_MAC_BUFFERS_SIZE 1522
268 #define STM32_MAC_PHY_TIMEOUT 100
269 #define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
270 #define STM32_MAC_ETH1_IRQ_PRIORITY 13
271 #define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
272 
273 /*
274  * PWM driver system settings.
275  */
276 #define STM32_PWM_USE_ADVANCED FALSE
277 #define STM32_PWM_USE_TIM1 FALSE
278 #ifndef STM32_PWM_USE_TIM2
279 #define STM32_PWM_USE_TIM2 FALSE // keep free if in tickless mode, can be used in systick mode
280 #endif
281 #ifndef STM32_PWM_USE_TIM3
282 #define STM32_PWM_USE_TIM3 TRUE
283 #endif
284 #ifndef STM32_PWM_USE_TIM4
285 #define STM32_PWM_USE_TIM4 TRUE
286 #endif
287 #define STM32_PWM_USE_TIM5 FALSE
288 #define STM32_PWM_USE_TIM8 FALSE
289 #define STM32_PWM_USE_TIM9 FALSE
290 #define STM32_PWM_TIM1_IRQ_PRIORITY 7
291 #define STM32_PWM_TIM2_IRQ_PRIORITY 7
292 #define STM32_PWM_TIM3_IRQ_PRIORITY 7
293 #define STM32_PWM_TIM4_IRQ_PRIORITY 7
294 #define STM32_PWM_TIM5_IRQ_PRIORITY 7
295 #define STM32_PWM_TIM8_IRQ_PRIORITY 7
296 #define STM32_PWM_TIM9_IRQ_PRIORITY 7
297 
298 /*
299  * SERIAL driver system settings.
300  */
301 #if USE_UART1
302 #define STM32_SERIAL_USE_USART1 TRUE
303 #else
304 #define STM32_SERIAL_USE_USART1 FALSE
305 #endif
306 #if USE_UART2
307 #define STM32_SERIAL_USE_USART2 TRUE
308 #else
309 #define STM32_SERIAL_USE_USART2 FALSE
310 #endif
311 #if USE_UART3
312 #define STM32_SERIAL_USE_USART3 TRUE
313 #else
314 #define STM32_SERIAL_USE_USART3 FALSE
315 #endif
316 #if USE_UART4
317 #define STM32_SERIAL_USE_UART4 TRUE
318 #else
319 #define STM32_SERIAL_USE_UART4 FALSE
320 #endif
321 #if USE_UART5
322 #define STM32_SERIAL_USE_UART5 TRUE
323 #else
324 #define STM32_SERIAL_USE_UART5 FALSE
325 #endif
326 #if USE_UART6
327 #define STM32_SERIAL_USE_USART6 TRUE
328 #else
329 #define STM32_SERIAL_USE_USART6 FALSE
330 #endif
331 #if USE_UART7
332 #define STM32_SERIAL_USE_UART7 TRUE
333 #else
334 #define STM32_SERIAL_USE_UART7 FALSE
335 #endif
336 #if USE_UART8
337 #define STM32_SERIAL_USE_UART8 TRUE
338 #else
339 #define STM32_SERIAL_USE_UART8 FALSE
340 #endif
341 #define STM32_SERIAL_USART1_PRIORITY 12
342 #define STM32_SERIAL_USART2_PRIORITY 12
343 #define STM32_SERIAL_USART3_PRIORITY 12
344 #define STM32_SERIAL_UART4_PRIORITY 12
345 #define STM32_SERIAL_UART5_PRIORITY 12
346 #define STM32_SERIAL_USART6_PRIORITY 12
347 #define STM32_SERIAL_UART7_PRIORITY 12
348 #define STM32_SERIAL_UART8_PRIORITY 12
349 
350 /*
351  * SPI driver system settings.
352  */
353 #if USE_SPI1
354 #define STM32_SPI_USE_SPI1 TRUE
355 #else
356 #define STM32_SPI_USE_SPI1 FALSE
357 #endif
358 #define STM32_SPI_USE_SPI2 FALSE
359 #define STM32_SPI_USE_SPI3 FALSE
360 #define STM32_SPI_USE_SPI4 FALSE
361 #define STM32_SPI_USE_SPI5 FALSE
362 #define STM32_SPI_USE_SPI6 FALSE
363 #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
364 #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
365 #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
366 #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
367 #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
368 #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
369 #define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
370 #define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
371 #define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
372 #define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
373 //#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
374 #define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
375 #define STM32_SPI_SPI1_DMA_PRIORITY 1
376 #define STM32_SPI_SPI2_DMA_PRIORITY 1
377 #define STM32_SPI_SPI3_DMA_PRIORITY 1
378 #define STM32_SPI_SPI4_DMA_PRIORITY 1
379 #define STM32_SPI_SPI4_DMA_PRIORITY 1
380 #define STM32_SPI_SPI4_DMA_PRIORITY 1
381 #define STM32_SPI_SPI1_IRQ_PRIORITY 10
382 #define STM32_SPI_SPI2_IRQ_PRIORITY 10
383 #define STM32_SPI_SPI3_IRQ_PRIORITY 10
384 #define STM32_SPI_SPI4_IRQ_PRIORITY 10
385 #define STM32_SPI_SPI5_IRQ_PRIORITY 10
386 #define STM32_SPI_SPI6_IRQ_PRIORITY 10
387 #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
388 
389 /*
390  * ST driver system settings.
391  */
392 #define STM32_ST_IRQ_PRIORITY 8
393 #define STM32_ST_USE_TIMER 2
394 
395 /*
396  * UART driver system settings.
397  */
398 #define STM32_UART_USE_USART1 FALSE /* DMA OK */
399 #define STM32_UART_USE_USART2 FALSE /* NO DMA AVAIL */
400 #define STM32_UART_USE_USART3 FALSE /* DMA OK */
401 #define STM32_UART_USE_UART4 FALSE /* NO DMA AVAIL */
402 #define STM32_UART_USE_UART5 FALSE /* NO DMA AVAIL */
403 #define STM32_UART_USE_USART6 FALSE /* NO DMA AVAIL */
404 #define STM32_UART_USE_UART7 FALSE /* NO DMA AVAIL */
405 #define STM32_UART_USE_UART8 FALSE /* NO DMA AVAIL */
406 #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
407 #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
408 /* #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) */
409 /* #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) */
410 #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
411 #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
412 /* #define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) */
413 /* #define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) */
414 /* #define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) */
415 /* #define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) */
416 /* #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) */
417 /* #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) */
418 /* #define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) */
419 /* #define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) */
420 /* #define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) */
421 /* #define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) */
422 #define STM32_UART_USART1_IRQ_PRIORITY 12
423 #define STM32_UART_USART2_IRQ_PRIORITY 12
424 #define STM32_UART_USART3_IRQ_PRIORITY 12
425 #define STM32_UART_UART4_IRQ_PRIORITY 12
426 #define STM32_UART_UART5_IRQ_PRIORITY 12
427 #define STM32_UART_USART6_IRQ_PRIORITY 12
428 #define STM32_UART_USART1_DMA_PRIORITY 0
429 #define STM32_UART_USART2_DMA_PRIORITY 0
430 #define STM32_UART_USART3_DMA_PRIORITY 0
431 #define STM32_UART_UART4_DMA_PRIORITY 0
432 #define STM32_UART_UART5_DMA_PRIORITY 0
433 #define STM32_UART_USART6_DMA_PRIORITY 0
434 #define STM32_UART_UART7_DMA_PRIORITY 0
435 #define STM32_UART_UART8_DMA_PRIORITY 0
436 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
437 
438 /*
439  * USB driver system settings.
440  */
441 #define STM32_USB_USE_OTG1 TRUE
442 #define STM32_USB_USE_OTG2 FALSE
443 #define STM32_USB_OTG1_IRQ_PRIORITY 14
444 #define STM32_USB_OTG2_IRQ_PRIORITY 14
445 #define STM32_USB_OTG1_RX_FIFO_SIZE 512
446 #define STM32_USB_OTG2_RX_FIFO_SIZE 1024
447 #define STM32_USB_OTG_THREAD_PRIO LOWPRIO
448 #define STM32_USB_OTG_THREAD_STACK_SIZE 128
449 #define STM32_USB_OTGFIFO_FILL_BASEPRI 0
450 
451 /*
452  * SDC driver system settings.
453  */
454 #define STM32_SDC_USE_SDMMC1 TRUE
455 #define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE
456 #define STM32_SDC_SDMMC_WRITE_TIMEOUT 250
457 #define STM32_SDC_SDMMC_READ_TIMEOUT 25
458 #define STM32_SDC_SDMMC_CLOCK_DELAY 10
459 #define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
460 #define STM32_SDC_SDMMC1_DMA_PRIORITY 3
461 #define STM32_SDC_SDMMC1_IRQ_PRIORITY 9
462 
463 /*
464  sdlog message buffer and queue configuration
465  */
466 #define SDLOG_QUEUE_BUCKETS 1024
467 #define SDLOG_MAX_MESSAGE_LEN 300
468 #define SDLOG_NUM_FILES 2
469 #define SDLOG_ALL_BUFFERS_SIZE (SDLOG_NUM_FILES*16*1024)
470 
471 /*
472  * WDG driver system settings.
473  */
474 #define STM32_WDG_USE_IWDG FALSE
475 
476 
477 //#define CH_HEAP_SIZE (32*1024)
478 //#define CH_HEAP_USE_TLSF 1 // if 0 or undef, chAlloc will be used
479 
480 
481 
482 #endif /* _MCUCONF_H_ */