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mcuconf.h
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1 /*
2  ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3 
4  Licensed under the Apache License, Version 2.0 (the "License");
5  you may not use this file except in compliance with the License.
6  You may obtain a copy of the License at
7 
8  http://www.apache.org/licenses/LICENSE-2.0
9 
10  Unless required by applicable law or agreed to in writing, software
11  distributed under the License is distributed on an "AS IS" BASIS,
12  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  See the License for the specific language governing permissions and
14  limitations under the License.
15 */
16 
17 #ifndef MCUCONF_H
18 #define MCUCONF_H
19 
20 /*
21  * STM32F4xx drivers configuration.
22  * The following settings override the default settings present in
23  * the various device driver implementation headers.
24  * Note that the settings for each driver only have effect if the whole
25  * driver is enabled in halconf.h.
26  *
27  * IRQ priorities:
28  * 15...0 Lowest...Highest.
29  *
30  * DMA priorities:
31  * 0...3 Lowest...Highest.
32  */
33 
34 #define STM32F4xx_MCUCONF
35 #define STM32F405_MCUCONF
36 #define STM32F415_MCUCONF
37 #define STM32F407_MCUCONF
38 #define STM32F417_MCUCONF
39 
40 /*
41  * HAL driver system settings.
42  */
43 #define STM32_NO_INIT FALSE
44 #define STM32_PVD_ENABLE FALSE
45 #define STM32_PLS STM32_PLS_LEV0
46 #define STM32_BKPRAM_ENABLE FALSE
47 #define STM32_HSI_ENABLED TRUE
48 #define STM32_LSI_ENABLED FALSE
49 #define STM32_HSE_ENABLED TRUE
50 #define STM32_LSE_ENABLED TRUE
51 #define STM32_CLOCK48_REQUIRED TRUE
52 #define STM32_SW STM32_SW_PLL
53 #define STM32_PLLSRC STM32_PLLSRC_HSE
54 #define STM32_PLLM_VALUE 16
55 #define STM32_PLLN_VALUE 336
56 #define STM32_PLLP_VALUE 2
57 #define STM32_PLLQ_VALUE 7
58 #define STM32_HPRE STM32_HPRE_DIV1
59 #define STM32_PPRE1 STM32_PPRE1_DIV4
60 #define STM32_PPRE2 STM32_PPRE2_DIV2
61 #define STM32_RTCSEL STM32_RTCSEL_LSE
62 #define STM32_RTCPRE_VALUE 8
63 #define STM32_MCO1SEL STM32_MCO1SEL_HSI
64 #define STM32_MCO1PRE STM32_MCO1PRE_DIV1
65 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
66 #define STM32_MCO2PRE STM32_MCO2PRE_DIV5
67 #define STM32_I2SSRC STM32_I2SSRC_CKIN
68 #define STM32_PLLI2SN_VALUE 192
69 #define STM32_PLLI2SR_VALUE 5
70 
71 /*
72  * IRQ system settings.
73  */
74 #define STM32_IRQ_EXTI0_PRIORITY 6
75 #define STM32_IRQ_EXTI1_PRIORITY 6
76 #define STM32_IRQ_EXTI2_PRIORITY 6
77 #define STM32_IRQ_EXTI3_PRIORITY 6
78 #define STM32_IRQ_EXTI4_PRIORITY 6
79 #define STM32_IRQ_EXTI5_9_PRIORITY 6
80 #define STM32_IRQ_EXTI10_15_PRIORITY 6
81 #define STM32_IRQ_EXTI16_PRIORITY 6
82 #define STM32_IRQ_EXTI17_PRIORITY 15
83 #define STM32_IRQ_EXTI18_PRIORITY 6
84 #define STM32_IRQ_EXTI19_PRIORITY 6
85 #define STM32_IRQ_EXTI20_PRIORITY 6
86 #define STM32_IRQ_EXTI21_PRIORITY 15
87 #define STM32_IRQ_EXTI22_PRIORITY 15
88 
89 /*
90  * ADC driver system settings.
91  */
92 #define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV8
93 #define STM32_ADC_USE_ADC1 TRUE
94 #define STM32_ADC_USE_ADC2 FALSE
95 #define STM32_ADC_USE_ADC3 FALSE
96 #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
97 #define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
98 #define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
99 #define STM32_ADC_ADC1_DMA_PRIORITY 2
100 #define STM32_ADC_ADC2_DMA_PRIORITY 2
101 #define STM32_ADC_ADC3_DMA_PRIORITY 2
102 #define STM32_ADC_IRQ_PRIORITY 6
103 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
104 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
105 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
106 
107 /*
108  * CAN driver system settings.
109  */
110 #if USE_CAN1
111 #define STM32_CAN_USE_CAN1 TRUE
112 #else
113 #define STM32_CAN_USE_CAN1 FALSE
114 #endif
115 #if USE_CAN2
116 #define STM32_CAN_USE_CAN2 TRUE
117 #else
118 #define STM32_CAN_USE_CAN2 FALSE
119 #endif
120 #define STM32_CAN_CAN1_IRQ_PRIORITY 11
121 #define STM32_CAN_CAN2_IRQ_PRIORITY 11
122 
123 /*
124  * DAC driver system settings.
125  */
126 #define STM32_DAC_DUAL_MODE FALSE
127 #define STM32_DAC_USE_DAC1_CH1 FALSE
128 #define STM32_DAC_USE_DAC1_CH2 FALSE
129 #define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
130 #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
131 #define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
132 #define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
133 #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
134 #define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
135 
136 /*
137  * GPT driver system settings.
138  */
139 #define STM32_GPT_USE_TIM1 FALSE
140 #define STM32_GPT_USE_TIM2 FALSE
141 #define STM32_GPT_USE_TIM3 FALSE
142 #define STM32_GPT_USE_TIM4 FALSE
143 #define STM32_GPT_USE_TIM5 FALSE
144 #define STM32_GPT_USE_TIM6 FALSE
145 #define STM32_GPT_USE_TIM7 FALSE
146 #define STM32_GPT_USE_TIM8 FALSE
147 #define STM32_GPT_USE_TIM9 FALSE
148 #define STM32_GPT_USE_TIM11 FALSE
149 #define STM32_GPT_USE_TIM12 FALSE
150 #define STM32_GPT_USE_TIM14 FALSE
151 #define STM32_GPT_TIM1_IRQ_PRIORITY 7
152 #define STM32_GPT_TIM2_IRQ_PRIORITY 7
153 #define STM32_GPT_TIM3_IRQ_PRIORITY 7
154 #define STM32_GPT_TIM4_IRQ_PRIORITY 7
155 #define STM32_GPT_TIM5_IRQ_PRIORITY 7
156 #define STM32_GPT_TIM6_IRQ_PRIORITY 7
157 #define STM32_GPT_TIM7_IRQ_PRIORITY 7
158 #define STM32_GPT_TIM8_IRQ_PRIORITY 7
159 #define STM32_GPT_TIM9_IRQ_PRIORITY 7
160 #define STM32_GPT_TIM11_IRQ_PRIORITY 7
161 #define STM32_GPT_TIM12_IRQ_PRIORITY 7
162 #define STM32_GPT_TIM14_IRQ_PRIORITY 7
163 
164 /*
165  * I2C driver system settings.
166  */
167 #if USE_I2C1
168 #define STM32_I2C_USE_I2C1 TRUE
169 #else
170 #define STM32_I2C_USE_I2C1 FALSE
171 #endif
172 #if USE_I2C2
173 #define STM32_I2C_USE_I2C2 TRUE
174 #else
175 #define STM32_I2C_USE_I2C2 FALSE
176 #endif
177 #if USE_I2C3
178 #define STM32_I2C_USE_I2C3 TRUE
179 #else
180 #define STM32_I2C_USE_I2C3 FALSE
181 #endif
182 #define STM32_I2C_BUSY_TIMEOUT 50
183 #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
184 #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
185 #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
186 #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
187 #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
188 #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
189 #define STM32_I2C_I2C1_IRQ_PRIORITY 5
190 #define STM32_I2C_I2C2_IRQ_PRIORITY 5
191 #define STM32_I2C_I2C3_IRQ_PRIORITY 5
192 #define STM32_I2C_I2C1_DMA_PRIORITY 3
193 #define STM32_I2C_I2C2_DMA_PRIORITY 3
194 #define STM32_I2C_I2C3_DMA_PRIORITY 3
195 #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
196 
197 /*
198  * I2S driver system settings.
199  */
200 #define STM32_I2S_USE_SPI2 FALSE
201 #define STM32_I2S_USE_SPI3 FALSE
202 #define STM32_I2S_SPI2_IRQ_PRIORITY 10
203 #define STM32_I2S_SPI3_IRQ_PRIORITY 10
204 #define STM32_I2S_SPI2_DMA_PRIORITY 1
205 #define STM32_I2S_SPI3_DMA_PRIORITY 1
206 #define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
207 #define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
208 #define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
209 #define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
210 #define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
211 
212 /*
213  * ICU driver system settings.
214  */
215 #define STM32_ICU_USE_TIM1 TRUE
216 #define STM32_ICU_USE_TIM2 FALSE
217 #define STM32_ICU_USE_TIM3 FALSE
218 #define STM32_ICU_USE_TIM4 FALSE
219 #define STM32_ICU_USE_TIM5 TRUE
220 #define STM32_ICU_USE_TIM8 FALSE
221 #define STM32_ICU_USE_TIM9 FALSE
222 #define STM32_ICU_TIM1_IRQ_PRIORITY 7
223 #define STM32_ICU_TIM2_IRQ_PRIORITY 7
224 #define STM32_ICU_TIM3_IRQ_PRIORITY 7
225 #define STM32_ICU_TIM4_IRQ_PRIORITY 7
226 #define STM32_ICU_TIM5_IRQ_PRIORITY 7
227 #define STM32_ICU_TIM8_IRQ_PRIORITY 7
228 #define STM32_ICU_TIM9_IRQ_PRIORITY 7
229 
230 /*
231  * MAC driver system settings.
232  */
233 #define STM32_MAC_TRANSMIT_BUFFERS 2
234 #define STM32_MAC_RECEIVE_BUFFERS 4
235 #define STM32_MAC_BUFFERS_SIZE 1522
236 #define STM32_MAC_PHY_TIMEOUT 100
237 #define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
238 #define STM32_MAC_ETH1_IRQ_PRIORITY 13
239 #define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
240 
241 /*
242  * PWM driver system settings.
243  */
244 #define STM32_PWM_USE_ADVANCED FALSE
245 #ifndef STM32_PWM_USE_TIM1
246 #define STM32_PWM_USE_TIM1 FALSE // enable for WS2812
247 #endif
248 #ifndef STM32_PWM_USE_TIM2
249 #define STM32_PWM_USE_TIM2 TRUE
250 #endif
251 #ifndef STM32_PWM_USE_TIM3
252 #define STM32_PWM_USE_TIM3 TRUE
253 #endif
254 #define STM32_PWM_USE_TIM4 FALSE
255 #define STM32_PWM_USE_TIM5 FALSE
256 #define STM32_PWM_USE_TIM8 FALSE
257 #define STM32_PWM_USE_TIM9 FALSE
258 #define STM32_PWM_TIM1_IRQ_PRIORITY 7
259 #define STM32_PWM_TIM2_IRQ_PRIORITY 7
260 #define STM32_PWM_TIM3_IRQ_PRIORITY 7
261 #define STM32_PWM_TIM4_IRQ_PRIORITY 7
262 #define STM32_PWM_TIM5_IRQ_PRIORITY 7
263 #define STM32_PWM_TIM8_IRQ_PRIORITY 7
264 #define STM32_PWM_TIM9_IRQ_PRIORITY 7
265 
266 #define STM32_PWM1_UP_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) // incompatible with SPI1_TX
267 #define STM32_PWM1_UP_DMA_CHANNEL 6
268 #define STM32_PWM1_UP_DMA_IRQ_PRIORITY 6
269 #define STM32_PWM1_UP_DMA_PRIORITY 2
270 
271 #define STM32_PWM2_UP_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
272 #define STM32_PWM2_UP_DMA_CHANNEL 3
273 #define STM32_PWM2_UP_DMA_IRQ_PRIORITY 6
274 #define STM32_PWM2_UP_DMA_PRIORITY 2
275 
276 #define STM32_PWM3_UP_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
277 #define STM32_PWM3_UP_DMA_CHANNEL 5
278 #define STM32_PWM3_UP_DMA_IRQ_PRIORITY 6
279 #define STM32_PWM3_UP_DMA_PRIORITY 2
280 
281 /*
282  * RTC driver system settings.
283  */
284 #define STM32_RTC_PRESA_VALUE 32
285 #define STM32_RTC_PRESS_VALUE 1024
286 #define STM32_RTC_CR_INIT 0
287 #define STM32_RTC_TAMPCR_INIT 0
288 
289 /*
290  * SDC driver system settings.
291  */
292 #define STM32_SDC_SDIO_DMA_PRIORITY 3
293 #define STM32_SDC_SDIO_IRQ_PRIORITY 9
294 #define STM32_SDC_WRITE_TIMEOUT_MS 250
295 #define STM32_SDC_READ_TIMEOUT_MS 15
296 #define STM32_SDC_CLOCK_ACTIVATION_DELAY 10
297 #define STM32_SDC_SDIO_UNALIGNED_SUPPORT FALSE
298 #define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
299 
300 /*
301  * SERIAL driver system settings.
302  */
303 #if USE_UART1
304 #define STM32_SERIAL_USE_USART1 TRUE
305 #else
306 #define STM32_SERIAL_USE_USART1 FALSE
307 #endif
308 #if USE_UART2
309 #define STM32_SERIAL_USE_USART2 TRUE
310 #else
311 #define STM32_SERIAL_USE_USART2 FALSE
312 #endif
313 #if USE_UART3
314 #define STM32_SERIAL_USE_USART3 TRUE
315 #else
316 #define STM32_SERIAL_USE_USART3 FALSE
317 #endif
318 #if USE_UART4
319 #define STM32_SERIAL_USE_UART4 TRUE
320 #else
321 #define STM32_SERIAL_USE_UART4 FALSE
322 #endif
323 #if USE_UART5
324 #define STM32_SERIAL_USE_UART5 TRUE
325 #else
326 #define STM32_SERIAL_USE_UART5 FALSE
327 #endif
328 #if USE_UART6
329 #define STM32_SERIAL_USE_USART6 TRUE
330 #else
331 #define STM32_SERIAL_USE_USART6 FALSE
332 #endif
333 #define STM32_SERIAL_USART1_PRIORITY 12
334 #define STM32_SERIAL_USART2_PRIORITY 12
335 #define STM32_SERIAL_USART3_PRIORITY 12
336 #define STM32_SERIAL_UART4_PRIORITY 12
337 #define STM32_SERIAL_UART5_PRIORITY 12
338 #define STM32_SERIAL_USART6_PRIORITY 12
339 
340 /*
341  * SPI driver system settings.
342  */
343 #if USE_SPI1
344 #define STM32_SPI_USE_SPI1 TRUE
345 #else
346 #define STM32_SPI_USE_SPI1 FALSE
347 #endif
348 #if USE_SPI2
349 #define STM32_SPI_USE_SPI2 TRUE
350 #else
351 #define STM32_SPI_USE_SPI2 FALSE
352 #endif
353 #if USE_SPI3
354 #define STM32_SPI_USE_SPI3 TRUE
355 #else
356 #define STM32_SPI_USE_SPI3 FALSE
357 #endif
358 #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
359 #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
360 #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
361 #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
362 #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
363 #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
364 #define STM32_SPI_SPI1_DMA_PRIORITY 1
365 #define STM32_SPI_SPI2_DMA_PRIORITY 1
366 #define STM32_SPI_SPI3_DMA_PRIORITY 1
367 #define STM32_SPI_SPI1_IRQ_PRIORITY 10
368 #define STM32_SPI_SPI2_IRQ_PRIORITY 10
369 #define STM32_SPI_SPI3_IRQ_PRIORITY 10
370 #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
371 
372 /*
373  * ST driver system settings.
374  */
375 #define STM32_ST_IRQ_PRIORITY 8
376 #define STM32_ST_USE_TIMER 2
377 
378 /*
379  * UART driver system settings.
380  */
381 #define STM32_UART_USE_USART1 FALSE
382 #define STM32_UART_USE_USART2 FALSE
383 #define STM32_UART_USE_USART3 FALSE
384 #define STM32_UART_USE_UART4 FALSE
385 #define STM32_UART_USE_UART5 FALSE
386 #define STM32_UART_USE_USART6 FALSE
387 #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) // Not used: conflict SPI1
388 #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
389 #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
390 #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
391 #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
392 #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
393 #define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
394 #define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
395 #define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
396 #define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
397 #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
398 #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
399 #define STM32_UART_USART1_IRQ_PRIORITY 12
400 #define STM32_UART_USART2_IRQ_PRIORITY 12
401 #define STM32_UART_USART3_IRQ_PRIORITY 12
402 #define STM32_UART_UART4_IRQ_PRIORITY 12
403 #define STM32_UART_UART5_IRQ_PRIORITY 12
404 #define STM32_UART_USART6_IRQ_PRIORITY 12
405 #define STM32_UART_USART1_DMA_PRIORITY 1
406 #define STM32_UART_USART2_DMA_PRIORITY 0
407 #define STM32_UART_USART3_DMA_PRIORITY 0
408 #define STM32_UART_UART4_DMA_PRIORITY 0
409 #define STM32_UART_UART5_DMA_PRIORITY 0
410 #define STM32_UART_USART6_DMA_PRIORITY 0
411 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
412 
413 /*
414  * USB driver system settings.
415  */
416 #define STM32_USB_USE_OTG1 TRUE // FS, DFU_BOOT
417 #define STM32_USB_USE_OTG2 FALSE // HS
418 #define STM32_USB_OTG1_IRQ_PRIORITY 14
419 #define STM32_USB_OTG2_IRQ_PRIORITY 14
420 #define STM32_USB_OTG1_RX_FIFO_SIZE 512
421 #define STM32_USB_OTG2_RX_FIFO_SIZE 512
422 #define STM32_USB_HOST_WAKEUP_DURATION 2
423 
424 /*
425  * WDG driver system settings.
426  */
427 #define STM32_WDG_USE_IWDG FALSE
428 
429 
430 /*
431  sdlog message buffer and queue configuration
432  */
433 #define SDLOG_QUEUE_BUCKETS 1024
434 #define SDLOG_MAX_MESSAGE_LEN 300
435 #define SDLOG_NUM_FILES 2
436 #define SDLOG_ALL_BUFFERS_SIZE (SDLOG_NUM_FILES*8*1024)
437 
438 
439 
440 
441 #endif /* _MCUCONF_H_ */