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stm32f4_chibios_vectors.h
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1 #pragma once
2 
3 /*
4 # ______
5 # | ____|
6 # | |__ _ __ ___ _ __ ___
7 # | __| | '__| / _ \ | '_ ` _ \
8 # | | | | | (_) | | | | | | |
9 # |_| |_| \___/ |_| |_| |_|
10 # ____ _ __ _____ __ __ ____
11 # / __ \ | '_ \ / ____| | \/ | |___ \
12 # | | | | | |_) | ___ _ __ | | | \ / | __) |
13 # | | | | | .__/ / _ \ | '_ \ | | | |\/| | |__ <
14 # | |__| | | | | __/ | | | | | |____ | | | | ___) |
15 # \____/ |_| \___| |_| |_| \_____| |_| |_| |____/
16 */
17 
18 #define NVIC_NVIC_WWDG_IRQ 0
19 #define NVIC_PVD_IRQ 1
20 #define NVIC_TAMP_STAMP_IRQ 2
21 #define NVIC_RTC_WKUP_IRQ 3
22 #define NVIC_FLASH_IRQ 4
23 #define NVIC_RCC_IRQ 5
24 #define NVIC_EXTI0_IRQ 6
25 #define NVIC_EXTI1_IRQ 7
26 #define NVIC_EXTI2_IRQ 8
27 #define NVIC_EXTI3_IRQ 9
28 #define NVIC_EXTI4_IRQ 10
29 #define NVIC_DMA1_STREAM0_IRQ 11
30 #define NVIC_DMA1_STREAM1_IRQ 12
31 #define NVIC_DMA1_STREAM2_IRQ 13
32 #define NVIC_DMA1_STREAM3_IRQ 14
33 #define NVIC_DMA1_STREAM4_IRQ 15
34 #define NVIC_DMA1_STREAM5_IRQ 16
35 #define NVIC_DMA1_STREAM6_IRQ 17
36 #define NVIC_ADC_IRQ 18
37 #define NVIC_CAN1_TX_IRQ 19
38 #define NVIC_CAN1_RX0_IRQ 20
39 #define NVIC_CAN1_RX1_IRQ 21
40 #define NVIC_CAN1_SCE_IRQ 22
41 #define NVIC_EXTI9_5_IRQ 23
42 #define NVIC_TIM1_BRK_TIM9_IRQ 24
43 #define NVIC_TIM1_UP_TIM10_IRQ 25
44 #define NVIC_TIM1_TRG_COM_TIM11_IRQ 26
45 #define NVIC_TIM1_CC_IRQ 27
46 #define NVIC_TIM2_IRQ 28
47 #define NVIC_TIM3_IRQ 29
48 #define NVIC_TIM4_IRQ 30
49 #define NVIC_I2C1_EV_IRQ 31
50 #define NVIC_I2C1_ER_IRQ 32
51 #define NVIC_I2C2_EV_IRQ 33
52 #define NVIC_I2C2_ER_IRQ 34
53 #define NVIC_SPI1_IRQ 35
54 #define NVIC_SPI2_IRQ 36
55 #define NVIC_USART1_IRQ 37
56 #define NVIC_USART2_IRQ 38
57 #define NVIC_USART3_IRQ 39
58 #define NVIC_EXTI15_10_IRQ 40
59 #define NVIC_RTC_ALARM_IRQ 41
60 #define NVIC_USB_FS_WKUP_IRQ 42
61 #define NVIC_TIM8_BRK_TIM12_IRQ 43
62 #define NVIC_TIM8_UP_TIM13_IRQ 44
63 #define NVIC_TIM8_TRG_COM_TIM14_IRQ 45
64 #define NVIC_TIM8_CC_IRQ 46
65 #define NVIC_DMA1_STREAM7_IRQ 47
66 #define NVIC_FSMC_IRQ 48
67 #define NVIC_SDIO_IRQ 49
68 #define NVIC_TIM5_IRQ 50
69 #define NVIC_SPI3_IRQ 51
70 #define NVIC_UART4_IRQ 52
71 #define NVIC_UART5_IRQ 53
72 #define NVIC_TIM6_DAC_IRQ 54
73 #define NVIC_TIM7_IRQ 55
74 #define NVIC_DMA2_STREAM0_IRQ 56
75 #define NVIC_DMA2_STREAM1_IRQ 57
76 #define NVIC_DMA2_STREAM2_IRQ 58
77 #define NVIC_DMA2_STREAM3_IRQ 59
78 #define NVIC_DMA2_STREAM4_IRQ 60
79 #define NVIC_ETH_IRQ 61
80 #define NVIC_ETH_WKUP_IRQ 62
81 #define NVIC_CAN2_TX_IRQ 63
82 #define NVIC_CAN2_RX0_IRQ 64
83 #define NVIC_CAN2_RX1_IRQ 65
84 #define NVIC_CAN2_SCE_IRQ 66
85 #define NVIC_OTG_FS_IRQ 67
86 #define NVIC_DMA2_STREAM5_IRQ 68
87 #define NVIC_DMA2_STREAM6_IRQ 69
88 #define NVIC_DMA2_STREAM7_IRQ 70
89 #define NVIC_USART6_IRQ 71
90 #define NVIC_I2C3_EV_IRQ 72
91 #define NVIC_I2C3_ER_IRQ 73
92 #define NVIC_OTG_HS_EP1_OUT_IRQ 74
93 #define NVIC_OTG_HS_EP1_IN_IRQ 75
94 #define NVIC_OTG_HS_WKUP_IRQ 76
95 #define NVIC_OTG_HS_IRQ 77
96 #define NVIC_DCMI_IRQ 78
97 #define NVIC_CRYP_IRQ 79
98 #define NVIC_HASH_RNG_IRQ 80
99 #define NVIC_IRQ_COUNT 81
100 
101 #define CM3_WEAK extern void __attribute__ ((weak))
102 
103 CM3_WEAK nvic_wwdg_isr(void);
104 CM3_WEAK pvd_isr(void);
106 CM3_WEAK rtc_wkup_isr(void);
107 CM3_WEAK flash_isr(void);
108 CM3_WEAK rcc_isr(void);
109 CM3_WEAK exti0_isr(void);
110 CM3_WEAK exti1_isr(void);
111 CM3_WEAK exti2_isr(void);
112 CM3_WEAK exti3_isr(void);
113 CM3_WEAK exti4_isr(void);
121 CM3_WEAK adc_isr(void);
122 CM3_WEAK can1_tx_isr(void);
123 CM3_WEAK can1_rx0_isr(void);
124 CM3_WEAK can1_rx1_isr(void);
125 CM3_WEAK can1_sce_isr(void);
126 CM3_WEAK exti9_5_isr(void);
130 CM3_WEAK tim1_cc_isr(void);
131 CM3_WEAK tim2_isr(void);
132 CM3_WEAK tim3_isr(void);
133 CM3_WEAK tim4_isr(void);
134 CM3_WEAK i2c1_ev_isr(void);
135 CM3_WEAK i2c1_er_isr(void);
136 CM3_WEAK i2c2_ev_isr(void);
137 CM3_WEAK i2c2_er_isr(void);
138 CM3_WEAK spi1_isr(void);
139 CM3_WEAK spi2_isr(void);
140 CM3_WEAK usart1_isr(void);
141 CM3_WEAK usart2_isr(void);
142 CM3_WEAK usart3_isr(void);
143 CM3_WEAK exti15_10_isr(void);
144 CM3_WEAK rtc_alarm_isr(void);
149 CM3_WEAK tim8_cc_isr(void);
151 CM3_WEAK fsmc_isr(void);
152 CM3_WEAK sdio_isr(void);
153 CM3_WEAK tim5_isr(void);
154 CM3_WEAK spi3_isr(void);
155 CM3_WEAK uart4_isr(void);
156 CM3_WEAK uart5_isr(void);
157 CM3_WEAK tim6_dac_isr(void);
158 CM3_WEAK tim7_isr(void);
164 CM3_WEAK eth_isr(void);
165 CM3_WEAK eth_wkup_isr(void);
166 CM3_WEAK can2_tx_isr(void);
167 CM3_WEAK can2_rx0_isr(void);
168 CM3_WEAK can2_rx1_isr(void);
169 CM3_WEAK can2_sce_isr(void);
170 CM3_WEAK otg_fs_isr(void);
174 CM3_WEAK usart6_isr(void);
175 CM3_WEAK i2c3_ev_isr(void);
176 CM3_WEAK i2c3_er_isr(void);
180 CM3_WEAK otg_hs_isr(void);
181 CM3_WEAK dcmi_isr(void);
182 CM3_WEAK cryp_isr(void);
183 CM3_WEAK hash_rng_isr(void);
184 
185 
186 
187 #define NVIC_NVIC_WWDG_IRQ_VEC_CHIBIOS Vector40
188 #define NVIC_NVIC_WWDG_IRQ_VEC_OPENCM3 nvic_wwdg_isr
189 #define NVIC_PVD_IRQ_VEC_CHIBIOS Vector44
190 #define NVIC_PVD_IRQ_VEC_OPENCM3 pvd_isr
191 #define NVIC_TAMP_STAMP_IRQ_VEC_CHIBIOS Vector48
192 #define NVIC_TAMP_STAMP_IRQ_VEC_OPENCM3 tamp_stamp_isr
193 #define NVIC_RTC_WKUP_IRQ_VEC_CHIBIOS Vector4C
194 #define NVIC_RTC_WKUP_IRQ_VEC_OPENCM3 rtc_wkup_isr
195 #define NVIC_FLASH_IRQ_VEC_CHIBIOS Vector50
196 #define NVIC_FLASH_IRQ_VEC_OPENCM3 flash_isr
197 #define NVIC_RCC_IRQ_VEC_CHIBIOS Vector54
198 #define NVIC_RCC_IRQ_VEC_OPENCM3 rcc_isr
199 #define NVIC_EXTI0_IRQ_VEC_CHIBIOS Vector58
200 #define NVIC_EXTI0_IRQ_VEC_OPENCM3 exti0_isr
201 #define NVIC_EXTI1_IRQ_VEC_CHIBIOS Vector5C
202 #define NVIC_EXTI1_IRQ_VEC_OPENCM3 exti1_isr
203 #define NVIC_EXTI2_IRQ_VEC_CHIBIOS Vector60
204 #define NVIC_EXTI2_IRQ_VEC_OPENCM3 exti2_isr
205 #define NVIC_EXTI3_IRQ_VEC_CHIBIOS Vector64
206 #define NVIC_EXTI3_IRQ_VEC_OPENCM3 exti3_isr
207 #define NVIC_EXTI4_IRQ_VEC_CHIBIOS Vector68
208 #define NVIC_EXTI4_IRQ_VEC_OPENCM3 exti4_isr
209 #define NVIC_DMA1_STREAM0_IRQ_VEC_CHIBIOS Vector6C
210 #define NVIC_DMA1_STREAM0_IRQ_VEC_OPENCM3 dma1_stream0_isr
211 #define NVIC_DMA1_STREAM1_IRQ_VEC_CHIBIOS Vector70
212 #define NVIC_DMA1_STREAM1_IRQ_VEC_OPENCM3 dma1_stream1_isr
213 #define NVIC_DMA1_STREAM2_IRQ_VEC_CHIBIOS Vector74
214 #define NVIC_DMA1_STREAM2_IRQ_VEC_OPENCM3 dma1_stream2_isr
215 #define NVIC_DMA1_STREAM3_IRQ_VEC_CHIBIOS Vector78
216 #define NVIC_DMA1_STREAM3_IRQ_VEC_OPENCM3 dma1_stream3_isr
217 #define NVIC_DMA1_STREAM4_IRQ_VEC_CHIBIOS Vector7C
218 #define NVIC_DMA1_STREAM4_IRQ_VEC_OPENCM3 dma1_stream4_isr
219 #define NVIC_DMA1_STREAM5_IRQ_VEC_CHIBIOS Vector80
220 #define NVIC_DMA1_STREAM5_IRQ_VEC_OPENCM3 dma1_stream5_isr
221 #define NVIC_DMA1_STREAM6_IRQ_VEC_CHIBIOS Vector84
222 #define NVIC_DMA1_STREAM6_IRQ_VEC_OPENCM3 dma1_stream6_isr
223 #define NVIC_ADC_IRQ_VEC_CHIBIOS Vector88
224 #define NVIC_ADC_IRQ_VEC_OPENCM3 adc_isr
225 #define NVIC_CAN1_TX_IRQ_VEC_CHIBIOS Vector8C
226 #define NVIC_CAN1_TX_IRQ_VEC_OPENCM3 can1_tx_isr
227 #define NVIC_CAN1_RX0_IRQ_VEC_CHIBIOS Vector90
228 #define NVIC_CAN1_RX0_IRQ_VEC_OPENCM3 can1_rx0_isr
229 #define NVIC_CAN1_RX1_IRQ_VEC_CHIBIOS Vector94
230 #define NVIC_CAN1_RX1_IRQ_VEC_OPENCM3 can1_rx1_isr
231 #define NVIC_CAN1_SCE_IRQ_VEC_CHIBIOS Vector98
232 #define NVIC_CAN1_SCE_IRQ_VEC_OPENCM3 can1_sce_isr
233 #define NVIC_EXTI9_5_IRQ_VEC_CHIBIOS Vector9C
234 #define NVIC_EXTI9_5_IRQ_VEC_OPENCM3 exti9_5_isr
235 #define NVIC_TIM1_BRK_TIM9_IRQ_VEC_CHIBIOS VectorA0
236 #define NVIC_TIM1_BRK_TIM9_IRQ_VEC_OPENCM3 tim1_brk_tim9_isr
237 #define NVIC_TIM1_UP_TIM10_IRQ_VEC_CHIBIOS VectorA4
238 #define NVIC_TIM1_UP_TIM10_IRQ_VEC_OPENCM3 tim1_up_tim10_isr
239 #define NVIC_TIM1_TRG_COM_TIM11_IRQ_VEC_CHIBIOS VectorA8
240 #define NVIC_TIM1_TRG_COM_TIM11_IRQ_VEC_OPENCM3 tim1_trg_com_tim11_isr
241 #define NVIC_TIM1_CC_IRQ_VEC_CHIBIOS VectorAC
242 #define NVIC_TIM1_CC_IRQ_VEC_OPENCM3 tim1_cc_isr
243 #define NVIC_TIM2_IRQ_VEC_CHIBIOS VectorB0
244 #define NVIC_TIM2_IRQ_VEC_OPENCM3 tim2_isr
245 #define NVIC_TIM3_IRQ_VEC_CHIBIOS VectorB4
246 #define NVIC_TIM3_IRQ_VEC_OPENCM3 tim3_isr
247 #define NVIC_TIM4_IRQ_VEC_CHIBIOS VectorB8
248 #define NVIC_TIM4_IRQ_VEC_OPENCM3 tim4_isr
249 #define NVIC_I2C1_EV_IRQ_VEC_CHIBIOS VectorBC
250 #define NVIC_I2C1_EV_IRQ_VEC_OPENCM3 i2c1_ev_isr
251 #define NVIC_I2C1_ER_IRQ_VEC_CHIBIOS VectorC0
252 #define NVIC_I2C1_ER_IRQ_VEC_OPENCM3 i2c1_er_isr
253 #define NVIC_I2C2_EV_IRQ_VEC_CHIBIOS VectorC4
254 #define NVIC_I2C2_EV_IRQ_VEC_OPENCM3 i2c2_ev_isr
255 #define NVIC_I2C2_ER_IRQ_VEC_CHIBIOS VectorC8
256 #define NVIC_I2C2_ER_IRQ_VEC_OPENCM3 i2c2_er_isr
257 #define NVIC_SPI1_IRQ_VEC_CHIBIOS VectorCC
258 #define NVIC_SPI1_IRQ_VEC_OPENCM3 spi1_isr
259 #define NVIC_SPI2_IRQ_VEC_CHIBIOS VectorD0
260 #define NVIC_SPI2_IRQ_VEC_OPENCM3 spi2_isr
261 #define NVIC_USART1_IRQ_VEC_CHIBIOS VectorD4
262 #define NVIC_USART1_IRQ_VEC_OPENCM3 usart1_isr
263 #define NVIC_USART2_IRQ_VEC_CHIBIOS VectorD8
264 #define NVIC_USART2_IRQ_VEC_OPENCM3 usart2_isr
265 #define NVIC_USART3_IRQ_VEC_CHIBIOS VectorDC
266 #define NVIC_USART3_IRQ_VEC_OPENCM3 usart3_isr
267 #define NVIC_EXTI15_10_IRQ_VEC_CHIBIOS VectorE0
268 #define NVIC_EXTI15_10_IRQ_VEC_OPENCM3 exti15_10_isr
269 #define NVIC_RTC_ALARM_IRQ_VEC_CHIBIOS VectorE4
270 #define NVIC_RTC_ALARM_IRQ_VEC_OPENCM3 rtc_alarm_isr
271 #define NVIC_USB_FS_WKUP_IRQ_VEC_CHIBIOS VectorE8
272 #define NVIC_USB_FS_WKUP_IRQ_VEC_OPENCM3 usb_fs_wkup_isr
273 #define NVIC_TIM8_BRK_TIM12_IRQ_VEC_CHIBIOS VectorEC
274 #define NVIC_TIM8_BRK_TIM12_IRQ_VEC_OPENCM3 tim8_brk_tim12_isr
275 #define NVIC_TIM8_UP_TIM13_IRQ_VEC_CHIBIOS VectorF0
276 #define NVIC_TIM8_UP_TIM13_IRQ_VEC_OPENCM3 tim8_up_tim13_isr
277 #define NVIC_TIM8_TRG_COM_TIM14_IRQ_VEC_CHIBIOS VectorF4
278 #define NVIC_TIM8_TRG_COM_TIM14_IRQ_VEC_OPENCM3 tim8_trg_com_tim14_isr
279 #define NVIC_TIM8_CC_IRQ_VEC_CHIBIOS VectorF8
280 #define NVIC_TIM8_CC_IRQ_VEC_OPENCM3 tim8_cc_isr
281 #define NVIC_DMA1_STREAM7_IRQ_VEC_CHIBIOS VectorFC
282 #define NVIC_DMA1_STREAM7_IRQ_VEC_OPENCM3 dma1_stream7_isr
283 #define NVIC_FSMC_IRQ_VEC_CHIBIOS Vector100
284 #define NVIC_FSMC_IRQ_VEC_OPENCM3 fsmc_isr
285 #define NVIC_SDIO_IRQ_VEC_CHIBIOS Vector104
286 #define NVIC_SDIO_IRQ_VEC_OPENCM3 sdio_isr
287 #define NVIC_TIM5_IRQ_VEC_CHIBIOS Vector108
288 #define NVIC_TIM5_IRQ_VEC_OPENCM3 tim5_isr
289 #define NVIC_SPI3_IRQ_VEC_CHIBIOS Vector10C
290 #define NVIC_SPI3_IRQ_VEC_OPENCM3 spi3_isr
291 #define NVIC_UART4_IRQ_VEC_CHIBIOS Vector110
292 #define NVIC_UART4_IRQ_VEC_OPENCM3 uart4_isr
293 #define NVIC_UART5_IRQ_VEC_CHIBIOS Vector114
294 #define NVIC_UART5_IRQ_VEC_OPENCM3 uart5_isr
295 #define NVIC_TIM6_DAC_IRQ_VEC_CHIBIOS Vector118
296 #define NVIC_TIM6_DAC_IRQ_VEC_OPENCM3 tim6_dac_isr
297 #define NVIC_TIM7_IRQ_VEC_CHIBIOS Vector11C
298 #define NVIC_TIM7_IRQ_VEC_OPENCM3 tim7_isr
299 #define NVIC_DMA2_STREAM0_IRQ_VEC_CHIBIOS Vector120
300 #define NVIC_DMA2_STREAM0_IRQ_VEC_OPENCM3 dma2_stream0_isr
301 #define NVIC_DMA2_STREAM1_IRQ_VEC_CHIBIOS Vector124
302 #define NVIC_DMA2_STREAM1_IRQ_VEC_OPENCM3 dma2_stream1_isr
303 #define NVIC_DMA2_STREAM2_IRQ_VEC_CHIBIOS Vector128
304 #define NVIC_DMA2_STREAM2_IRQ_VEC_OPENCM3 dma2_stream2_isr
305 #define NVIC_DMA2_STREAM3_IRQ_VEC_CHIBIOS Vector12C
306 #define NVIC_DMA2_STREAM3_IRQ_VEC_OPENCM3 dma2_stream3_isr
307 #define NVIC_DMA2_STREAM4_IRQ_VEC_CHIBIOS Vector130
308 #define NVIC_DMA2_STREAM4_IRQ_VEC_OPENCM3 dma2_stream4_isr
309 #define NVIC_ETH_IRQ_VEC_CHIBIOS Vector134
310 #define NVIC_ETH_IRQ_VEC_OPENCM3 eth_isr
311 #define NVIC_ETH_WKUP_IRQ_VEC_CHIBIOS Vector138
312 #define NVIC_ETH_WKUP_IRQ_VEC_OPENCM3 eth_wkup_isr
313 #define NVIC_CAN2_TX_IRQ_VEC_CHIBIOS Vector13C
314 #define NVIC_CAN2_TX_IRQ_VEC_OPENCM3 can2_tx_isr
315 #define NVIC_CAN2_RX0_IRQ_VEC_CHIBIOS Vector140
316 #define NVIC_CAN2_RX0_IRQ_VEC_OPENCM3 can2_rx0_isr
317 #define NVIC_CAN2_RX1_IRQ_VEC_CHIBIOS Vector144
318 #define NVIC_CAN2_RX1_IRQ_VEC_OPENCM3 can2_rx1_isr
319 #define NVIC_CAN2_SCE_IRQ_VEC_CHIBIOS Vector148
320 #define NVIC_CAN2_SCE_IRQ_VEC_OPENCM3 can2_sce_isr
321 #define NVIC_OTG_FS_IRQ_VEC_CHIBIOS Vector14C
322 #define NVIC_OTG_FS_IRQ_VEC_OPENCM3 otg_fs_isr
323 #define NVIC_DMA2_STREAM5_IRQ_VEC_CHIBIOS Vector150
324 #define NVIC_DMA2_STREAM5_IRQ_VEC_OPENCM3 dma2_stream5_isr
325 #define NVIC_DMA2_STREAM6_IRQ_VEC_CHIBIOS Vector154
326 #define NVIC_DMA2_STREAM6_IRQ_VEC_OPENCM3 dma2_stream6_isr
327 #define NVIC_DMA2_STREAM7_IRQ_VEC_CHIBIOS Vector158
328 #define NVIC_DMA2_STREAM7_IRQ_VEC_OPENCM3 dma2_stream7_isr
329 #define NVIC_USART6_IRQ_VEC_CHIBIOS Vector15C
330 #define NVIC_USART6_IRQ_VEC_OPENCM3 usart6_isr
331 #define NVIC_I2C3_EV_IRQ_VEC_CHIBIOS Vector160
332 #define NVIC_I2C3_EV_IRQ_VEC_OPENCM3 i2c3_ev_isr
333 #define NVIC_I2C3_ER_IRQ_VEC_CHIBIOS Vector164
334 #define NVIC_I2C3_ER_IRQ_VEC_OPENCM3 i2c3_er_isr
335 #define NVIC_OTG_HS_EP1_OUT_IRQ_VEC_CHIBIOS Vector168
336 #define NVIC_OTG_HS_EP1_OUT_IRQ_VEC_OPENCM3 otg_hs_ep1_out_isr
337 #define NVIC_OTG_HS_EP1_IN_IRQ_VEC_CHIBIOS Vector16C
338 #define NVIC_OTG_HS_EP1_IN_IRQ_VEC_OPENCM3 otg_hs_ep1_in_isr
339 #define NVIC_OTG_HS_WKUP_IRQ_VEC_CHIBIOS Vector170
340 #define NVIC_OTG_HS_WKUP_IRQ_VEC_OPENCM3 otg_hs_wkup_isr
341 #define NVIC_OTG_HS_IRQ_VEC_CHIBIOS Vector174
342 #define NVIC_OTG_HS_IRQ_VEC_OPENCM3 otg_hs_isr
343 #define NVIC_DCMI_IRQ_VEC_CHIBIOS Vector178
344 #define NVIC_DCMI_IRQ_VEC_OPENCM3 dcmi_isr
345 #define NVIC_CRYP_IRQ_VEC_CHIBIOS Vector17C
346 #define NVIC_CRYP_IRQ_VEC_OPENCM3 cryp_isr
347 #define NVIC_HASH_RNG_IRQ_VEC_CHIBIOS Vector180
348 #define NVIC_HASH_RNG_IRQ_VEC_OPENCM3 hash_rng_isr
CM3_WEAK dma2_stream1_isr(void)
CM3_WEAK tim8_cc_isr(void)
CM3_WEAK cryp_isr(void)
CM3_WEAK tim8_brk_tim12_isr(void)
CM3_WEAK can1_rx0_isr(void)
CM3_WEAK tim2_isr(void)
CM3_WEAK can1_tx_isr(void)
CM3_WEAK tim6_dac_isr(void)
CM3_WEAK uart4_isr(void)
CM3_WEAK dcmi_isr(void)
CM3_WEAK tim3_isr(void)
CM3_WEAK rcc_isr(void)
CM3_WEAK nvic_wwdg_isr(void)
CM3_WEAK tim1_cc_isr(void)
CM3_WEAK i2c2_ev_isr(void)
CM3_WEAK rtc_alarm_isr(void)
CM3_WEAK spi2_isr(void)
CM3_WEAK exti1_isr(void)
CM3_WEAK usart6_isr(void)
CM3_WEAK dma1_stream0_isr(void)
CM3_WEAK tim1_trg_com_tim11_isr(void)
CM3_WEAK i2c3_ev_isr(void)
CM3_WEAK usb_fs_wkup_isr(void)
CM3_WEAK pvd_isr(void)
CM3_WEAK hash_rng_isr(void)
CM3_WEAK can2_sce_isr(void)
CM3_WEAK otg_hs_isr(void)
CM3_WEAK dma2_stream6_isr(void)
CM3_WEAK tim1_up_tim10_isr(void)
CM3_WEAK uart5_isr(void)
CM3_WEAK i2c3_er_isr(void)
CM3_WEAK adc_isr(void)
CM3_WEAK exti15_10_isr(void)
CM3_WEAK flash_isr(void)
CM3_WEAK tim7_isr(void)
CM3_WEAK tamp_stamp_isr(void)
CM3_WEAK i2c1_er_isr(void)
CM3_WEAK tim8_trg_com_tim14_isr(void)
CM3_WEAK i2c2_er_isr(void)
CM3_WEAK eth_wkup_isr(void)
CM3_WEAK dma1_stream1_isr(void)
CM3_WEAK dma1_stream3_isr(void)
CM3_WEAK dma2_stream3_isr(void)
CM3_WEAK sdio_isr(void)
CM3_WEAK usart2_isr(void)
CM3_WEAK spi3_isr(void)
CM3_WEAK exti9_5_isr(void)
Definition: hmc5843_arch.c:57
CM3_WEAK dma1_stream2_isr(void)
CM3_WEAK can1_sce_isr(void)
CM3_WEAK dma1_stream7_isr(void)
CM3_WEAK rtc_wkup_isr(void)
CM3_WEAK can1_rx1_isr(void)
CM3_WEAK dma2_stream7_isr(void)
CM3_WEAK eth_isr(void)
CM3_WEAK exti4_isr(void)
CM3_WEAK otg_hs_wkup_isr(void)
CM3_WEAK otg_hs_ep1_in_isr(void)
CM3_WEAK otg_fs_isr(void)
CM3_WEAK tim4_isr(void)
CM3_WEAK spi1_isr(void)
CM3_WEAK usart3_isr(void)
CM3_WEAK can2_tx_isr(void)
CM3_WEAK dma2_stream0_isr(void)
CM3_WEAK exti2_isr(void)
Definition: max1168_arch.c:50
CM3_WEAK can2_rx1_isr(void)
CM3_WEAK dma2_stream4_isr(void)
CM3_WEAK dma2_stream2_isr(void)
CM3_WEAK tim8_up_tim13_isr(void)
CM3_WEAK tim1_brk_tim9_isr(void)
CM3_WEAK dma1_stream4_isr(void)
CM3_WEAK exti0_isr(void)
CM3_WEAK exti3_isr(void)
CM3_WEAK otg_hs_ep1_out_isr(void)
CM3_WEAK can2_rx0_isr(void)
#define CM3_WEAK
CM3_WEAK usart1_isr(void)
CM3_WEAK tim5_isr(void)
CM3_WEAK dma2_stream5_isr(void)
CM3_WEAK dma1_stream6_isr(void)
CM3_WEAK dma1_stream5_isr(void)
CM3_WEAK fsmc_isr(void)
CM3_WEAK i2c1_ev_isr(void)