Paparazzi UAS  v5.2.2_stable-0-gd6b9f29
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imu_crista_arch.c
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1 /*
2  * Copyright (C) 2008-2009 Antoine Drouin <poinix@gmail.com>
3  *
4  * This file is part of paparazzi.
5  *
6  * paparazzi is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2, or (at your option)
9  * any later version.
10  *
11  * paparazzi is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
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17  * along with paparazzi; see the file COPYING. If not, write to
18  * the Free Software Foundation, 59 Temple Place - Suite 330,
19  * Boston, MA 02111-1307, USA.
20  */
21 
22 #include "subsystems/imu.h"
23 
24 #include <stm32/gpio.h>
25 #include <stm32/rcc.h>
26 #include <stm32/spi.h>
27 #include <stm32/misc.h>
28 #include <stm32/dma.h>
29 
30 static volatile uint8_t channel;
31 static uint8_t buf_in[4];
32 static uint8_t buf_out[4];
33 
34 #define POWER_MODE (1 << 1 | 1)
35 #define SGL_DIF 1 // Single ended
36 
37 #define ADS8344Unselect() GPIOB->BSRR = GPIO_Pin_12
38 #define ADS8344Select() GPIOB->BRR = GPIO_Pin_12
39 
40 extern void dma1_c4_irq_handler(void);
41 static void ADS8344_read_channel( void );
42 
44 
45  channel = 0;
46  /* Enable SPI2 Periph clock -------------------------------------------------*/
47  RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
48  /* Enable SPI_2 DMA clock ---------------------------------------------------*/
49  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
50  /* Enable PORTB GPIO clock --------------------------------------------------*/
51  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO , ENABLE);
52  /* Configure GPIOs: SCK, MISO and MOSI -------------------------------------*/
53  GPIO_InitTypeDef GPIO_InitStructure;
54  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
55  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
56  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
57  GPIO_Init(GPIOB, &GPIO_InitStructure);
58  /* set slave select as output and assert it ( on PB12) */
59  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
60  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
61  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
62  GPIO_Init(GPIOB, &GPIO_InitStructure);
64  /* configure SPI after enabling it*/
65  SPI_Cmd(SPI2, ENABLE);
66  SPI_InitTypeDef SPI_InitStructure;
67  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
68  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
69  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
70  SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
71  SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
72  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
73  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_16;
74  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
75  SPI_InitStructure.SPI_CRCPolynomial = 7;
76  SPI_Init(SPI2, &SPI_InitStructure);
77 
78  /* Enable DMA1 channel4 IRQ Channel */
79  NVIC_InitTypeDef NVIC_init_struct = {
80  .NVIC_IRQChannel = DMA1_Channel4_IRQn,
81  .NVIC_IRQChannelPreemptionPriority = 0,
82  .NVIC_IRQChannelSubPriority = 0,
83  .NVIC_IRQChannelCmd = ENABLE
84  };
85  NVIC_Init(&NVIC_init_struct);
86 
87 }
88 
89 
90 void ADS8344_start( void ) {
91 
92  ADS8344Select();
93  channel = 0;
95 
96 }
97 
98 static void ADS8344_read_channel( void ) {
99 
100  // control byte
101  buf_out[0] = 1 << 7 | channel << 4 | SGL_DIF << 2 | POWER_MODE;
102 
103  /* trigger 4 bytes read */
104  /* SPI2_Rx_DMA_Channel configuration ------------------------------------*/
105  DMA_DeInit(DMA1_Channel4);
106  DMA_InitTypeDef DMA_initStructure_4 = {
107  .DMA_PeripheralBaseAddr = (uint32_t)(SPI2_BASE+0x0C),
108  .DMA_MemoryBaseAddr = (uint32_t)buf_in,
109  .DMA_DIR = DMA_DIR_PeripheralSRC,
110  .DMA_BufferSize = 4,
111  .DMA_PeripheralInc = DMA_PeripheralInc_Disable,
112  .DMA_MemoryInc = DMA_MemoryInc_Enable,
113  .DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte,
114  .DMA_MemoryDataSize = DMA_MemoryDataSize_Byte,
115  .DMA_Mode = DMA_Mode_Normal,
116  .DMA_Priority = DMA_Priority_VeryHigh,
117  .DMA_M2M = DMA_M2M_Disable
118  };
119  DMA_Init(DMA1_Channel4, &DMA_initStructure_4);
120 
121  /* SPI2_Tx_DMA_Channel configuration ------------------------------------*/
122  DMA_DeInit(DMA1_Channel5);
123  DMA_InitTypeDef DMA_initStructure_5 = {
124  .DMA_PeripheralBaseAddr = (uint32_t)(SPI2_BASE+0x0C),
125  .DMA_MemoryBaseAddr = (uint32_t)buf_out,
126  .DMA_DIR = DMA_DIR_PeripheralDST,
127  .DMA_BufferSize = 4,
128  .DMA_PeripheralInc = DMA_PeripheralInc_Disable,
129  .DMA_MemoryInc = DMA_MemoryInc_Enable,
130  .DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte,
131  .DMA_MemoryDataSize = DMA_MemoryDataSize_Byte,
132  .DMA_Mode = DMA_Mode_Normal,
133  .DMA_Priority = DMA_Priority_Medium,
134  .DMA_M2M = DMA_M2M_Disable
135  };
136  DMA_Init(DMA1_Channel5, &DMA_initStructure_5);
137 
138  /* Enable SPI_2 Rx request */
139  SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Rx, ENABLE);
140  /* Enable DMA1 Channel4 */
141  DMA_Cmd(DMA1_Channel4, ENABLE);
142 
143  /* Enable SPI_2 Tx request */
144  SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, ENABLE);
145  /* Enable DMA1 Channel5 */
146  DMA_Cmd(DMA1_Channel5, ENABLE);
147 
148  /* Enable DMA1 Channel4 Transfer Complete interrupt */
149  DMA_ITConfig(DMA1_Channel4, DMA_IT_TC, ENABLE);
150 
151 }
152 
153 
155 
156  ADS8344_values[channel] = (buf_in[1] << 8 | buf_in[2]) << 1 | buf_in[3] >> 7;
157  channel++;
158  if (channel > 6) {
160  ADS8344Unselect();
161  DMA_ITConfig(DMA1_Channel4, DMA_IT_TC, DISABLE);
162  /* Disable SPI_2 Rx and TX request */
163  SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Rx, DISABLE);
164  SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, DISABLE);
165  /* Disable DMA1 Channel4 and 5 */
166  DMA_Cmd(DMA1_Channel4, DISABLE);
167  DMA_Cmd(DMA1_Channel5, DISABLE);
168  }
169  else {
171  }
172 }
#define SGL_DIF
#define POWER_MODE
void dma1_c4_irq_handler(void)
uint16_t ADS8344_values[NB_CHANNELS]
Definition: ADS8344.c:39
#define GPIOB
Definition: gpio_arch.h:35
bool_t ADS8344_available
Definition: ADS8344.c:38
static uint8_t buf_in[4]
#define ADS8344Unselect()
unsigned long uint32_t
Definition: types.h:18
static volatile uint8_t channel
Inertial Measurement Unit interface.
#define TRUE
Definition: imu_chimu.h:144
void ADS8344_start(void)
unsigned char uint8_t
Definition: types.h:14
void imu_crista_arch_init(void)
#define ADS8344Select()
static void ADS8344_read_channel(void)
static uint8_t buf_out[4]