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uart_arch.c
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1 /*
2  * Copyright (C) 2009 Antoine Drouin <poinix@gmail.com>
3  * Copyright (C) 2013 Felix Ruess <felix.ruess@gmail.com>
4  *
5  * This file is part of paparazzi.
6  *
7  * paparazzi is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2, or (at your option)
10  * any later version.
11  *
12  * paparazzi is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with paparazzi; see the file COPYING. If not, write to
19  * the Free Software Foundation, 59 Temple Place - Suite 330,
20  * Boston, MA 02111-1307, USA.
21  */
22 
30 #include "mcu_periph/uart.h"
31 #include "mcu_periph/gpio.h"
32 
33 #include <libopencm3/stm32/gpio.h>
34 #include <libopencm3/stm32/rcc.h>
35 #include <libopencm3/stm32/usart.h>
36 #include <libopencm3/cm3/nvic.h>
37 
38 #include "std.h"
39 
40 #include BOARD_CONFIG
41 
43 
44  /* Configure USART baudrate */
45  usart_set_baudrate((uint32_t)p->reg_addr, baud);
46 
47  /* Disable Idle Line interrupt */
48  USART_CR1((uint32_t)p->reg_addr) &= ~USART_CR1_IDLEIE;
49 
50  /* Disable LIN break detection interrupt */
51  USART_CR2((uint32_t)p->reg_addr) &= ~USART_CR2_LBDIE;
52 
53  /* Enable USART1 Receive interrupts */
54  USART_CR1((uint32_t)p->reg_addr) |= USART_CR1_RXNEIE;
55 
56  /* Enable the USART */
57  usart_enable((uint32_t)p->reg_addr);
58 
59 }
60 
62  /* Configure USART parity and data bits */
63  if (parity == UPARITY_EVEN) {
64  usart_set_parity((uint32_t)p->reg_addr, USART_PARITY_EVEN);
65  if (bits == UBITS_7)
66  usart_set_databits((uint32_t)p->reg_addr, 8);
67  else // 8 data bits by default
68  usart_set_databits((uint32_t)p->reg_addr, 9);
69  }
70  else if (parity == UPARITY_ODD) {
71  usart_set_parity((uint32_t)p->reg_addr, USART_PARITY_ODD);
72  if (bits == UBITS_7)
73  usart_set_databits((uint32_t)p->reg_addr, 8);
74  else // 8 data bits by default
75  usart_set_databits((uint32_t)p->reg_addr, 9);
76  }
77  else { // 8 data bist, NO_PARITY by default
78  usart_set_parity((uint32_t)p->reg_addr, USART_PARITY_NONE);
79  usart_set_databits((uint32_t)p->reg_addr, 8); // is 7bits without parity possible ?
80  }
81  /* Configure USART stop bits */
82  if (stop == USTOP_2)
83  usart_set_stopbits((uint32_t)p->reg_addr, USART_STOPBITS_2);
84  else // 1 stop bit by default
85  usart_set_stopbits((uint32_t)p->reg_addr, USART_STOPBITS_1);
86 }
87 
88 void uart_periph_set_mode(struct uart_periph* p, bool_t tx_enabled, bool_t rx_enabled, bool_t hw_flow_control) {
89  uint32_t mode = 0;
90  if (tx_enabled)
91  mode |= USART_MODE_TX;
92  if (rx_enabled)
93  mode |= USART_MODE_RX;
94 
95  /* set mode to Tx, Rx or TxRx */
96  usart_set_mode((uint32_t)p->reg_addr, mode);
97 
98  if (hw_flow_control) {
99  usart_set_flow_control((uint32_t)p->reg_addr, USART_FLOWCONTROL_RTS_CTS);
100  }
101  else {
102  usart_set_flow_control((uint32_t)p->reg_addr, USART_FLOWCONTROL_NONE);
103  }
104 }
105 
106 void uart_transmit(struct uart_periph* p, uint8_t data ) {
107 
108  uint16_t temp = (p->tx_insert_idx + 1) % UART_TX_BUFFER_SIZE;
109 
110  if (temp == p->tx_extract_idx)
111  return; // no room
112 
113  USART_CR1((uint32_t)p->reg_addr) &= ~USART_CR1_TXEIE; // Disable TX interrupt
114 
115  // check if in process of sending data
116  if (p->tx_running) { // yes, add to queue
117  p->tx_buf[p->tx_insert_idx] = data;
118  p->tx_insert_idx = temp;
119  }
120  else { // no, set running flag and write to output register
121  p->tx_running = TRUE;
122  usart_send((uint32_t)p->reg_addr, data);
123  }
124 
125  USART_CR1((uint32_t)p->reg_addr) |= USART_CR1_TXEIE; // Enable TX interrupt
126 
127 }
128 
129 static inline void usart_isr(struct uart_periph* p) {
130 
131  if (((USART_CR1((uint32_t)p->reg_addr) & USART_CR1_TXEIE) != 0) &&
132  ((USART_SR((uint32_t)p->reg_addr) & USART_SR_TXE) != 0)) {
133  // check if more data to send
134  if (p->tx_insert_idx != p->tx_extract_idx) {
135  usart_send((uint32_t)p->reg_addr,p->tx_buf[p->tx_extract_idx]);
136  p->tx_extract_idx++;
138  }
139  else {
140  p->tx_running = FALSE; // clear running flag
141  USART_CR1((uint32_t)p->reg_addr) &= ~USART_CR1_TXEIE; // Disable TX interrupt
142  }
143  }
144 
145  if (((USART_CR1((uint32_t)p->reg_addr) & USART_CR1_RXNEIE) != 0) &&
146  ((USART_SR((uint32_t)p->reg_addr) & USART_SR_RXNE) != 0) &&
147  ((USART_SR((uint32_t)p->reg_addr) & USART_SR_ORE) == 0) &&
148  ((USART_SR((uint32_t)p->reg_addr) & USART_SR_NE) == 0) &&
149  ((USART_SR((uint32_t)p->reg_addr) & USART_SR_FE) == 0)) {
150  uint16_t temp = (p->rx_insert_idx + 1) % UART_RX_BUFFER_SIZE;;
151  p->rx_buf[p->rx_insert_idx] = usart_recv((uint32_t)p->reg_addr);
152  // check for more room in queue
153  if (temp != p->rx_extract_idx)
154  p->rx_insert_idx = temp; // update insert index
155  }
156  else {
157  /* ORE, NE or FE error - read USART_DR reg and log the error */
158  if (((USART_CR1((uint32_t)p->reg_addr) & USART_CR1_RXNEIE) != 0) &&
159  ((USART_SR((uint32_t)p->reg_addr) & USART_SR_ORE) != 0)) {
160  usart_recv((uint32_t)p->reg_addr);
161  p->ore++;
162  }
163  if (((USART_CR1((uint32_t)p->reg_addr) & USART_CR1_RXNEIE) != 0) &&
164  ((USART_SR((uint32_t)p->reg_addr) & USART_SR_NE) != 0)) {
165  usart_recv((uint32_t)p->reg_addr);
166  p->ne_err++;
167  }
168  if (((USART_CR1((uint32_t)p->reg_addr) & USART_CR1_RXNEIE) != 0) &&
169  ((USART_SR((uint32_t)p->reg_addr) & USART_SR_FE) != 0)) {
170  usart_recv((uint32_t)p->reg_addr);
171  p->fe_err++;
172  }
173  }
174 }
175 
176 static inline void usart_enable_irq(uint8_t IRQn) {
177  /* Note:
178  * In libstm32 times the priority of this interrupt was set to
179  * preemption priority 2 and sub priority 1
180  */
181  /* Enable USART interrupts */
182  nvic_enable_irq(IRQn);
183 }
184 
185 
186 #if USE_UART1
187 
188 /* by default enable UART Tx and Rx */
189 #ifndef USE_UART1_TX
190 #define USE_UART1_TX TRUE
191 #endif
192 #ifndef USE_UART1_RX
193 #define USE_UART1_RX TRUE
194 #endif
195 
196 #ifndef UART1_HW_FLOW_CONTROL
197 #define UART1_HW_FLOW_CONTROL FALSE
198 #endif
199 
200 #ifndef UART1_BITS
201 #define UART1_BITS UBITS_8
202 #endif
203 
204 #ifndef UART1_STOP
205 #define UART1_STOP USTOP_1
206 #endif
207 
208 #ifndef UART1_PARITY
209 #define UART1_PARITY UPARITY_NO
210 #endif
211 
212 void uart1_init( void ) {
213 
214  uart_periph_init(&uart1);
215  uart1.reg_addr = (void *)USART1;
216 
217  /* init RCC and GPIOs */
218  rcc_periph_clock_enable(RCC_USART1);
219 
220 #if USE_UART1_TX
222 #endif
223 #if USE_UART1_RX
225 #endif
226 
227  /* Enable USART interrupts in the interrupt controller */
229 
230 #if UART1_HW_FLOW_CONTROL
231 #warning "USING UART1 FLOW CONTROL. Make sure to pull down CTS if you are not connecting any flow-control-capable hardware."
232  /* setup CTS and RTS gpios */
233  gpio_setup_pin_af(UART1_GPIO_PORT_CTS, UART1_GPIO_CTS, UART1_GPIO_AF, FALSE);
234  gpio_setup_pin_af(UART1_GPIO_PORT_RTS, UART1_GPIO_RTS, UART1_GPIO_AF, TRUE);
235 #endif
236 
237  /* Configure USART1, enable hardware flow control*/
238  uart_periph_set_mode(&uart1, USE_UART1_TX, USE_UART1_RX, UART1_HW_FLOW_CONTROL);
239 
240  /* Set USART1 parameters and enable interrupt */
241  uart_periph_set_bits_stop_parity(&uart1, UART1_BITS, UART1_STOP, UART1_PARITY);
242  uart_periph_set_baudrate(&uart1, UART1_BAUD);
243 }
244 
245 void usart1_isr(void) { usart_isr(&uart1); }
246 
247 #endif /* USE_UART1 */
248 
249 
250 #if USE_UART2
251 
252 /* by default enable UART Tx and Rx */
253 #ifndef USE_UART2_TX
254 #define USE_UART2_TX TRUE
255 #endif
256 #ifndef USE_UART2_RX
257 #define USE_UART2_RX TRUE
258 #endif
259 
260 #ifndef UART2_HW_FLOW_CONTROL
261 #define UART2_HW_FLOW_CONTROL FALSE
262 #endif
263 
264 #ifndef UART2_BITS
265 #define UART2_BITS UBITS_8
266 #endif
267 
268 #ifndef UART2_STOP
269 #define UART2_STOP USTOP_1
270 #endif
271 
272 #ifndef UART2_PARITY
273 #define UART2_PARITY UPARITY_NO
274 #endif
275 
276 void uart2_init( void ) {
277 
278  uart_periph_init(&uart2);
279  uart2.reg_addr = (void *)USART2;
280 
281  /* init RCC and GPIOs */
282  rcc_periph_clock_enable(RCC_USART2);
283 
284 #if USE_UART2_TX
286 #endif
287 #if USE_UART2_RX
289 #endif
290 
291  /* Enable USART interrupts in the interrupt controller */
293 
294 #if UART2_HW_FLOW_CONTROL && defined(STM32F4)
295 #warning "USING UART2 FLOW CONTROL. Make sure to pull down CTS if you are not connecting any flow-control-capable hardware."
296  /* setup CTS and RTS pins */
297  gpio_setup_pin_af(UART2_GPIO_PORT_CTS, UART2_GPIO_CTS, UART2_GPIO_AF, FALSE);
298  gpio_setup_pin_af(UART2_GPIO_PORT_RTS, UART2_GPIO_RTS, UART2_GPIO_AF, TRUE);
299 #endif
300 
301  /* Configure USART Tx,Rx, and hardware flow control*/
302  uart_periph_set_mode(&uart2, USE_UART2_TX, USE_UART2_RX, UART2_HW_FLOW_CONTROL);
303 
304  /* Configure USART */
305  uart_periph_set_bits_stop_parity(&uart2, UART2_BITS, UART2_STOP, UART2_PARITY);
306  uart_periph_set_baudrate(&uart2, UART2_BAUD);
307 }
308 
309 void usart2_isr(void) { usart_isr(&uart2); }
310 
311 #endif /* USE_UART2 */
312 
313 
314 #if USE_UART3
315 
316 /* by default enable UART Tx and Rx */
317 #ifndef USE_UART3_TX
318 #define USE_UART3_TX TRUE
319 #endif
320 #ifndef USE_UART3_RX
321 #define USE_UART3_RX TRUE
322 #endif
323 
324 #ifndef UART3_HW_FLOW_CONTROL
325 #define UART3_HW_FLOW_CONTROL FALSE
326 #endif
327 
328 #ifndef UART3_BITS
329 #define UART3_BITS UBITS_8
330 #endif
331 
332 #ifndef UART3_STOP
333 #define UART3_STOP USTOP_1
334 #endif
335 
336 #ifndef UART3_PARITY
337 #define UART3_PARITY UPARITY_NO
338 #endif
339 
340 void uart3_init( void ) {
341 
342  uart_periph_init(&uart3);
343  uart3.reg_addr = (void *)USART3;
344 
345  /* init RCC */
346  rcc_periph_clock_enable(RCC_USART3);
347 
348 #if USE_UART3_TX
350 #endif
351 #if USE_UART3_RX
353 #endif
354 
355  /* Enable USART interrupts in the interrupt controller */
357 
358 #if UART3_HW_FLOW_CONTROL && defined(STM32F4)
359 #warning "USING UART3 FLOW CONTROL. Make sure to pull down CTS if you are not connecting any flow-control-capable hardware."
360  /* setup CTS and RTS pins */
361  gpio_setup_pin_af(UART3_GPIO_PORT_CTS, UART3_GPIO_CTS, UART3_GPIO_AF, FALSE);
362  gpio_setup_pin_af(UART3_GPIO_PORT_RTS, UART3_GPIO_RTS, UART3_GPIO_AF, TRUE);
363 #endif
364 
365  /* Configure USART Tx,Rx, and hardware flow control*/
366  uart_periph_set_mode(&uart3, USE_UART3_TX, USE_UART3_RX, UART3_HW_FLOW_CONTROL);
367 
368  /* Configure USART */
369  uart_periph_set_bits_stop_parity(&uart3, UART3_BITS, UART3_STOP, UART3_PARITY);
370  uart_periph_set_baudrate(&uart3, UART3_BAUD);
371 }
372 
373 void usart3_isr(void) { usart_isr(&uart3); }
374 
375 #endif /* USE_UART3 */
376 
377 
378 #if USE_UART4 && defined STM32F4
379 
380 /* by default enable UART Tx and Rx */
381 #ifndef USE_UART4_TX
382 #define USE_UART4_TX TRUE
383 #endif
384 #ifndef USE_UART4_RX
385 #define USE_UART4_RX TRUE
386 #endif
387 
388 #ifndef UART4_BITS
389 #define UART4_BITS UBITS_8
390 #endif
391 
392 #ifndef UART4_STOP
393 #define UART4_STOP USTOP_1
394 #endif
395 
396 #ifndef UART4_PARITY
397 #define UART4_PARITY UPARITY_NO
398 #endif
399 
400 void uart4_init( void ) {
401 
402  uart_periph_init(&uart4);
403  uart4.reg_addr = (void *)UART4;
404 
405  /* init RCC and GPIOs */
406  rcc_periph_clock_enable(RCC_UART4);
407 
408 #if USE_UART4_TX
410 #endif
411 #if USE_UART4_RX
413 #endif
414 
415  /* Enable USART interrupts in the interrupt controller */
417 
418  /* Configure USART */
419  uart_periph_set_mode(&uart4, USE_UART4_TX, USE_UART4_RX, FALSE);
420  uart_periph_set_bits_stop_parity(&uart4, UART4_BITS, UART4_STOP, UART4_PARITY);
421  uart_periph_set_baudrate(&uart4, UART4_BAUD);
422 }
423 
424 void uart4_isr(void) { usart_isr(&uart4); }
425 
426 #endif /* USE_UART4 */
427 
428 
429 #if USE_UART5
430 
431 /* by default enable UART Tx and Rx */
432 #ifndef USE_UART5_TX
433 #define USE_UART5_TX TRUE
434 #endif
435 #ifndef USE_UART5_RX
436 #define USE_UART5_RX TRUE
437 #endif
438 
439 #ifndef UART5_BITS
440 #define UART5_BITS UBITS_8
441 #endif
442 
443 #ifndef UART5_STOP
444 #define UART5_STOP USTOP_1
445 #endif
446 
447 #ifndef UART5_PARITY
448 #define UART5_PARITY UPARITY_NO
449 #endif
450 
451 void uart5_init( void ) {
452 
453  uart_periph_init(&uart5);
454  uart5.reg_addr = (void *)UART5;
455 
456  /* init RCC and GPIOs */
457  rcc_periph_clock_enable(RCC_UART5);
458 
459 #if USE_UART5_TX
461 #endif
462 #if USE_UART5_RX
464 #endif
465 
466  /* Enable USART interrupts in the interrupt controller */
468 
469  /* Configure USART */
470  uart_periph_set_mode(&uart5, USE_UART5_TX, USE_UART5_RX, FALSE);
471  uart_periph_set_bits_stop_parity(&uart5, UART5_BITS, UART5_STOP, UART5_PARITY);
472  uart_periph_set_baudrate(&uart5, UART5_BAUD);
473 }
474 
475 void uart5_isr(void) { usart_isr(&uart5); }
476 
477 #endif /* USE_UART5 */
478 
479 
480 #if USE_UART6 && defined STM32F4
481 
482 /* by default enable UART Tx and Rx */
483 #ifndef USE_UART6_TX
484 #define USE_UART6_TX TRUE
485 #endif
486 #ifndef USE_UART6_RX
487 #define USE_UART6_RX TRUE
488 #endif
489 
490 #ifndef UART6_HW_FLOW_CONTROL
491 #define UART6_HW_FLOW_CONTROL FALSE
492 #endif
493 
494 #ifndef UART6_BITS
495 #define UART6_BITS UBITS_8
496 #endif
497 
498 #ifndef UART6_STOP
499 #define UART6_STOP USTOP_1
500 #endif
501 
502 #ifndef UART6_PARITY
503 #define UART6_PARITY UPARITY_NO
504 #endif
505 
506 void uart6_init( void ) {
507 
508  uart_periph_init(&uart6);
509  uart6.reg_addr = (void *)USART6;
510 
511  /* enable uart clock */
512  rcc_periph_clock_enable(RCC_USART6);
513 
514  /* init RCC and GPIOs */
515 #if USE_UART6_TX
517 #endif
518 #if USE_UART6_RX
520 #endif
521 
522  /* Enable USART interrupts in the interrupt controller */
524 
525 #if UART6_HW_FLOW_CONTROL
526 #warning "USING UART6 FLOW CONTROL. Make sure to pull down CTS if you are not connecting any flow-control-capable hardware."
527  /* setup CTS and RTS pins */
528  gpio_setup_pin_af(UART6_GPIO_PORT_CTS, UART6_GPIO_CTS, UART6_GPIO_AF, FALSE);
529  gpio_setup_pin_af(UART6_GPIO_PORT_RTS, UART6_GPIO_RTS, UART6_GPIO_AF, TRUE);
530 #endif
531 
532  /* Configure USART Tx,Rx and hardware flow control*/
533  uart_periph_set_mode(&uart6, USE_UART6_TX, USE_UART6_RX, UART6_HW_FLOW_CONTROL);
534  uart_periph_set_bits_stop_parity(&uart6, UART6_BITS, UART6_STOP, UART6_PARITY);
535  uart_periph_set_baudrate(&uart6, UART6_BAUD);
536 }
537 
538 void usart6_isr(void) { usart_isr(&uart6); }
539 
540 #endif /* USE_UART6 */
unsigned short uint16_t
Definition: types.h:16
arch independent UART (Universal Asynchronous Receiver/Transmitter) API
CM3_WEAK uart4_isr(void)
volatile uint16_t ore
overrun error counter
Definition: uart.h:69
volatile uint16_t fe_err
framing error counter
Definition: uart.h:71
Some architecture independent helper functions for GPIOs.
uint8_t tx_running
Definition: uart.h:64
volatile uint16_t ne_err
noise error counter
Definition: uart.h:70
#define UART2_GPIO_PORT_TX
Definition: lisa_l_1.0.h:61
#define UART3_GPIO_AF
Definition: krooz_sd.h:87
#define NVIC_USART3_IRQ
void * reg_addr
UART Register.
Definition: uart.h:66
uint16_t tx_extract_idx
Definition: uart.h:63
#define UART4_GPIO_AF
Definition: apogee_0.99.h:49
CM3_WEAK usart6_isr(void)
#define UART2_GPIO_RX
Definition: apogee_1.0.h:120
#define UART3_GPIO_TX
Definition: krooz_sd.h:91
void uart_transmit(struct uart_periph *p, uint8_t data)
Definition: uart_arch.c:75
static void usart_isr(struct uart_periph *p)
Definition: uart_arch.c:129
#define USE_UART2_TX
Definition: apogee_1.0.h:121
#define NVIC_UART4_IRQ
#define UART5_GPIO_PORT_RX
Definition: krooz_sd.h:94
#define UART5_GPIO_RX
Definition: krooz_sd.h:95
#define FALSE
Definition: imu_chimu.h:141
#define UPARITY_ODD
Definition: uart.h:49
#define UPARITY_EVEN
Definition: uart.h:50
#define UART4_GPIO_PORT_TX
Definition: apogee_0.99.h:52
CM3_WEAK uart5_isr(void)
UART peripheral.
Definition: uart.h:55
#define UART4_GPIO_TX
Definition: apogee_0.99.h:53
#define UBITS_7
Definition: uart.h:42
#define UART2_GPIO_TX
Definition: lisa_l_1.0.h:62
#define UART1_GPIO_TX
Definition: apogee_0.99.h:47
#define UART_TX_BUFFER_SIZE
Definition: uart.h:35
void uart_periph_init(struct uart_periph *p)
Definition: uart.c:181
unsigned long uint32_t
Definition: types.h:18
#define NVIC_UART5_IRQ
#define UART1_GPIO_PORT_RX
Definition: apogee_0.99.h:44
#define UART6_GPIO_AF
Definition: apogee_0.99.h:55
void uart_periph_set_bits_stop_parity(struct uart_periph *p, uint8_t bits, uint8_t stop, uint8_t parity)
Definition: uart_arch.c:71
#define UART1_GPIO_RX
Definition: apogee_0.99.h:45
void uart_periph_set_mode(struct uart_periph *p, bool_t tx_enabled, bool_t rx_enabled, bool_t hw_flow_control)
Definition: uart_arch.c:88
#define NVIC_USART6_IRQ
uint16_t rx_insert_idx
Definition: uart.h:58
#define UART4_GPIO_RX
Definition: apogee_0.99.h:51
CM3_WEAK usart2_isr(void)
#define UART4_GPIO_PORT_RX
Definition: apogee_0.99.h:50
#define UART3_GPIO_PORT_RX
Definition: krooz_sd.h:88
#define TRUE
Definition: imu_chimu.h:144
void gpio_setup_pin_af(uint32_t port, uint16_t pin, uint8_t af, bool_t is_output)
Setup a gpio for input or output with alternate function.
uint8_t tx_buf[UART_TX_BUFFER_SIZE]
Transmit buffer.
Definition: uart.h:61
#define NVIC_USART2_IRQ
#define UART6_GPIO_TX
Definition: apogee_0.99.h:59
#define UART3_GPIO_PORT_TX
Definition: krooz_sd.h:90
#define UART6_GPIO_RX
Definition: apogee_0.99.h:57
#define UART5_GPIO_PORT_TX
Definition: krooz_sd.h:96
unsigned char uint8_t
Definition: types.h:14
#define UART2_GPIO_PORT_RX
Definition: apogee_1.0.h:119
CM3_WEAK usart3_isr(void)
uint16_t tx_insert_idx
Definition: uart.h:62
#define UART5_GPIO_TX
Definition: krooz_sd.h:97
#define UART6_GPIO_PORT_RX
Definition: apogee_0.99.h:56
#define USTOP_2
Definition: uart.h:46
uint8_t rx_buf[UART_RX_BUFFER_SIZE]
Receive buffer.
Definition: uart.h:57
#define UART2_GPIO_AF
Definition: apogee_1.0.h:118
#define UART1_GPIO_PORT_TX
Definition: apogee_0.99.h:46
static float p[2][2]
uint16_t rx_extract_idx
Definition: uart.h:59
#define UART1_GPIO_AF
Definition: apogee_0.99.h:43
#define UART5_GPIO_AF
Definition: krooz_sd.h:93
#define NVIC_USART1_IRQ
CM3_WEAK usart1_isr(void)
#define UART6_GPIO_PORT_TX
Definition: apogee_0.99.h:58
#define UART_RX_BUFFER_SIZE
Definition: uart.h:34
#define UART3_GPIO_RX
Definition: krooz_sd.h:89
void uart_periph_set_baudrate(struct uart_periph *p, uint32_t baud)
Definition: uart_arch.c:65
static void usart_enable_irq(uint8_t IRQn)
Definition: uart_arch.c:176