Paparazzi UAS  v5.2.2_stable-0-gd6b9f29
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i2c_arch.c
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1 /*
2  * Copyright (C) 2009-2012 The Paparazzi Team
3  *
4  * This file is part of paparazzi.
5  *
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21  */
22 
29 #include "mcu_periph/i2c.h"
30 
31 #include BOARD_CONFIG
32 
33 #include <libopencm3/stm32/rcc.h>
34 #include <libopencm3/stm32/gpio.h>
35 #include <libopencm3/cm3/nvic.h>
36 #include <libopencm3/cm3/scb.h>
37 
38 #include "mcu_periph/gpio.h"
39 
40 
41 #ifdef I2C_DEBUG_LED
42 #include "i2c_debug_led.h"
43 #endif // I2C_DEBUG_LED
44 
47 
48 
49 // Error bit mask
50 // XXX: consider moving this define into libopencm3
51 #define I2C_SR1_ERR_MASK (I2C_SR1_SMBALERT | \
52  I2C_SR1_TIMEOUT | \
53  I2C_SR1_PECERR | \
54  I2C_SR1_OVR | \
55  I2C_SR1_AF | \
56  I2C_SR1_ARLO | \
57  I2C_SR1_BERR)
58 
59 // Bit Control
60 
61 #define BIT_X_IS_SET_IN_REG(X,REG) (((REG) & (X)) == (X))
62 
63 // disable and enable irq functions are not implemented in libopencm3 defining them here
64 // XXX: consider moving this definitions into libopencm3
65 static inline void __disable_irq(void) { asm volatile ("cpsid i"); }
66 static inline void __enable_irq(void) { asm volatile ("cpsie i"); }
67 
68 // Critical Zones
69 
70 #define __I2C_REG_CRITICAL_ZONE_START __disable_irq();
71 #define __I2C_REG_CRITICAL_ZONE_STOP __enable_irq();
72 
73 
74 #ifndef NVIC_I2C_IRQ_PRIO
75 #define NVIC_I2C1_IRQ_PRIO 0
76 #define NVIC_I2C2_IRQ_PRIO 0
77 #define NVIC_I2C3_IRQ_PRIO 0
78 #else
79 #define NVIC_I2C1_IRQ_PRIO NVIC_I2C_IRQ_PRIO
80 #define NVIC_I2C2_IRQ_PRIO NVIC_I2C_IRQ_PRIO
81 #define NVIC_I2C3_IRQ_PRIO NVIC_I2C_IRQ_PRIO
82 #endif
83 
84 #if USE_I2C1 || USE_I2C2 || USE_I2C3
85 #if defined(STM32F1)
86 static void i2c_setup_gpio(uint32_t i2c) {
87  switch (i2c) {
88 #if USE_I2C1
89  case I2C1:
91  gpio_set_mode(I2C1_GPIO_PORT, GPIO_MODE_OUTPUT_2_MHZ,
92  GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN,
94  break;
95 #endif
96 #if USE_I2C2
97  case I2C2:
99  gpio_set_mode(I2C2_GPIO_PORT, GPIO_MODE_OUTPUT_2_MHZ,
100  GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN,
102  break;
103 #endif
104  default:
105  break;
106  }
107 }
108 
109 #elif defined(STM32F4)
110 
111 static void i2c_setup_gpio(uint32_t i2c) {
112  switch (i2c) {
113 #if USE_I2C1
114  case I2C1:
116  gpio_mode_setup(I2C1_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE,
118  gpio_set_output_options(GPIOB, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ,
120  gpio_set_af(I2C1_GPIO_PORT, GPIO_AF4, I2C1_GPIO_SCL | I2C1_GPIO_SDA);
121  break;
122 #endif
123 #if USE_I2C2
124  case I2C2:
126  gpio_mode_setup(I2C2_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE,
128  gpio_set_output_options(I2C2_GPIO_PORT, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ,
130  gpio_set_af(I2C2_GPIO_PORT, GPIO_AF4,
132  break;
133 #endif
134 #if USE_I2C3
135  case I2C3:
137  gpio_mode_setup(I2C3_GPIO_PORT_SCL, GPIO_MODE_AF, GPIO_PUPD_NONE, I2C3_GPIO_SCL);
138  gpio_set_output_options(I2C3_GPIO_PORT_SCL, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ,
139  I2C3_GPIO_SCL);
140  gpio_set_af(I2C3_GPIO_PORT_SCL, GPIO_AF4, I2C3_GPIO_SCL);
141 
143  gpio_mode_setup(I2C3_GPIO_PORT_SDA, GPIO_MODE_AF, GPIO_PUPD_NONE, I2C3_GPIO_SDA);
144  gpio_set_output_options(I2C3_GPIO_PORT_SDA, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ,
145  I2C3_GPIO_SDA);
146  gpio_set_af(I2C3_GPIO_PORT_SDA, GPIO_AF4, I2C3_GPIO_SDA);
147  break;
148 #endif
149  default:
150  break;
151  }
152 }
153 #endif
154 #endif // USE_I2Cx
155 
156 static inline void PPRZ_I2C_SEND_STOP(uint32_t i2c)
157 {
158  // Man: p722: Stop generation after the current byte transfer or after the current Start condition is sent.
159  i2c_send_stop(i2c);
160 
161 #ifdef I2C_DEBUG_LED
162  LED2_ON();
163  LED1_ON();
164  LED1_OFF();
165  LED2_OFF();
166 #endif
167 }
168 
169 // (RE)START
170 
171 static inline void PPRZ_I2C_SEND_START(struct i2c_periph *periph)
172 {
173  uint32_t i2c = (uint32_t) periph->reg_addr;
174 
175  // Reset the buffer pointer to the first byte
176  periph->idx_buf = 0;
177 
178 #ifdef I2C_DEBUG_LED
179  LED_SHOW_ACTIVE_BITS(regs);
180 
181  LED2_ON();
182  LED1_ON();
183  LED1_OFF();
184  LED1_ON();
185  LED1_OFF();
186  LED1_ON();
187  LED1_OFF();
188  LED2_OFF();
189 #endif
190 
191  // Enable Error IRQ, Event IRQ but disable Buffer IRQ
192  i2c_enable_interrupt(i2c, I2C_CR2_ITERREN);
193  i2c_enable_interrupt(i2c, I2C_CR2_ITEVTEN);
194  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
195 
196  // Issue a new start
197  i2c_nack_current(i2c);
198  i2c_disable_ack(i2c);
199  i2c_clear_stop(i2c);
200  i2c_peripheral_enable(i2c);
201  i2c_send_start(i2c);
202  periph->status = I2CStartRequested;
203 
204 }
205 
206 // STOP
207 
210 //
211 // SUBTRANSACTION SEQUENCES
212 // -We arrive here every time a ISR is called with no error
213 
219 };
220 
221 // Doc ID 13902 Rev 11 p 710/1072
222 // Transfer Sequence Diagram for Master Transmitter
223 static inline enum STMI2CSubTransactionStatus stmi2c_send(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
224 {
225  uint16_t SR1 = I2C_SR1(i2c);
226 
227  // Start Condition Was Just Generated
228  if (BIT_X_IS_SET_IN_REG( I2C_SR1_SB, SR1 ) )
229  {
230  // Disable buffer interrupt
231  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
232  // Send Slave address and wait for ADDR interrupt
233  i2c_send_data(i2c, trans->slave_addr);
234  // Document the current Status
235  periph->status = I2CAddrWrSent;
236  }
237  // Address Was Sent
238  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1) )
239  {
240  // Now read SR2 to clear the ADDR status Bit
241  uint16_t SR2 __attribute__ ((unused)) = I2C_SR2(i2c);
242 
243  // Maybe check we are transmitting (did not loose arbitration for instance)
244  // if (! BIT_X_IS_SET_IN_REG(I2C_SR2_TRA, SR2)) { }
245  // update: this should be caught by the ARLO error: so we will not arrive here
246 
247  // Send First max 2 bytes
248  i2c_send_data(i2c, trans->buf[0]);
249  if (trans->len_w > 1)
250  {
251  i2c_send_data(i2c, trans->buf[1]);
252  periph->idx_buf = 2;
253  }
254  else
255  {
256  periph->idx_buf = 1;
257  }
258 
259  // Enable buffer-space available interrupt
260  // only if there is more to send: wait for TXE, no more to send: wait for BTF
261  if ( periph->idx_buf < trans->len_w)
262  i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN);
263 
264  // Document the current Status
265  periph->status = I2CSendingByte;
266  }
267  // The buffer is not full anymore AND we were not waiting for BTF
268  else if ((BIT_X_IS_SET_IN_REG(I2C_SR1_TxE, SR1) ) && (BIT_X_IS_SET_IN_REG(I2C_CR2_ITBUFEN, I2C_CR2(i2c))) )
269  {
270  // Send the next byte
271  i2c_send_data(i2c, trans->buf[periph->idx_buf]);
272  periph->idx_buf++;
273 
274  // All bytes Sent? Then wait for BTF instead
275  if ( periph->idx_buf >= trans->len_w)
276  {
277  // Not interested anymore to know the buffer has space left
278  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
279  // Next interrupt will be BTF (or error)
280  }
281  }
282  // BTF: means last byte was sent
283  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1) )
284  {
285  if (trans->type == I2CTransTx)
286  {
287  // Tell the driver we are ready
288  trans->status = I2CTransSuccess;
289  }
290  // Otherwise we still need to do the receiving part
291 
292  return STMI2C_SubTra_Ready;
293  }
294  else // Event Logic Error
295  {
296  return STMI2C_SubTra_Error;
297  }
298 
299  return STMI2C_SubTra_Busy;
300 }
301 
302 // Doc ID 13902 Rev 11 p 714/1072
303 // Transfer Sequence Diagram for Master Receiver for N=1
304 static inline enum STMI2CSubTransactionStatus stmi2c_read1(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
305 {
306  uint16_t SR1 = I2C_SR1(i2c);
307 
308  // Start Condition Was Just Generated
309  if (BIT_X_IS_SET_IN_REG( I2C_SR1_SB, SR1 ) )
310  {
311  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
312  i2c_send_data(i2c, trans->slave_addr | 0x01);
313 
314  // Document the current Status
315  periph->status = I2CAddrRdSent;
316  }
317  // Address Was Sent
318  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1) )
319  {
320  // First Clear the ACK bit: after the next byte we do not want new bytes
321  i2c_nack_current(i2c);
322  i2c_disable_ack(i2c);
323 
324  // --- next to steps MUST be executed together to avoid missing the stop
326 
327  // Only after setting ACK, read SR2 to clear the ADDR (next byte will start arriving)
328  uint16_t SR2 __attribute__ ((unused)) = I2C_SR2(i2c);
329 
330  // Schedule a Stop
331  PPRZ_I2C_SEND_STOP(i2c);
332 
334  // --- end of critical zone -----------
335 
336  // Enable the RXNE: it will trigger as soon as the 1 byte is received to get the result
337  i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN);
338 
339  // Document the current Status
340  periph->status = I2CReadingLastByte;
341  }
342  // As soon as there is 1 byte ready to read, we have our byte
343  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_RxNE, SR1) )
344  {
345  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
346  trans->buf[0] = I2C_DR(i2c);
347 
348  // We got all the results (stop condition might still be in progress but this is the last interrupt)
349  trans->status = I2CTransSuccess;
350 
351  // Document the current Status:
352  // -the stop was actually already requested in the previous step
353  periph->status = I2CStopRequested;
354 
356  }
357  else // Event Logic Error
358  {
359  return STMI2C_SubTra_Error;
360  }
361 
362  return STMI2C_SubTra_Busy;
363 }
364 
365 // Doc ID 13902 Rev 11 p 713/1072
366 // Transfer Sequence Diagram for Master Receiver for N=2
367 static inline enum STMI2CSubTransactionStatus stmi2c_read2(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
368 {
369  uint16_t SR1 = I2C_SR1(i2c);
370 
371  // Start Condition Was Just Generated
372  if (BIT_X_IS_SET_IN_REG( I2C_SR1_SB, SR1 ) )
373  {
374  // according to the datasheet: instantly shedule a NAK on the second received byte:
375  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
376  i2c_enable_ack(i2c);
377  i2c_nack_next(i2c);
378  i2c_send_data(i2c, trans->slave_addr | 0x01);
379 
380  // Document the current Status
381  periph->status = I2CAddrRdSent;
382  }
383  // Address Was Sent
384  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1) )
385  {
386  // --- make absolutely sure this command is not delayed too much after the previous:
387  // --- the NAK bits must be set before the first byte arrived: allow other interrupts here
389 
390  // if transfer of DR was finished already then we will get too many bytes
391  // BEFORE clearing ACK, read SR2 to clear the ADDR (next byte will start arriving)
392  // clearing ACK after the byte transfer has already started will NACK the next (2nd)
393  uint16_t SR2 __attribute__ ((unused)) = I2C_SR2(i2c);
394 
395  // NOT First Clear the ACK bit but only AFTER clearing ADDR
396  i2c_disable_ack(i2c);
397 
398  // Disable the RXNE and wait for BTF
399  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
400 
402  // --- end of critical zone -----------
403 
404  // We do not set the RxE but wait for both bytes to arrive using BTF
405 
406  // Document the current Status
407  periph->status = I2CReadingByte;
408  }
409  // Receive buffer if full, master is halted: BTF
410  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1) )
411  {
412  // Stop condition MUST be set BEFORE reading the DR
413  // otherwise since there is new buffer space a new byte will be read
414  PPRZ_I2C_SEND_STOP(i2c);
415 
416  // Document the current Status
417  periph->status = I2CStopRequested;
418 
419  trans->buf[0] = I2C_DR(i2c);
420  trans->buf[1] = I2C_DR(i2c);
421 
422  // We got all the results
423  trans->status = I2CTransSuccess;
424 
426  }
427  else // Event Logic Error
428  {
429  return STMI2C_SubTra_Error;
430  }
431 
432  return STMI2C_SubTra_Busy;
433 }
434 
435 // Doc ID 13902 Rev 11 p 712/1072
436 // Transfer Sequence Diagram for Master Receiver for N>2
437 static inline enum STMI2CSubTransactionStatus stmi2c_readmany(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
438 {
439  uint16_t SR1 = I2C_SR1(i2c);
440 
441  // Start Condition Was Just Generated
442  if (BIT_X_IS_SET_IN_REG( I2C_SR1_SB, SR1 ) )
443  {
444  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
445  // The first data byte will be acked in read many so the slave knows it should send more
446  i2c_nack_current(i2c);
447  i2c_enable_ack(i2c);
448  // Clear the SB flag
449  i2c_send_data(i2c, trans->slave_addr | 0x01);
450 
451  // Document the current Status
452  periph->status = I2CAddrRdSent;
453  }
454  // Address Was Sent
455  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1) )
456  {
457  periph->idx_buf = 0;
458 
459  // Enable RXNE: receive an interrupt any time a byte is available
460  // only enable if MORE than 3 bytes need to be read
461  if (periph->idx_buf < (trans->len_r - 3))
462  {
463  i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN);
464  }
465 
466  // ACK is still on to get more DATA
467  // Read SR2 to clear the ADDR (next byte will start arriving)
468  uint16_t SR2 __attribute__ ((unused)) = I2C_SR2(i2c);
469 
470  // Document the current Status
471  periph->status = I2CReadingByte;
472  }
473  // one or more bytes are available AND we were interested in Buffer interrupts
474  else if ( (BIT_X_IS_SET_IN_REG(I2C_SR1_RxNE, SR1) ) && (BIT_X_IS_SET_IN_REG(I2C_CR2_ITBUFEN, I2C_CR2(i2c))) )
475  {
476  // read byte until 3 bytes remain to be read (e.g. len_r = 6, -> idx=3 means idx 3,4,5 = 3 remain to be read
477  if (periph->idx_buf < (trans->len_r - 3))
478  {
479  trans->buf[periph->idx_buf] = I2C_DR(i2c);
480  periph->idx_buf ++;
481  }
482  // from : 3bytes -> last byte: do nothing
483  //
484  // finally: this was the last byte
485  else if (periph->idx_buf >= (trans->len_r - 1))
486  {
487  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
488 
489  // Last Value
490  trans->buf[periph->idx_buf] = i2c_get_data(i2c);
491  periph->idx_buf ++;
492 
493  // We got all the results
494  trans->status = I2CTransSuccess;
495 
497  }
498 
499  // Check for end of transaction: start waiting for BTF instead of RXNE
500  if (periph->idx_buf < (trans->len_r - 3))
501  {
502  i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN);
503  }
504  else // idx >= len-3: there are 3 bytes to be read
505  {
506  // We want to halt I2C to have sufficient time to clear ACK, so:
507  // Stop listening to RXNE as it will be triggered infinitely since we did not empty the buffer
508  // on the next (second in buffer) received byte BTF will be set (buffer full and I2C halted)
509  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
510  }
511  }
512  // Buffer is full while this was not a RXNE interrupt
513  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1) )
514  {
515  // Now the shift register and data register contain data(n-2) and data(n-1)
516  // And I2C is halted so we have time
517 
518  // --- Make absolutely sure the next 2 I2C actions are performed with no delay
520 
521  // First we clear the ACK while the SCL is held low by BTF
522  i2c_disable_ack(i2c);
523 
524  // Now that ACK is cleared we read one byte: instantly the last byte is being clocked in...
525  trans->buf[periph->idx_buf] = i2c_get_data(i2c);
526  periph->idx_buf ++;
527 
528  // Now the last byte is being clocked. Stop in MUST be set BEFORE the transfer of the last byte is complete
529  PPRZ_I2C_SEND_STOP(i2c);
530 
532 
533 
534  // --- end of critical zone -----------
535 
536  // Document the current Status
537  periph->status = I2CStopRequested;
538 
539  // read the byte2 we had in the buffer (BTF means 2 bytes available)
540  trans->buf[periph->idx_buf] = i2c_get_data(i2c);
541  periph->idx_buf ++;
542 
543  // Ask for an interrupt to read the last byte (which is normally still busy now)
544  // The last byte will be received with RXNE
545  i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN);
546  }
547  else // Event Logic Error
548  {
549  return STMI2C_SubTra_Error;
550  }
551 
552  return STMI2C_SubTra_Busy;
553 }
554 
556 // Restore bus conditions to normal after errors
557 
558 static inline void i2c_error(struct i2c_periph *periph)
559 {
560 #ifdef I2C_DEBUG_LED
561  uint8_t err_nr = 0;
562 #endif
563  periph->errors->er_irq_cnt;
564  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_AF) != 0) { /* Acknowledge failure */
565  periph->errors->ack_fail_cnt++;
566  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_AF;
567 #ifdef I2C_DEBUG_LED
568  err_nr = 1;
569 #endif
570  }
571  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_BERR) != 0) { /* Misplaced Start or Stop condition */
572  periph->errors->miss_start_stop_cnt++;
573  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_BERR;
574 #ifdef I2C_DEBUG_LED
575  err_nr = 2;
576 #endif
577  }
578  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_ARLO) != 0) { /* Arbitration lost */
579  periph->errors->arb_lost_cnt++;
580  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_ARLO;
581 #ifdef I2C_DEBUG_LED
582  err_nr = 3;
583 #endif
584  }
585  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_OVR) != 0) { /* Overrun/Underrun */
586  periph->errors->over_under_cnt++;
587  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_OVR;
588 #ifdef I2C_DEBUG_LED
589  err_nr = 4;
590 #endif
591  }
592  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_PECERR) != 0) { /* PEC Error in reception */
593  periph->errors->pec_recep_cnt++;
594  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_PECERR;
595 #ifdef I2C_DEBUG_LED
596  err_nr = 5;
597 #endif
598  }
599  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_TIMEOUT) != 0) { /* Timeout or Tlow error */
600  periph->errors->timeout_tlow_cnt++;
601  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_TIMEOUT;
602 #ifdef I2C_DEBUG_LED
603  err_nr = 6;
604 #endif
605  }
606  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_SMBALERT) != 0) { /* SMBus alert */
607  periph->errors->smbus_alert_cnt++;
608  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_SMBALERT;
609 #ifdef I2C_DEBUG_LED
610  err_nr = 7;
611 #endif
612  }
613 
614 #ifdef I2C_DEBUG_LED
615  LED_ERROR(20, err_nr);
616 #endif
617 
618  return;
619 }
620 
621 
623 {
624  uint16_t SR1 = I2C_SR1(i2c);
625 
626  // Certainly do not wait for buffer interrupts:
627  // -------------------------------------------
628  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN); // Disable TXE, RXNE
629 
630  // Error interrupts are handled separately:
631  // ---------------------------------------
632 
633  // Clear Event interrupt conditions:
634  // --------------------------------
635 
636  // Start Condition Was Generated
637  if (BIT_X_IS_SET_IN_REG( I2C_SR1_SB, SR1 ) )
638  {
639  // SB: cleared by software when reading SR1 and writing to DR
640  i2c_send_data(i2c, 0x00);
641  }
642  // Address Was Sent
643  if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1) )
644  {
645  // ADDR: Cleared by software when reading SR1 and then SR2
646  uint16_t SR2 __attribute__ ((unused)) = I2C_SR2(i2c);
647  }
648  // Byte Transfer Finished
649  if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1) )
650  {
651  // SB: cleared by software when reading SR1 and reading/writing to DR
652  uint8_t dummy __attribute__ ((unused)) = i2c_get_data(i2c);
653  i2c_send_data(i2c, 0x00);
654  }
655 
656 }
657 
658 
660 // Restore bus conditions to normal after errors
661 
662 static inline void i2c_irq(struct i2c_periph *periph)
663 {
664 
665  /*
666  There are 7 possible event reasons to get here + all errors
667 
668  If IT_EV_FEN
669  -------------------------
670 
671  We are always interested in all IT_EV_FEV: all are required.
672 
673  1) SB // Start Condition Success in Master mode
674  2) ADDR // Address sent received Acknoledge
675  [ADDR10] // -- 10bit address stuff: not used
676  [STOPF] // -- only for slaves: master has no stop interrupt: not used
677  3) BTF // I2C has stopped working (it is waiting for new data, all buffers are tx_empty/rx_full)
678 
679  // Beware: using the buffered I2C has some interesting properties:
680  - in master receive mode: BTF only occurs after the 2nd received byte: after the first byte is received it is
681  in RD but the I2C can still receive a second byte. Only when the 2nd byte is received while the RxNE is 1
682  then a BTF occurs (I2C can not continue receiving bytes or they will get lost). During BTF I2C is halted (SCL held low)
683  - in master transmit mode: when writing a byte to WD, you instantly get a new TxE interrupt while the first is not
684  transmitted yet. The byte was pushed to the I2C shift register and the buffer is ready for more. You can already
685  fill new data in the buffer while the first is still being transmitted for max performance transmission.
686 
687  // Beware: besides data buffering you can/must plan several consecutive actions. You can send 2 bytes to the buffer, ask for a stop and
688  a new start in one go.
689 
690  - thanks to / because of this buffering and event sheduling there is not 1 interrupt per start / byte / stop
691  This also means you must think more in advance and a transaction could be popped from the transaction stack even before it's
692  stop condition is actually generated.
693 
694  // Beware: the order in which Status (and other register) is read determines how flags are cleared.
695  You should NOT simply read SR1 & SR2 every time
696 
697  If IT_EV_FEN AND IT_EV_BUF
698  --------------------------
699 
700  Buffer event are not always wanted and are typically switched on during longer data transfers. Make sure to turn off in time.
701 
702  4) RxNE
703  5) TxE
704 
705  --------------------------------------------------------------------------------------------------
706 
707  The STM waits indefinately (holding SCL low) for user interaction:
708  a) after a master-start (waiting for address)
709  b) after an address (waiting for data)
710  not during data sending when using buffered
711  c) after the last byte is transmitted (waiting for either stop or restart)
712  not during data receiving when using buffered
713  not after the last byte is received
714 
715  - The STM I2C stalls indefinately when a stop condition was attempted that
716  did not succeed. The BUSY flag remains on.
717  - There is no STOP interrupt.
718 
719  Caution Reading the status:
720  - Caution: this clears several flags and can start transmissions etc...
721  - Certain flags like STOP / (N)ACK need to be guaranteed to be set before
722  the transmission of the byte is finished. At higher clock rates that can be
723  quite fast: so we allow no other interrupt to be triggered in between
724  reading the status and setting all needed flags
725 
726  */
727 
728  // Here we go ...
729 
730  // Apparently we got an I2C interrupt: EVT BUF or ERR
731 
732 #ifdef I2C_DEBUG_LED
733  // Notify ISR is triggered
734  LED1_ON();
735  LED1_OFF();
736 #endif
737 
738  // Save Some Direct Access to the I2C Registers ...
739  uint32_t i2c = (uint32_t) periph->reg_addr;
740 
742  // Check if we were ready ...
743  if (periph->trans_extract_idx == periph->trans_insert_idx)
744  {
745  // Nothing Left To Do
746 
747 #ifdef I2C_DEBUG_LED
748  LED2_ON();
749  LED1_ON();
750  LED2_OFF();
751  LED1_OFF();
752 
753  // no transaction and also an error?
754  LED_SHOW_ACTIVE_BITS(regs);
755 #endif
756 
757  // If we still get an interrupt but there are no more things to do
758  // (which can happen if an event was sheduled just before a bus error occurs)
759  // (or can happen if both error and event interrupts were called together [the 2nd will then get this error])
760 
761  // since there is nothing more to do: its easy: just stop: clear all interrupt generating bits
762 
763  // Count The Errors
764  i2c_error(periph);
765 
766  // Clear Running Events
768 
769  // Mark this as a special error
770  periph->errors->last_unexpected_event++;
771 
772  // Document the current Status
773  periph->status = I2CIdle;
774 
775  // There are no transactions anymore: return
776  // further-on in this routine we need a transaction pointer: so we are not allowed to continue
777  return;
778  }
779 
780  // get the I2C transaction we were working on ...
781 
782  enum STMI2CSubTransactionStatus ret = 0;
783  struct i2c_transaction* trans = periph->trans[periph->trans_extract_idx];
784 
786  // If there was an error:
787  if (( I2C_SR1(i2c) & I2C_SR1_ERR_MASK ) != 0x0000)
788  {
789 
790 #ifdef I2C_DEBUG_LED
791  LED1_ON();
792  LED2_ON();
793  LED1_OFF();
794  LED2_OFF();
795 
796  LED_SHOW_ACTIVE_BITS(regs);
797 #endif
798 
799  // Notify everyone about the error ...
800 
801  // Set result in transaction
802  trans->status = I2CTransFailed;
803 
804  // Document the current Status
805  periph->status = I2CFailed;
806 
807  // Make sure a TxRx does not Restart
808  trans->type = I2CTransRx;
809 
810  // Count The Errors
811  i2c_error(periph);
812 
813  // Clear Running Events
815 
816  // Now continue as if everything was normal from now on
817  ret = STMI2C_SubTra_Ready;
818 
819  }
820 
822  // Normal Event:
823  else
824  {
825 
828  //
829  // SUB-TRANSACTION HANDLER
830 
831  if (trans->type == I2CTransRx) // TxRx are converted to Rx after the Tx Part
832  {
833  switch (trans->len_r)
834  {
835  case 1:
836  ret = stmi2c_read1(i2c,periph,trans);
837  break;
838  case 2:
839  ret = stmi2c_read2(i2c,periph,trans);
840  break;
841  default:
842  ret = stmi2c_readmany(i2c,periph,trans);
843  break;
844  }
845  }
846  else // TxRx or Tx
847  {
848  ret = stmi2c_send(i2c,periph,trans);
849  }
850  }
851 
853  // Sub-transaction has finished
854  if (ret != STMI2C_SubTra_Busy)
855  {
856  // Ready or SubTraError
857  // -ready: with or without stop already asked
858 
859  // In case of unexpected event condition during subtransaction handling:
860  if (ret == STMI2C_SubTra_Error)
861  {
862  // Tell everyone about the subtransaction error:
863  // this is the previously called SPURRIOUS INTERRUPT
864  periph->status = I2CFailed;
865  trans->type = I2CTransRx; // Avoid possible restart
866  trans->status = I2CTransFailed; // Notify Ready
867  periph->errors->unexpected_event_cnt++;
868 
869  // Error
870 #ifdef I2C_DEBUG_LED
871  LED2_ON();
872  LED1_ON();
873  LED2_OFF();
874  LED1_OFF();
875 
876  LED_SHOW_ACTIVE_BITS(regs);
877 #endif
878 
879  // Clear Running Events
881  }
882 
883  // RxTx -> Restart and do Rx part
884  if (trans->type == I2CTransTxRx)
885  {
886  trans->type = I2CTransRx;
887  periph->status = I2CStartRequested;
888  i2c_send_start(i2c);
889 
890  // Silent any BTF that would occur before SB
891  i2c_send_data(i2c, 0x00);
892  }
893  // If a restart is not needed: Rx part or Tx-only
894  else
895  {
896  // Ready, no stop condition set yet
897  if (ret == STMI2C_SubTra_Ready)
898  {
899 
900  // Program a stop
901  PPRZ_I2C_SEND_STOP(i2c);
902 
903  // Silent any BTF that would occur before STOP is executed
904  i2c_send_data(i2c, 0x00);
905  }
906 
907  // Jump to the next transaction
908  periph->trans_extract_idx++;
910  periph->trans_extract_idx = 0;
911 
912  // Tell everyone we are ready
913  periph->status = I2CIdle;
914 
915 
916  // if we have no more transaction to process, stop here
917  if (periph->trans_extract_idx == periph->trans_insert_idx)
918  {
919 
920  periph->watchdog = -1; // stop watchdog
921 #ifdef I2C_DEBUG_LED
922  LED2_ON();
923  LED1_ON();
924  LED1_OFF();
925  LED1_ON();
926  LED1_OFF();
927  LED2_OFF();
928 #endif
929  }
930  // if not, start next transaction
931  else
932  {
933  // Restart transaction doing the Rx part now
934  // --- moved to idle function
935  PPRZ_I2C_SEND_START(periph);
936  // ------
937  }
938  }
939  }
940 
941  return;
942 }
943 
944 
945 /*
946 // Make sure the bus is free before resetting (p722)
947 if (regs->SR2 & (I2C_FLAG_BUSY >> 16)) {
948 // Reset the I2C block
949 I2C_SoftwareResetCmd(periph->reg_addr, ENABLE);
950 I2C_SoftwareResetCmd(periph->reg_addr, DISABLE);
951 }
952 */
953 
954 
955 #if USE_I2C0
956 #error "The STM32 doesn't have I2C0, use I2C1 or I2C2"
957 #endif
958 
959 #if USE_I2C1
960 
962 #ifndef I2C1_CLOCK_SPEED
963 #define I2C1_CLOCK_SPEED 200000
964 #endif
965 PRINT_CONFIG_VAR(I2C1_CLOCK_SPEED)
966 
967 struct i2c_errors i2c1_errors;
968 
969 void i2c1_hw_init(void) {
970 
971  i2c1.reg_addr = (void *)I2C1;
972  i2c1.init_struct = NULL;
973  i2c1.errors = &i2c1_errors;
974  i2c1.watchdog = -1;
975 
976  /* zeros error counter */
977  ZEROS_ERR_COUNTER(i2c1_errors);
978 
979  // Extra
980 #ifdef I2C_DEBUG_LED
981  LED_INIT();
982 #else
983 
984  /* reset peripheral to default state ( sometimes not achieved on reset :( ) */
985  //rcc_periph_reset_pulse(RST_I2C1);
986 
987  /* Configure and enable I2C1 event interrupt --------------------------------*/
988  nvic_set_priority(NVIC_I2C1_EV_IRQ, NVIC_I2C1_IRQ_PRIO);
989  nvic_enable_irq(NVIC_I2C1_EV_IRQ);
990 
991  /* Configure and enable I2C1 err interrupt ----------------------------------*/
992  nvic_set_priority(NVIC_I2C1_ER_IRQ, NVIC_I2C1_IRQ_PRIO+1);
993  nvic_enable_irq(NVIC_I2C1_ER_IRQ);
994 
995  /* Enable peripheral clocks -------------------------------------------------*/
996  /* Enable I2C1 clock */
997  rcc_periph_clock_enable(RCC_I2C1);
998  /* setup gpio clock and pins */
999  i2c_setup_gpio(I2C1);
1000 
1001  rcc_periph_reset_pulse(RST_I2C1);
1002 
1003  // enable peripheral
1004  i2c_peripheral_enable(I2C1);
1005 
1006  /*
1007  * XXX: there is a function to do that already in libopencm3 but I am not
1008  * sure if it is correct, using direct register instead (esden)
1009  */
1010  //i2c_set_own_7bit_slave_address(I2C1, 0);
1011  I2C_OAR1(I2C1) = 0 | 0x4000;
1012 
1013  // enable error interrupts
1014  i2c_enable_interrupt(I2C1, I2C_CR2_ITERREN);
1015 
1016  i2c_setbitrate(&i2c1, I2C1_CLOCK_SPEED);
1017 #endif
1018 }
1019 
1020 void i2c1_ev_isr(void) {
1021  uint32_t i2c = (uint32_t) i2c1.reg_addr;
1022  i2c_disable_interrupt(i2c, I2C_CR2_ITERREN);
1023  i2c1.watchdog = 0; // restart watchdog
1024  i2c_irq(&i2c1);;
1025  i2c_enable_interrupt(i2c, I2C_CR2_ITERREN);
1026 }
1027 
1028 void i2c1_er_isr(void) {
1029  uint32_t i2c = (uint32_t) i2c1.reg_addr;
1030  i2c_disable_interrupt(i2c, I2C_CR2_ITEVTEN);
1031  i2c1.watchdog = 0; // restart watchdog
1032  i2c_irq(&i2c1);
1033  i2c_enable_interrupt(i2c, I2C_CR2_ITEVTEN);
1034 }
1035 
1036 #endif /* USE_I2C1 */
1037 
1038 #if USE_I2C2
1039 
1041 #ifndef I2C2_CLOCK_SPEED
1042 #define I2C2_CLOCK_SPEED 300000
1043 #endif
1044 PRINT_CONFIG_VAR(I2C2_CLOCK_SPEED)
1045 
1046 struct i2c_errors i2c2_errors;
1047 
1048 void i2c2_hw_init(void) {
1049 
1050  i2c2.reg_addr = (void *)I2C2;
1051  i2c2.init_struct = NULL;
1052  i2c2.errors = &i2c2_errors;
1053  i2c2.watchdog = -1;
1054 
1055  /* zeros error counter */
1056  ZEROS_ERR_COUNTER(i2c2_errors);
1057 
1058  /* reset peripheral to default state ( sometimes not achieved on reset :( ) */
1059  //rcc_periph_reset_pulse(RST_I2C2);
1060 
1061  /* Configure and enable I2C2 event interrupt --------------------------------*/
1062  nvic_set_priority(NVIC_I2C2_EV_IRQ, NVIC_I2C2_IRQ_PRIO);
1063  nvic_enable_irq(NVIC_I2C2_EV_IRQ);
1064 
1065  /* Configure and enable I2C2 err interrupt ----------------------------------*/
1066  nvic_set_priority(NVIC_I2C2_ER_IRQ, NVIC_I2C2_IRQ_PRIO+1);
1067  nvic_enable_irq(NVIC_I2C2_ER_IRQ);
1068 
1069  /* Enable peripheral clocks -------------------------------------------------*/
1070  /* Enable I2C2 clock */
1071  rcc_periph_clock_enable(RCC_I2C2);
1072 
1073  /* setup gpio clock and pins */
1074  i2c_setup_gpio(I2C2);
1075 
1076  rcc_periph_reset_pulse(RST_I2C2);
1077 
1078  // enable peripheral
1079  i2c_peripheral_enable(I2C2);
1080 
1081  /*
1082  * XXX: there is a function to do that already in libopencm3 but I am not
1083  * sure if it is correct, using direct register instead (esden)
1084  */
1085  //i2c_set_own_7bit_slave_address(I2C2, 0);
1086  I2C_OAR1(I2C2) = 0 | 0x4000;
1087 
1088  // enable error interrupts
1089  i2c_enable_interrupt(I2C2, I2C_CR2_ITERREN);
1090 
1091  i2c_setbitrate(&i2c2, I2C2_CLOCK_SPEED);
1092 }
1093 
1094 void i2c2_ev_isr(void) {
1095  uint32_t i2c = (uint32_t) i2c2.reg_addr;
1096  i2c_disable_interrupt(i2c, I2C_CR2_ITERREN);
1097  i2c2.watchdog = 0; // restart watchdog
1098  i2c_irq(&i2c2);
1099  i2c_enable_interrupt(i2c, I2C_CR2_ITERREN);
1100 }
1101 
1102 void i2c2_er_isr(void) {
1103  uint32_t i2c = (uint32_t) i2c2.reg_addr;
1104  i2c_disable_interrupt(i2c, I2C_CR2_ITEVTEN);
1105  i2c2.watchdog = 0; // restart watchdog
1106  i2c_irq(&i2c2);
1107  i2c_enable_interrupt(i2c, I2C_CR2_ITEVTEN);
1108 }
1109 
1110 #endif /* USE_I2C2 */
1111 
1112 
1113 #if USE_I2C3 && defined STM32F4
1114 
1116 #ifndef I2C3_CLOCK_SPEED
1117 #define I2C3_CLOCK_SPEED 300000
1118 #endif
1119 PRINT_CONFIG_VAR(I2C3_CLOCK_SPEED)
1120 
1121 struct i2c_errors i2c3_errors;
1122 
1123 void i2c3_hw_init(void) {
1124 
1125  i2c3.reg_addr = (void *)I2C3;
1126  i2c3.init_struct = NULL;
1127  i2c3.errors = &i2c3_errors;
1128  i2c3.watchdog = -1;
1129 
1130  /* zeros error counter */
1131  ZEROS_ERR_COUNTER(i2c3_errors);
1132 
1133  /* reset peripheral to default state ( sometimes not achieved on reset :( ) */
1134  //rcc_periph_reset_pulse(RST_I2C3);
1135 
1136  /* Configure and enable I2C3 event interrupt --------------------------------*/
1137  nvic_set_priority(NVIC_I2C3_EV_IRQ, NVIC_I2C3_IRQ_PRIO);
1138  nvic_enable_irq(NVIC_I2C3_EV_IRQ);
1139 
1140  /* Configure and enable I2C3 err interrupt ----------------------------------*/
1141  nvic_set_priority(NVIC_I2C3_ER_IRQ, NVIC_I2C3_IRQ_PRIO+1);
1142  nvic_enable_irq(NVIC_I2C3_ER_IRQ);
1143 
1144  /* Enable peripheral clocks -------------------------------------------------*/
1145  /* Enable I2C3 clock */
1146  rcc_periph_clock_enable(RCC_I2C3);
1147 
1148  /* setup gpio clock and pins */
1149  i2c_setup_gpio(I2C3);
1150 
1151  rcc_periph_reset_pulse(RST_I2C3);
1152 
1153  // enable peripheral
1154  i2c_peripheral_enable(I2C3);
1155 
1156  /*
1157  * XXX: there is a function to do that already in libopencm3 but I am not
1158  * sure if it is correct, using direct register instead (esden)
1159  */
1160  //i2c_set_own_7bit_slave_address(I2C3, 0);
1161  I2C_OAR1(I2C3) = 0 | 0x4000;
1162 
1163  // enable error interrupts
1164  i2c_enable_interrupt(I2C3, I2C_CR2_ITERREN);
1165 
1166  i2c_setbitrate(&i2c3, I2C3_CLOCK_SPEED);
1167 }
1168 
1169 void i2c3_ev_isr(void) {
1170  uint32_t i2c = (uint32_t) i2c3.reg_addr;
1171  i2c_disable_interrupt(i2c, I2C_CR2_ITERREN);
1172  i2c3.watchdog = 0; // restart watchdog
1173  i2c_irq(&i2c3);
1174  i2c_enable_interrupt(i2c, I2C_CR2_ITERREN);
1175 }
1176 
1177 void i2c3_er_isr(void) {
1178  uint32_t i2c = (uint32_t) i2c3.reg_addr;
1179  i2c_disable_interrupt(i2c, I2C_CR2_ITEVTEN);
1180  I2C_CR2(i2c) &= ~I2C_CR2_ITEVTEN;
1181  i2c3.watchdog = 0; // restart watchdog
1182  i2c_irq(&i2c3);
1183  i2c_enable_interrupt(i2c, I2C_CR2_ITEVTEN);
1184 }
1185 
1186 #endif /* USE_I2C3 */
1187 
1189 // Set Bitrate to Match your application:
1190 // -short wires, low capacitance bus: IMU: high speed
1191 // -long wires with a lot of capacitance: motor controller: put speed as low as possible
1192 
1193 void i2c_setbitrate(struct i2c_periph *periph, int bitrate)
1194 {
1195  // If NOT Busy
1196  if (i2c_idle(periph))
1197  {
1198  volatile int devider;
1199  volatile int risetime;
1200 
1201  uint32_t i2c = (uint32_t) periph->reg_addr;
1202 
1203  /*****************************************************
1204  Bitrate:
1205 
1206  -CR2 + CCR + TRISE registers
1207  -only change when PE=0
1208 
1209  e.g.
1210 
1211  10kHz: 36MHz + Standard 0x708 + 0x25
1212  70kHz: 36MHz + Standard 0x101 +
1213  400kHz: 36MHz + Fast 0x1E + 0xb
1214 
1215  // 1) Program peripheral input clock CR2: to get correct timings
1216  // 2) Configure clock control registers
1217  // 3) Configure rise time register
1218  ******************************************************/
1219 
1220  if (bitrate < 3000)
1221  bitrate = 3000;
1222 
1223  // rcc_ppre1_frequency is normally configured to max: 36MHz on F1 and 42MHz on F4
1224  // in fast mode: 2counts low 1 count high -> / 3:
1225  // in standard mode: 1 count low, 1 count high -> /2:
1226  devider = (rcc_ppre1_frequency/2000) / (bitrate/1000);
1227 
1228  // never allow faster than 600kbps
1229  if (devider < 20)
1230  devider = 20;
1231 
1232  // no overflow either
1233  if (devider >=4095)
1234  devider = 4095;
1235 
1236  // risetime can be up to 1/6th of the period
1237  risetime = 1000000 / (bitrate/1000) / 6 / 28;
1238 
1239  if (risetime < 10)
1240  risetime = 10;
1241 
1242  // more will overflow the register: for more you should lower the FREQ
1243  if (risetime >=31)
1244  risetime = 31;
1245 
1246  // we do not expect an interrupt as the interface should have been idle, but just in case...
1247  __disable_irq(); // this code is in user space:
1248 
1249  // CCR can only be written when PE is disabled
1250  // p731 note 5
1251  i2c_peripheral_disable(i2c);
1252 
1253  // 1)
1254 #ifdef STM32F1
1255  i2c_set_clock_frequency(i2c, I2C_CR2_FREQ_36MHZ);
1256 #else // STM32F4
1257  i2c_set_clock_frequency(i2c, I2C_CR2_FREQ_42MHZ);
1258 #endif
1259  // 2)
1260  //i2c_set_fast_mode(i2c);
1261  i2c_set_ccr(i2c, devider);
1262  // 3)
1263  i2c_set_trise(i2c, risetime);
1264 
1265  // Re-Enable
1266  i2c_peripheral_enable(i2c);
1267 
1268  __enable_irq();
1269 
1270 #ifdef I2C_DEBUG_LED
1271  __disable_irq(); // this code is in user space:
1272 
1273  LED2_ON();
1274  LED1_ON();
1275  LED2_OFF();
1276  LED1_OFF();
1277  LED2_ON();
1278  LED1_ON();
1279  LED2_OFF();
1280  LED1_OFF();
1281 
1282  __enable_irq();
1283 #endif
1284 
1285  }
1286 }
1287 
1288 #if USE_I2C1 || USE_I2C2 || USE_I2C3
1289 static inline void i2c_scl_set(uint32_t i2c) {
1290 #if USE_I2C1
1291  if (i2c == I2C1)
1293 #endif
1294 #if USE_I2C2
1295  if (i2c == I2C2)
1297 #endif
1298 #if USE_I2C3
1299  if (i2c == I2C3)
1301 #endif
1302 }
1303 
1304 static inline void i2c_scl_clear(uint32_t i2c) {
1305 #if USE_I2C1
1306  if (i2c == I2C1)
1308 #endif
1309 #if USE_I2C2
1310  if (i2c == I2C2)
1312 #endif
1313 #if USE_I2C3
1314  if (i2c == I2C3)
1316 #endif
1317 }
1318 
1319 #define WD_DELAY 20 // number of ticks with 2ms - 40ms delay before resetting the bus
1320 #define WD_RECOVERY_TICKS 10 // number of generated SCL clocking pulses
1321 
1322 static void i2c_wd_check(struct i2c_periph *periph) {
1323  uint32_t i2c = (uint32_t) periph->reg_addr;
1324 
1325  if (periph->watchdog > WD_DELAY) {
1326  if (periph->watchdog == WD_DELAY + 1) {
1327 
1328  i2c_disable_interrupt(i2c, I2C_CR2_ITEVTEN);
1329  i2c_disable_interrupt(i2c, I2C_CR2_ITERREN);
1330 
1331  i2c_peripheral_disable(i2c);
1332 
1333 #if USE_I2C1
1334  if (i2c == I2C1) {
1337  }
1338 #endif
1339 #if USE_I2C2
1340  if (i2c == I2C2) {
1343  }
1344 #endif
1345 #if USE_I2C3
1346  if (i2c == I2C3) {
1349  }
1350 #endif
1351 
1352  i2c_scl_clear(i2c);
1353  }
1354  else if (periph->watchdog < WD_DELAY + WD_RECOVERY_TICKS) {
1355  if ((periph->watchdog - WD_DELAY) % 2)
1356  i2c_scl_clear(i2c);
1357  else
1358  i2c_scl_set(i2c);
1359  }
1360  else {
1361  i2c_scl_set(i2c);
1362 
1363  /* setup gpios for normal i2c operation again */
1364  i2c_setup_gpio(i2c);
1365 
1366  periph->trans_insert_idx = 0;
1367  periph->trans_extract_idx = 0;
1368  periph->status = I2CIdle;
1369 
1370  i2c_enable_interrupt(i2c, I2C_CR2_ITEVTEN);
1371  i2c_enable_interrupt(i2c, I2C_CR2_ITERREN);
1372 
1373  i2c_peripheral_enable(i2c);
1374  periph->watchdog = 0; // restart watchdog
1375 
1376  periph->errors->timeout_tlow_cnt++;
1377 
1378  return;
1379  }
1380  }
1381  if (periph->watchdog >= 0)
1382  periph->watchdog++;
1383 }
1384 #endif // USE_I2Cx
1385 
1386 #include "mcu_periph/sys_time.h"
1387 
1388 void i2c_event(void) {
1389  static uint32_t i2c_wd_timer;
1390 
1391  if (SysTimeTimer(i2c_wd_timer) > 2000) { // 2ms (500Hz) periodic watchdog check
1392  SysTimeTimerStart(i2c_wd_timer);
1393 #if USE_I2C1
1394  i2c_wd_check(&i2c1);
1395 #endif
1396 
1397 #if USE_I2C2
1398  i2c_wd_check(&i2c2);
1399 #endif
1400 #if USE_I2C3
1401  i2c_wd_check(&i2c3);
1402 #endif
1403  }
1404 }
1405 
1407 // Implement Interface Functions
1408 
1409 bool_t i2c_submit(struct i2c_periph* periph, struct i2c_transaction* t) {
1410 
1411  uint8_t temp;
1412  temp = periph->trans_insert_idx + 1;
1413  if (temp >= I2C_TRANSACTION_QUEUE_LEN) temp = 0;
1414  if (temp == periph->trans_extract_idx) {
1415  // queue full
1416  periph->errors->queue_full_cnt++;
1417  t->status = I2CTransFailed;
1418  return FALSE;
1419  }
1420 
1421  t->status = I2CTransPending;
1422 
1423  __disable_irq();
1424  /* put transacation in queue */
1425  periph->trans[periph->trans_insert_idx] = t;
1426  periph->trans_insert_idx = temp;
1427 
1428  /* if peripheral is idle, start the transaction */
1429  // if (PPRZ_I2C_IS_IDLE(p))
1430  if (periph->status == I2CIdle)
1431  {
1432  //if (i2c_idle(periph))
1433  {
1434 #ifdef I2C_DEBUG_LED
1435 #if USE_I2C1
1436  if (periph == &i2c1)
1437  {
1438 
1439  }
1440  else
1441 #endif
1442 #endif
1443  {
1444 #ifdef I2C_DEBUG_LED
1445  LED2_ON();
1446  LED2_OFF();
1447 #endif
1448  PPRZ_I2C_SEND_START(periph);
1449  }
1450  }
1451  }
1452  /* else it will be started by the interrupt handler when the previous transactions completes */
1453  __enable_irq();
1454 
1455  return TRUE;
1456 }
1457 
1458 bool_t i2c_idle(struct i2c_periph* periph)
1459 {
1460  // This is actually a difficult function:
1461  // -simply reading the status flags can clear bits and corrupt the transaction
1462 
1463  uint32_t i2c = (uint32_t) periph->reg_addr;
1464 
1465 #ifdef I2C_DEBUG_LED
1466 #if USE_I2C1
1467  if (periph == &i2c1)
1468  {
1469  return TRUE;
1470  }
1471 #endif
1472 #endif
1473 
1474  // First we check if the software thinks it is ready
1475  if (periph->status == I2CIdle)
1476  return ! (BIT_X_IS_SET_IN_REG( I2C_SR2_BUSY, I2C_SR2(i2c) ) );
1477  else
1478  return FALSE;
1479 }
static void LED2_OFF(void)
Definition: debug_led.h:18
unsigned short uint16_t
Definition: types.h:16
#define I2C_TRANSACTION_QUEUE_LEN
I2C transaction queue length.
Definition: i2c.h:133
#define I2C3_GPIO_SCL
Definition: krooz_sd.h:134
#define I2C3_GPIO_PORT_SCL
Definition: krooz_sd.h:132
bool_t i2c_submit(struct i2c_periph *p, struct i2c_transaction *t)
Submit a I2C transaction.
Definition: i2c_arch.c:335
#define I2C1
Definition: LPC21xx.h:166
#define NVIC_I2C2_ER_IRQ
static void __enable_irq(void)
Definition: i2c_arch.c:66
volatile uint16_t queue_full_cnt
Definition: i2c.h:155
transaction successfully finished by I2C driver
Definition: i2c.h:57
I2C transaction structure.
Definition: i2c.h:93
void * reg_addr
Definition: i2c.h:146
uint8_t trans_extract_idx
Definition: i2c.h:142
volatile uint16_t ack_fail_cnt
Definition: i2c.h:156
static void i2c_irq(struct i2c_periph *periph)
Definition: i2c_arch.c:662
#define I2C3_GPIO_SDA
Definition: krooz_sd.h:135
Some architecture independent helper functions for GPIOs.
transmit and receive transaction
Definition: i2c.h:49
void gpio_set(uint32_t port, uint16_t pin)
Set a gpio output to high level.
CM3_WEAK i2c2_ev_isr(void)
#define I2C1_GPIO_SDA
Definition: apogee_0.99.h:122
#define NVIC_I2C3_EV_IRQ
static void __disable_irq(void)
Definition: i2c_arch.c:65
Definition: i2c.h:66
#define GPIOB
Definition: gpio_arch.h:35
CM3_WEAK i2c3_ev_isr(void)
#define BIT_X_IS_SET_IN_REG(X, REG)
Definition: i2c_arch.c:61
void i2c_setbitrate(struct i2c_periph *p, int bitrate)
Set I2C bitrate.
Definition: i2c_arch.c:370
#define __I2C_REG_CRITICAL_ZONE_STOP
Definition: i2c_arch.c:71
static enum STMI2CSubTransactionStatus stmi2c_readmany(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
Definition: i2c_arch.c:437
static void LED1_ON(void)
Definition: debug_led.h:3
if(PrimarySpektrumState.SpektrumTimer)--PrimarySpektrumState.SpektrumTimer
volatile uint8_t idx_buf
Definition: i2c.h:145
#define I2C3_GPIO_PORT_SDA
Definition: krooz_sd.h:133
enum I2CStatus status
Definition: i2c.h:144
uint8_t slave_addr
Slave address.
Definition: i2c.h:104
#define FALSE
Definition: imu_chimu.h:141
static void LED_SHOW_ACTIVE_BITS(I2C_TypeDef *regs)
Definition: debug_led.h:48
volatile uint16_t smbus_alert_cnt
Definition: i2c.h:162
static void LED2_ON(void)
Definition: debug_led.h:13
#define I2C2_GPIO_SCL
Definition: apogee_0.99.h:125
volatile uint16_t timeout_tlow_cnt
Definition: i2c.h:161
#define __I2C_REG_CRITICAL_ZONE_START
Definition: i2c_arch.c:70
#define I2C_SR1_ERR_MASK
Definition: i2c_arch.c:51
#define NVIC_I2C1_IRQ_PRIO
Definition: i2c_arch.c:75
static void LED_ERROR(uint8_t base, uint8_t nr)
Definition: debug_led.h:37
CM3_WEAK i2c3_er_isr(void)
#define ZEROS_ERR_COUNTER(_i2c_err)
Definition: i2c.h:179
#define I2C1_GPIO_PORT
Definition: apogee_0.99.h:120
volatile uint16_t miss_start_stop_cnt
Definition: i2c.h:157
static enum STMI2CSubTransactionStatus stmi2c_read2(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
Definition: i2c_arch.c:367
Architecture independent timing functions.
static void i2c_error(struct i2c_periph *periph)
Definition: i2c_arch.c:558
CM3_WEAK i2c1_er_isr(void)
unsigned long uint32_t
Definition: types.h:18
CM3_WEAK i2c2_er_isr(void)
volatile uint16_t unexpected_event_cnt
Definition: i2c.h:163
transaction failed
Definition: i2c.h:58
Definition: i2c.h:77
I2C errors counter.
Definition: i2c.h:154
enum I2CTransactionStatus status
Transaction status.
Definition: i2c.h:126
static enum STMI2CSubTransactionStatus stmi2c_read1(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
Definition: i2c_arch.c:304
volatile uint16_t over_under_cnt
Definition: i2c.h:159
volatile uint16_t pec_recep_cnt
Definition: i2c.h:160
#define SysTimeTimer(_t)
Definition: sys_time.h:199
void gpio_clear(uint32_t port, uint16_t pin)
Clear a gpio output to low level.
#define NVIC_I2C2_IRQ_PRIO
Definition: i2c_arch.c:76
#define NVIC_I2C2_EV_IRQ
#define I2C1_GPIO_SCL
Definition: apogee_0.99.h:121
#define TRUE
Definition: imu_chimu.h:144
volatile uint32_t er_irq_cnt
Definition: i2c.h:165
volatile uint8_t buf[I2C_BUF_LEN]
Transaction buffer With I2C_BUF_LEN number of bytes.
Definition: i2c.h:122
uint8_t len_w
Number of bytes to write/transmit.
Definition: i2c.h:116
uint16_t len_r
Number of bytes to read/receive.
Definition: i2c.h:110
#define NVIC_I2C1_ER_IRQ
unsigned char uint8_t
Definition: types.h:14
STMI2CSubTransactionStatus
Definition: i2c_arch.c:214
static void gpio_setup_output(uint32_t port, uint32_t gpios)
Setup one or more pins of the given GPIO port as outputs.
Definition: gpio_arch.h:76
#define NVIC_I2C3_IRQ_PRIO
Definition: i2c_arch.c:77
volatile uint16_t arb_lost_cnt
Definition: i2c.h:158
uint8_t trans_insert_idx
Definition: i2c.h:141
#define LED_INIT(i)
Definition: led_hw.h:26
struct i2c_errors * errors
Definition: i2c.h:148
I2C peripheral structure.
Definition: i2c.h:138
#define I2C2_GPIO_PORT
Definition: apogee_0.99.h:124
transmit only transaction
Definition: i2c.h:47
enum I2CTransactionType type
Transaction type.
Definition: i2c.h:98
static enum STMI2CSubTransactionStatus stmi2c_send(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
Definition: i2c_arch.c:223
#define NVIC_I2C3_ER_IRQ
void gpio_enable_clock(uint32_t port)
Enable the relevant clock.
Definition: gpio_arch.c:34
static void LED1_OFF(void)
Definition: debug_led.h:8
void i2c_event(void)
Definition: i2c_arch.c:368
#define SysTimeTimerStart(_t)
Definition: sys_time.h:198
static void PPRZ_I2C_SEND_START(struct i2c_periph *periph)
Definition: i2c_arch.c:171
static void gpio_setup_input(uint32_t port, uint32_t gpios)
Setup one or more pins of the given GPIO port as inputs.
Definition: gpio_arch.h:88
receive only transaction
Definition: i2c.h:48
bool_t i2c_idle(struct i2c_periph *p)
Check if I2C bus is idle.
Definition: i2c_arch.c:331
volatile uint32_t last_unexpected_event
Definition: i2c.h:164
transaction is pending in queue
Definition: i2c.h:55
static void stmi2c_clear_pending_interrupts(uint32_t i2c)
Definition: i2c_arch.c:622
#define NVIC_I2C1_EV_IRQ
static void PPRZ_I2C_SEND_STOP(uint32_t i2c)
Definition: i2c_arch.c:156
CM3_WEAK i2c1_ev_isr(void)
struct i2c_transaction * trans[I2C_TRANSACTION_QUEUE_LEN]
Definition: i2c.h:140
volatile int16_t watchdog
Definition: i2c.h:149
#define I2C2_GPIO_SDA
Definition: apogee_0.99.h:126
Architecture independent I2C (Inter-Integrated Circuit Bus) API.