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adc_arch.c
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2  * Copyright (C) 2010-2013 The Paparazzi Team
3  *
4  * This file is part of paparazzi.
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6  * paparazzi is free software; you can redistribute it and/or modify
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14  * GNU General Public License for more details.
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20  */
41 /*
42  For better understanding of timer and GPIO settings:
43 
44  Table of GPIO pins available per ADC:
45 
46  ADC1/2: ADC3:
47  C0 -> PA0 C0 -> PA0
48  C1 -> PA1 C1 -> PA1
49  C2 -> PA2 C2 -> PA2
50  C3 -> PA3 C3 -> PA3
51  C4 -> PA4 C4 -> PF6
52  C5 -> PA5 C5 -> PF7
53  C6 -> PA6 C6 -> PF8
54  C7 -> PA7 C7 -> PF9
55  C8 -> PB0 C8 -> PF10
56  C9 -> PB1
57  C10 -> PC0 C10 -> PC0
58  C11 -> PC1 C11 -> PC1
59  C12 -> PC2 C12 -> PC2
60  C13 -> PC3 C13 -> PC3
61  C14 -> PC4
62  C15 -> PC5
63 
64  Table of timers available per ADC (from libstm/src/stm32_adc.c):
65 
66  T1_TRGO: Timer1 TRGO event (ADC1, ADC2 and ADC3)
67  T1_CC4: Timer1 capture compare4 (ADC1, ADC2 and ADC3)
68  T2_TRGO: Timer2 TRGO event (ADC1 and ADC2)
69  T2_CC1: Timer2 capture compare1 (ADC1 and ADC2)
70  T3_CC4: Timer3 capture compare4 (ADC1 and ADC2)
71  T4_TRGO: Timer4 TRGO event (ADC1 and ADC2)
72  TIM8_CC4: External interrupt line 15 or Timer8 capture compare4 event (ADC1 and ADC2)
73  T4_CC3: Timer4 capture compare3 (ADC3 only)
74  T8_CC2: Timer8 capture compare2 (ADC3 only)
75  T8_CC4: Timer8 capture compare4 (ADC3 only)
76  T5_TRGO: Timer5 TRGO event (ADC3 only)
77  T5_CC4: Timer5 capture compare4 (ADC3 only)
78 
79  By setting ADC_ExternalTrigInjecConv_None, injected conversion
80  is started by software instead of external trigger for any ADC.
81 
82  Table of APB per Timer (from libstm/src/stm32_tim.c):
83 
84  RCC_APB1: TIM2, TIM3, TIM4, TIM5, TIM7 (non-advanced timers)
85  RCC_APB2: TIM1, TIM8 (advanced timers)
86 
87 */
88 
89 #include "mcu_periph/adc.h"
90 
91 #include <libopencm3/stm32/rcc.h>
92 #include <libopencm3/stm32/gpio.h>
93 #include <libopencm3/stm32/adc.h>
94 #include <libopencm3/cm3/nvic.h>
95 #include <libopencm3/stm32/timer.h>
96 #include <string.h>
97 #include "mcu_periph/gpio.h"
98 #include "mcu_arch.h"
99 #include "std.h"
100 #include BOARD_CONFIG
101 
102 
103 #ifndef NVIC_ADC_IRQ_PRIO
104 #define NVIC_ADC_IRQ_PRIO 0
105 #endif
106 
107 #if defined(STM32F1)
108 #define ADC_SAMPLE_TIME ADC_SMPR_SMP_41DOT5CYC
109 #elif defined(STM32F4)
110 #define ADC_SAMPLE_TIME ADC_SMPR_SMP_56CYC
111 #endif
112 
113 // Macros to automatically enable the correct ADC
114 
115 #if defined(AD1_1_CHANNEL) || defined(AD1_2_CHANNEL) || defined(AD1_3_CHANNEL) || defined(AD1_4_CHANNEL)
116 #ifndef USE_AD1
117 #define USE_AD1 1
118 #endif
119 #endif
120 
121 #if defined(AD2_1_CHANNEL) || defined(AD2_2_CHANNEL) || defined(AD2_3_CHANNEL) || defined(AD2_4_CHANNEL)
122 #ifndef USE_AD2
123 #define USE_AD2 1
124 #endif
125 #endif
126 
127 #if defined(STM32F4)
128 
129 #if defined(AD3_1_CHANNEL) || defined(AD3_2_CHANNEL) || defined(AD3_3_CHANNEL) || defined(AD3_4_CHANNEL)
130 #ifndef USE_AD3
131 #define USE_AD3 1
132 #endif
133 #endif
134 
135 #else // !STM32F4
136 // ADC 3 not supported on STM32F1
137 #undef USE_AD3
138 #define USE_AD3 0
139 #endif
140 
141 #if USE_AD1
142 PRINT_CONFIG_MSG("Analog to Digital Coverter 1 active")
143 #endif
144 #if USE_AD2
145 PRINT_CONFIG_MSG("Analog to Digital Coverter 2 active")
146 #endif
147 #if USE_AD3
148 PRINT_CONFIG_MSG("Analog to Digital Coverter 3 active")
149 #endif
150 #if !USE_AD1 && !USE_AD2 && !USE_AD3
151 #warning ALL ADC CONVERTERS INACTIVE
152 #endif
153 
154 #ifndef ADC_TIMER_PERIOD
155 #define ADC_TIMER_PERIOD 10000
156 #endif
157 
163 #ifndef ADC_TIMER_FREQUENCY
164 #define ADC_TIMER_FREQUENCY 2000000
165 #endif
166 
167 /***************************************/
168 /*** STATIC FUNCTION PROTOTYPES ***/
169 /***************************************/
170 
171 static inline void adc_init_single(uint32_t adc, uint8_t nb_channels, uint8_t* channel_map);
172 
173 static inline void adc_push_sample(struct adc_buf * buf,
174  uint16_t sample);
175 
176 static inline void adc_init_rcc( void );
177 static inline void adc_init_irq( void );
178 
179 
180 /********************************/
181 /*** GLOBAL VARIABLES ***/
182 /********************************/
183 
184 /* Only 4 ADC channels may be enabled at the same time
185  * on each ADC, as there are only 4 injection registers.
186  * Currently, the enums adc1_channels and adc2_channels only
187  * serve to resolve the number of channels on each ADC.
188  * There are 3 separate buffer lists, each holds the addresses of the actual adc buffers
189  * for the particular adc converter.
190  */
191 
195 
196 #if USE_AD1
197 static struct adc_buf * adc1_buffers[4];
199 #endif
200 #if USE_AD2
201 static struct adc_buf * adc2_buffers[4];
203 #endif
204 #if USE_AD3
205 static struct adc_buf * adc3_buffers[4];
207 #endif
208 
209 #if USE_ADC_WATCHDOG
210 #include "mcu_periph/sys_time.h"
211 // watchdog structure with adc bank and callback
212 static struct {
213  uint32_t timeStamp;
214  uint32_t adc;
215  adc_watchdog_callback cb;
216 } adc_watchdog;
217 #endif
218 
219 /***************************************/
220 /*** PUBLIC FUNCTION DEFINITIONS ***/
221 /***************************************/
222 
223 void adc_init( void ) {
224 
225  uint8_t x=0;
226 
227  // ADC channel mapping
228  uint8_t adc_channel_map[4];
229 
230  /* Init GPIO ports for ADC operation
231  */
232 #if USE_ADC_1
233  PRINT_CONFIG_MSG("Info: Using ADC_1");
235 #endif
236 #if USE_ADC_2
237  PRINT_CONFIG_MSG("Info: Using ADC_2");
239 #endif
240 #if USE_ADC_3
241  PRINT_CONFIG_MSG("Info: Using ADC_3");
243 #endif
244 #if USE_ADC_4
245  PRINT_CONFIG_MSG("Info: Using ADC_4");
247 #endif
248 #if USE_ADC_5
249  PRINT_CONFIG_MSG("Info: Using ADC_5");
251 #endif
252 #if USE_ADC_6
253  PRINT_CONFIG_MSG("Info: Using ADC_6");
255 #endif
256 #if USE_ADC_7
257  PRINT_CONFIG_MSG("Info: Using ADC_7");
258  gpio_setup_pin_analog(ADC_7_GPIO_PORT, ADC_7_GPIO_PIN);
259 #endif
260 #if USE_ADC_8
261  PRINT_CONFIG_MSG("Info: Using ADC_8");
262  gpio_setup_pin_analog(ADC_8_GPIO_PORT, ADC_8_GPIO_PIN);
263 #endif
264 #if USE_ADC_9
265  PRINT_CONFIG_MSG("Info: Using ADC_9");
266  gpio_setup_pin_analog(ADC_9_GPIO_PORT, ADC_9_GPIO_PIN);
267 #endif
268 
269  // Init clock and irq
270  adc_init_rcc();
271  adc_init_irq();
272 
273  /* If fewer than 4 channels are active, say 3, then they are placed in to
274  * injection slots 2,3 and 4 because the stm32 architecture converts injected
275  * slots 2,3 and 4 and skips slot 1 instead of logicaly converting slots 1,2
276  * and 3 and leave slot 4.
277  * EXAMPLE OF ADC EXECUTION ORDER WHEN WE HAVE SAY 2 ADC INPUTS USED on ADC1
278  * The first board adc channel ADC1_1 is mapped to injected channel 3 and ADC1_2
279  * to injected channel 4 and because the conversions start from the lowest
280  * injection channel used, 3 in our case, injected channel 3 data will be
281  * located at JDR1 and 4 to JDR2 so JDR1 = ADC1_1 and JDR2 = ADC1_2.
282  * That's why "adc_channel_map" has this descending order.
283  */
284 
285  nb_adc1_channels = 0;
286 #if USE_AD1
287 #ifdef AD1_1_CHANNEL
288  adc_channel_map[AD1_1] = AD1_1_CHANNEL;
289  nb_adc1_channels++;
290 #endif
291 #ifdef AD1_2_CHANNEL
292  adc_channel_map[AD1_2] = AD1_2_CHANNEL;
293  nb_adc1_channels++;
294 #endif
295 #ifdef AD1_3_CHANNEL
296  adc_channel_map[AD1_3] = AD1_3_CHANNEL;
297  nb_adc1_channels++;
298 #endif
299 #ifdef AD1_4_CHANNEL
300  adc_channel_map[AD1_4] = AD1_4_CHANNEL;
301  nb_adc1_channels++;
302 #endif
303  // initialize buffer pointers with 0 (not set). Buffer null pointers will be ignored in interrupt
304  // handler, which is important as there are no buffers registered at the time the ADC trigger
305  // interrupt is enabled.
306  for (x = 0; x < 4; x++) { adc1_buffers[x] = NULL; }
307  adc_init_single(ADC1, nb_adc1_channels, adc_channel_map);
308 #endif // USE_AD1
309 
310 
311  nb_adc2_channels = 0;
312 #if USE_AD2
313 #ifdef AD2_1_CHANNEL
314  adc_channel_map[AD2_1 - nb_adc1_channels] = AD2_1_CHANNEL;
315  nb_adc2_channels++;
316 #endif
317 #ifdef AD2_2_CHANNEL
318  adc_channel_map[AD2_2 - nb_adc1_channels] = AD2_2_CHANNEL;
319  nb_adc2_channels++;
320 #endif
321 #ifdef AD2_3_CHANNEL
322  adc_channel_map[AD2_3 - nb_adc1_channels] = AD2_3_CHANNEL;
323  nb_adc2_channels++;
324 #endif
325 #ifdef AD2_4_CHANNEL
326  adc_channel_map[AD2_4 - nb_adc1_channels] = AD2_4_CHANNEL;
327  nb_adc2_channels++;
328 #endif
329  // initialize buffer pointers with 0 (not set). Buffer null pointers will be ignored in interrupt
330  // handler, which is important as there are no buffers registered at the time the ADC trigger
331  // interrupt is enabled.
332  for (x = 0; x < 4; x++) { adc2_buffers[x] = NULL; }
333  adc_init_single(ADC2, nb_adc2_channels, adc_channel_map);
334 #endif // USE_AD2
335 
336 
337  nb_adc3_channels = 0;
338 #if USE_AD3
339 #ifdef AD3_1_CHANNEL
340  adc_channel_map[AD3_1 - nb_adc1_channels - nb_adc2_channels] = AD3_1_CHANNEL;
341  nb_adc3_channels++;
342 #endif
343 #ifdef AD3_2_CHANNEL
344  adc_channel_map[AD3_2 - nb_adc1_channels - nb_adc2_channels] = AD3_2_CHANNEL;
345  nb_adc3_channels++;
346 #endif
347 #ifdef AD3_3_CHANNEL
348  adc_channel_map[AD3_3 - nb_adc1_channels - nb_adc2_channels] = AD3_3_CHANNEL;
349  nb_adc3_channels++;
350 #endif
351 #ifdef AD3_4_CHANNEL
352  adc_channel_map[AD3_4 - nb_adc1_channels - nb_adc2_channels] = AD3_4_CHANNEL;
353  nb_adc3_channels++;
354 #endif
355  // initialize buffer pointers with 0 (not set). Buffer null pointers will be ignored in interrupt
356  // handler, which is important as there are no buffers registered at the time the ADC trigger
357  // interrupt is enabled.
358  for (x = 0; x < 4; x++) { adc3_buffers[x] = NULL; }
359  adc_init_single(ADC3, nb_adc3_channels, adc_channel_map);
360 #endif // USE_AD3
361 
362 #if USE_ADC_WATCHDOG
363  adc_watchdog.cb = NULL;
364  adc_watchdog.timeStamp=0;
365 #endif
366 
367 }
368 
369 void adc_buf_channel(uint8_t adc_channel, struct adc_buf * s, uint8_t av_nb_sample)
370 {
371 
372  if (adc_channel < nb_adc1_channels) {
373 #if USE_AD1
374  adc1_buffers[adc_channel] = s;
375 #endif
376  }
377  else if (adc_channel < (nb_adc1_channels+nb_adc2_channels)) {
378 #if USE_AD2
379  adc2_buffers[adc_channel-nb_adc1_channels] = s;
380 #endif
381  }
382  else if (adc_channel < (nb_adc1_channels+nb_adc2_channels+nb_adc3_channels)) {
383 #if USE_AD3
384  adc3_buffers[adc_channel-(nb_adc1_channels+nb_adc2_channels)] = s;
385 #endif
386  }
387 
388  s->av_nb_sample = av_nb_sample;
389 
390 }
391 
392 #if USE_ADC_WATCHDOG
393 void register_adc_watchdog(uint32_t adc, uint8_t chan, uint16_t low, uint16_t high, adc_watchdog_callback cb) {
394  adc_watchdog.adc = adc;
395  adc_watchdog.cb = cb;
396 
397  // activated adc watchdog of a single injected channel with interrupt
398  adc_set_watchdog_low_threshold(adc, low);
399  adc_set_watchdog_high_threshold(adc, high);
400  adc_enable_analog_watchdog_injected(adc);
401  adc_enable_analog_watchdog_on_selected_channel(adc, chan);
402  adc_enable_awd_interrupt(adc);
403 }
404 #endif
405 
406 /**************************************/
407 /*** PRIVATE FUNCTION DEFINITIONS ***/
408 /**************************************/
409 
410 #if defined(USE_AD_TIM4)
411 #define TIM_ADC TIM4
412 #define RCC_TIM_ADC RCC_TIM4
413 #elif defined(USE_AD_TIM1)
414 #define TIM_ADC TIM1
415 #define RCC_TIM_ADC RCC_TIM1
416 #else
417 #define TIM_ADC TIM2
418 #define RCC_TIM_ADC RCC_TIM2
419 #endif
420 
422 static inline void adc_init_rcc( void )
423 {
424 #if USE_AD1 || USE_AD2 || USE_AD3
425  /* Timer peripheral clock enable. */
426  rcc_periph_clock_enable(RCC_TIM_ADC);
427 #if defined(STM32F4)
428  adc_set_clk_prescale(ADC_CCR_ADCPRE_BY2);
429 #endif
430 
431  /* Enable ADC peripheral clocks. */
432 #if USE_AD1
433  rcc_periph_clock_enable(RCC_ADC1);
434 #endif
435 #if USE_AD2
436  rcc_periph_clock_enable(RCC_ADC2);
437 #endif
438 #if USE_AD3
439  rcc_periph_clock_enable(RCC_ADC3);
440 #endif
441 
442  /* Time Base configuration */
443  timer_reset(TIM_ADC);
444  timer_set_mode(TIM_ADC, TIM_CR1_CKD_CK_INT,
445  TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
446  /* timer counts with ADC_TIMER_FREQUENCY */
447  uint32_t timer_clk = timer_get_frequency(TIM_ADC);
448  timer_set_prescaler(TIM_ADC, (timer_clk / ADC_TIMER_FREQUENCY) - 1);
449 
450  timer_set_period(TIM_ADC, ADC_TIMER_PERIOD);
451  /* Generate TRGO on every update (when counter reaches period reload value) */
452  timer_set_master_mode(TIM_ADC, TIM_CR2_MMS_UPDATE);
453  timer_enable_counter(TIM_ADC);
454 
455 #endif // USE_AD1 || USE_AD2 || USE_AD3
456 }
457 
459 static inline void adc_init_irq( void )
460 {
461 #if defined(STM32F1)
462  nvic_set_priority(NVIC_ADC1_2_IRQ, NVIC_ADC_IRQ_PRIO);
463  nvic_enable_irq(NVIC_ADC1_2_IRQ);
464 #elif defined(STM32F4)
465  nvic_set_priority(NVIC_ADC_IRQ, NVIC_ADC_IRQ_PRIO);
466  nvic_enable_irq(NVIC_ADC_IRQ);
467 #endif
468 }
469 
470 
471 static inline void adc_init_single(uint32_t adc, uint8_t nb_channels, uint8_t* channel_map)
472 {
473  // Paranoia, must be down for 2+ ADC clock cycles before calibration
474  adc_off(adc);
475 
476  /* Configure ADC */
477  /* Explicitly setting most registers, reset/default values are correct for most */
478  /* Set CR1 register. */
479  /* Clear AWDEN */
480  adc_disable_analog_watchdog_regular(adc);
481  /* Clear JAWDEN */
482  adc_disable_analog_watchdog_injected(adc);
483  /* Clear DISCEN */
484  adc_disable_discontinuous_mode_regular(adc);
485  /* Clear JDISCEN */
486  adc_disable_discontinuous_mode_injected(adc);
487  /* Clear JAUTO */
488  adc_disable_automatic_injected_group_conversion(adc);
489  /* Set SCAN */
490  adc_enable_scan_mode(adc);
491  /* Enable ADC<X> JEOC interrupt (Set JEOCIE) */
492  adc_enable_eoc_interrupt_injected(adc);
493  /* Clear AWDIE */
494  adc_disable_awd_interrupt(adc);
495  /* Clear EOCIE */
496  adc_disable_eoc_interrupt(adc);
497 
498  /* Set CR2 register. */
499  /* Clear TSVREFE */
500 #if defined(STM32F1)
501  adc_disable_temperature_sensor(adc);
502 #elif defined(STM32F4)
503  adc_disable_temperature_sensor();
504 #endif
505  /* Clear EXTTRIG */
506  adc_disable_external_trigger_regular(adc);
507  /* Clear ALIGN */
508  adc_set_right_aligned(adc);
509  /* Clear DMA */
510  adc_disable_dma(adc);
511  /* Clear CONT */
512  adc_set_single_conversion_mode(adc);
513 
514  //uint8_t x = 0;
515  //for (x = 0; x < nb_channels; x++) {
516  // adc_set_sample_time(adc, channel_map[x], ADC_SAMPLE_TIME);
517  //}
518  adc_set_sample_time_on_all_channels(adc, ADC_SAMPLE_TIME);
519 
520  adc_set_injected_sequence(adc, nb_channels, channel_map);
521 
522 #if USE_AD_TIM4
523  PRINT_CONFIG_MSG("Info: Using TIM4 for ADC")
524 #if defined(STM32F1)
525  adc_enable_external_trigger_injected(adc, ADC_CR2_JEXTSEL_TIM4_TRGO);
526 #elif defined(STM32F4)
527  adc_enable_external_trigger_injected(adc, ADC_CR2_JEXTSEL_TIM4_TRGO, ADC_CR2_JEXTEN_BOTH_EDGES);
528 #endif
529 #elif USE_AD_TIM1
530  PRINT_CONFIG_MSG("Info: Using TIM1 for ADC")
531 #if defined(STM32F1)
532  adc_enable_external_trigger_injected(adc, ADC_CR2_JEXTSEL_TIM1_TRGO);
533 #elif defined(STM32F4)
534  adc_enable_external_trigger_injected(adc, ADC_CR2_JEXTSEL_TIM1_TRGO, ADC_CR2_JEXTEN_BOTH_EDGES);
535 #endif
536 #else
537  PRINT_CONFIG_MSG("Info: Using default TIM2 for ADC")
538 #if defined(STM32F1)
539  adc_enable_external_trigger_injected(adc, ADC_CR2_JEXTSEL_TIM2_TRGO);
540 #elif defined(STM32F4)
541  adc_enable_external_trigger_injected(adc, ADC_CR2_JEXTSEL_TIM2_TRGO, ADC_CR2_JEXTEN_BOTH_EDGES);
542 #endif
543 #endif
544 
545  /* Enable ADC<X> */
546  adc_power_on(adc);
547 #if defined(STM32F1)
548  /* Enable ADC<X> reset calibaration register */
549  adc_reset_calibration(adc);
550  /* Check the end of ADC<X> reset calibration */
551  while ((ADC_CR2(adc) & ADC_CR2_RSTCAL) != 0);
552  /* Start ADC<X> calibaration */
553  adc_calibration(adc);
554  /* Check the end of ADC<X> calibration */
555  while ((ADC_CR2(adc) & ADC_CR2_CAL) != 0);
556 #endif
557 
558  return;
559 } // adc_init_single
560 
561 
562 static inline void adc_push_sample(struct adc_buf * buf, uint16_t value) {
563  uint8_t new_head = buf->head + 1;
564 
565  if (new_head >= buf->av_nb_sample) {
566  new_head = 0;
567  }
568  buf->sum -= buf->values[new_head];
569  buf->values[new_head] = value;
570  buf->sum += value;
571  buf->head = new_head;
572 }
573 
574 /*********************************/
575 /*** ADC INTERRUPT HANDLER ***/
576 /*********************************/
577 
578 #if defined(STM32F1)
579 void adc1_2_isr(void)
580 #elif defined(STM32F4)
581 void adc_isr(void)
582 #endif
583 {
584  uint8_t channel = 0;
586  struct adc_buf * buf;
587 
588 #if USE_ADC_WATCHDOG
589  /*
590  We need adc sampling fast enough to detect battery plug out, but we did not
591  need to get actual actual value so fast. So timer fire adc conversion fast,
592  at least 500 hz, but we inject adc value in sampling buffer only at 50hz
593  */
594  const uint32_t timeStampDiff = get_sys_time_msec() - adc_watchdog.timeStamp;
595  const bool_t shouldAccumulateValue = timeStampDiff > 20;
596  if (shouldAccumulateValue)
597  adc_watchdog.timeStamp = get_sys_time_msec();
598 
599  if (adc_watchdog.cb != NULL) {
600  if (adc_awd(adc_watchdog.adc)) {
601  ADC_SR(adc_watchdog.adc) &= ~ADC_SR_AWD; // clear int flag
602  adc_watchdog.cb();
603  }
604  }
605 #endif
606 
607 #if USE_AD1
608  // Clear Injected End Of Conversion
609  if (adc_eoc_injected(ADC1)){
610  ADC_SR(ADC1) &= ~ADC_SR_JEOC;
611 #if USE_ADC_WATCHDOG
612  if (shouldAccumulateValue) {
613 #endif
614  for (channel = 0; channel < nb_adc1_channels; channel++) {
615  buf = adc1_buffers[channel];
616  if (buf) {
617  value = adc_read_injected(ADC1, channel+1);
618  adc_push_sample(buf, value);
619  }
620  }
621 #if USE_ADC_WATCHDOG
622  }
623 #endif
624  }
625 #endif // USE_AD1
626 
627 #if USE_AD2
628  if (adc_eoc_injected(ADC2)){
629  ADC_SR(ADC2) &= ~ADC_SR_JEOC;
630 #if USE_ADC_WATCHDOG
631  if (shouldAccumulateValue) {
632 #endif
633  for (channel = 0; channel < nb_adc2_channels; channel++) {
634  buf = adc2_buffers[channel];
635  if (buf) {
636  value = adc_read_injected(ADC2, channel+1);
637  adc_push_sample(buf, value);
638  }
639  }
640 #if USE_ADC_WATCHDOG
641  }
642 #endif
643  }
644 #endif // USE_AD2
645 
646 #if USE_AD3
647  if (adc_eoc_injected(ADC3)){
648  ADC_SR(ADC3) &= ~ADC_SR_JEOC;
649 #if USE_ADC_WATCHDOG
650  if (shouldAccumulateValue) {
651 #endif
652  for (channel = 0; channel < nb_adc3_channels; channel++) {
653  buf = adc3_buffers[channel];
654  if (buf) {
655  value = adc_read_injected(ADC3, channel+1);
656  adc_push_sample(buf, value);
657  }
658  }
659 #if USE_ADC_WATCHDOG
660  }
661 #endif
662  }
663 #endif // USE_AD3
664 
665  return;
666 }
#define ADC1
Definition: LPC21xx.h:370
unsigned short uint16_t
Definition: types.h:16
void gpio_setup_pin_analog(uint32_t port, uint16_t pin)
Setup a gpio for analog use.
static void adc_init_single(uint32_t adc, uint8_t nb_channels, uint8_t *channel_map)
Definition: adc_arch.c:471
#define ADC_1_GPIO_PORT
Definition: lisa_s_1.0.h:81
uint16_t value
Definition: adc_arch.c:585
#define AD3_2_CHANNEL
void adc_buf_channel(uint8_t adc_channel, struct adc_buf *s, uint8_t av_nb_sample)
Registers a buffer to be used to store the specified converted channel Usage:
Definition: adc_arch.c:59
Some architecture independent helper functions for GPIOs.
uint16_t values[MAX_AV_NB_SAMPLE]
Definition: adc.h:55
uint32_t timer_get_frequency(uint32_t timer_peripheral)
Get Timer clock frequency (before prescaling) Only valid if using the internal clock for the timer...
Definition: mcu_arch.c:139
#define ADC_6_GPIO_PIN
#define AD1_4_CHANNEL
Definition: apogee_0.99.h:107
uint8_t av_nb_sample
Definition: adc.h:57
arch independent ADC (Analog to Digital Converter) API
uint32_t sum
Definition: adc.h:54
#define ADC_5_GPIO_PORT
static uint8_t nb_adc3_channels
Definition: adc_arch.c:194
#define ADC_3_GPIO_PIN
Definition: lisa_l_1.0.h:151
#define NVIC_ADC_IRQ_PRIO
Definition: adc_arch.c:104
CM3_WEAK adc_isr(void)
static uint8_t nb_adc1_channels
Definition: adc_arch.c:192
Architecture independent timing functions.
#define AD2_2_CHANNEL
static uint32_t get_sys_time_msec(void)
Get the time in milliseconds since startup.
Definition: sys_time_arch.h:75
Generic interface for all ADC hardware drivers, independent from microcontroller architecture.
Definition: adc.h:53
unsigned long uint32_t
Definition: types.h:18
#define ADC_4_GPIO_PIN
Definition: apogee_0.99.h:110
#define ADC_TIMER_FREQUENCY
Timer frequency for ADC Timer will trigger an update event after reaching the period reload value...
Definition: adc_arch.c:164
static void adc_push_sample(struct adc_buf *buf, uint16_t sample)
Definition: adc_arch.c:562
#define ADC_TIMER_PERIOD
Definition: adc_arch.c:155
#define ADC_3_GPIO_PORT
Definition: lisa_l_1.0.h:150
#define AD3_1_CHANNEL
#define ADC_4_GPIO_PORT
Definition: apogee_0.99.h:109
struct adc_buf * buf
Definition: adc_arch.c:586
unsigned char uint8_t
Definition: types.h:14
#define NVIC_ADC_IRQ
#define TIM_ADC
Definition: adc_arch.c:417
void adc_init(void)
Starts conversions.
Definition: adc_arch.c:194
static void adc_init_irq(void)
Configure and enable ADC interrupt.
Definition: adc_arch.c:459
#define AD1_1_CHANNEL
Definition: lisa_s_1.0.h:79
#define AD2_1_CHANNEL
#define ADC_6_GPIO_PORT
static uint8_t nb_adc2_channels
Definition: adc_arch.c:193
static uint8_t channel
Definition: ADS8344.c:80
#define RCC_TIM_ADC
Definition: adc_arch.c:418
uint8_t head
Definition: adc.h:56
#define AD1_3_CHANNEL
Definition: lisa_l_1.0.h:148
#define ADC_5_GPIO_PIN
static void adc_init_rcc(void)
Configure and enable RCC for peripherals (ADC1, ADC2, Timer)
Definition: adc_arch.c:422
#define ADC_1_GPIO_PIN
Definition: lisa_s_1.0.h:82