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sc18is600_arch.c
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1 #include "peripherals/sc18is600.h"
2 
3 #include <stm32/rcc.h>
4 #include <stm32/spi.h>
5 #include <stm32/exti.h>
6 #include <stm32/misc.h>
7 #include <stm32/dma.h>
8 #include <stm32/gpio.h>
9 
10 /* commands definition */
11 #define Sc18Is600_Cmd_Write 0x00
12 #define Sc18Is600_Cmd_Read 0x01
13 #define Sc18Is600_Cmd_Read_After_Write 0x02
14 #define Sc18Is600_Cmd_Write_After_Write 0x03
15 #define Sc18Is600_Cmd_Read_Buffer 0x06
16 #define Sc18Is600_Cmd_Write_To_Reg 0x20
17 #define Sc18Is600_Cmd_Read_From_Reg 0x21
18 #define Sc18Is600_Cmd_Power_Down 0x30
19 
20 extern void exti2_irq_handler(void);
21 extern void dma1_c4_irq_handler(void);
22 
23 static inline void sc18is600_setup_SPI_DMA(uint8_t _len);
24 
25 void sc18is600_arch_init(void) {
26 
27  /* set slave select as output and assert it ( on PB12) */
29  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
30  GPIO_InitTypeDef GPIO_InitStructure;
31  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
32  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
33  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
34  GPIO_Init(GPIOB, &GPIO_InitStructure);
35 
36  /* configure external interrupt exti2 on PD2( data ready ) */
37  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_AFIO, ENABLE);
38  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
39  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
40  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
41  GPIO_Init(GPIOD, &GPIO_InitStructure);
42 
43  EXTI_InitTypeDef EXTI_InitStructure;
44  GPIO_EXTILineConfig(GPIO_PortSourceGPIOD, GPIO_PinSource2);
45  EXTI_InitStructure.EXTI_Line = EXTI_Line2;
46  EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
47  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
48  EXTI_InitStructure.EXTI_LineCmd = ENABLE;
49  EXTI_Init(&EXTI_InitStructure);
50 
51  NVIC_InitTypeDef NVIC_InitStructure;
52  NVIC_InitStructure.NVIC_IRQChannel = EXTI2_IRQn;
53  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
54  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
55  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
56 
57  NVIC_Init(&NVIC_InitStructure);
58 
59  /* Enable DMA1 channel4 IRQ Channel */
60  NVIC_InitTypeDef NVIC_init_struct = {
61  .NVIC_IRQChannel = DMA1_Channel4_IRQn,
62  .NVIC_IRQChannelPreemptionPriority = 0,
63  .NVIC_IRQChannelSubPriority = 0,
64  .NVIC_IRQChannelCmd = ENABLE
65  };
66  NVIC_Init(&NVIC_init_struct);
67  /* Enable SPI2 Periph clock -------------------------------------------------*/
68  RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
69 
70  /* Configure GPIOs: SCK, MISO and MOSI --------------------------------*/
71  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15;
72  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
73  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
74  GPIO_Init(GPIOB, &GPIO_InitStructure);
75 
76  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO , ENABLE);
77 
78 
79  /* configure SPI */
80  SPI_InitTypeDef SPI_InitStructure;
81  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
82  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
83  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
84  SPI_InitStructure.SPI_CPOL = SPI_CPOL_High;
85  SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
86  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
87  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_256;
88  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
89  SPI_InitStructure.SPI_CRCPolynomial = 7;
90  SPI_Init(SPI2, &SPI_InitStructure);
91 
92  /* Enable SPI */
93  SPI_Cmd(SPI2, ENABLE);
94 
95  /* Enable SPI_2 DMA clock ---------------------------------------------------*/
96  RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
97 
98 }
99 
100 static inline void sc18is600_setup_SPI_DMA(uint8_t _len) {
101  /* SPI2_Rx_DMA_Channel configuration ------------------------------------*/
102  DMA_DeInit(DMA1_Channel4);
103  DMA_InitTypeDef DMA_initStructure_4 = {
104  .DMA_PeripheralBaseAddr = (uint32_t)(SPI2_BASE+0x0C),
105  .DMA_MemoryBaseAddr = (uint32_t)sc18is600.priv_rx_buf,
106  .DMA_DIR = DMA_DIR_PeripheralSRC,
107  .DMA_BufferSize = _len,
108  .DMA_PeripheralInc = DMA_PeripheralInc_Disable,
109  .DMA_MemoryInc = DMA_MemoryInc_Enable,
110  .DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte,
111  .DMA_MemoryDataSize = DMA_MemoryDataSize_Byte,
112  .DMA_Mode = DMA_Mode_Normal,
113  .DMA_Priority = DMA_Priority_VeryHigh,
114  .DMA_M2M = DMA_M2M_Disable
115  };
116  DMA_Init(DMA1_Channel4, &DMA_initStructure_4);
117  /* SPI2_Tx_DMA_Channel configuration ------------------------------------*/
118  DMA_DeInit(DMA1_Channel5);
119  DMA_InitTypeDef DMA_initStructure_5 = {
120  .DMA_PeripheralBaseAddr = (uint32_t)(SPI2_BASE+0x0C),
121  .DMA_MemoryBaseAddr = (uint32_t)sc18is600.priv_tx_buf,
122  .DMA_DIR = DMA_DIR_PeripheralDST,
123  .DMA_BufferSize = _len,
124  .DMA_PeripheralInc = DMA_PeripheralInc_Disable,
125  .DMA_MemoryInc = DMA_MemoryInc_Enable,
126  .DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte,
127  .DMA_MemoryDataSize = DMA_MemoryDataSize_Byte,
128  .DMA_Mode = DMA_Mode_Normal,
129  .DMA_Priority = DMA_Priority_Medium,
130  .DMA_M2M = DMA_M2M_Disable
131  };
132  DMA_Init(DMA1_Channel5, &DMA_initStructure_5);
133 
134  /* Enable SPI_2 Rx request */
135  SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Rx, ENABLE);
136  /* Enable DMA1 Channel4 */
137  DMA_Cmd(DMA1_Channel4, ENABLE);
138 
139  /* Enable SPI_2 Tx request */
140  SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, ENABLE);
141  /* Enable DMA1 Channel5 */
142  DMA_Cmd(DMA1_Channel5, ENABLE);
143 
144  /* Enable DMA1 Channel4 Transfer Complete interrupt */
145  DMA_ITConfig(DMA1_Channel4, DMA_IT_TC, ENABLE);
146 }
147 
148 
150 
153  sc18is600.priv_tx_buf[0] = Sc18Is600_Cmd_Write; // write command
154  sc18is600.priv_tx_buf[1] = len;
155  sc18is600.priv_tx_buf[2] = addr;
156  Sc18Is600Select();
158 
159 }
160 
162 
163 }
164 
165 void sc18is600_tranceive(uint8_t addr, uint8_t len_tx, uint8_t len_rx) {
168  sc18is600.rx_len = len_rx;
169  sc18is600.priv_tx_buf[0] = Sc18Is600_Cmd_Read_After_Write; // read after write command
170  sc18is600.priv_tx_buf[1] = len_tx;
171  sc18is600.priv_tx_buf[2] = len_rx;
172  sc18is600.priv_tx_buf[3] = addr;
173  sc18is600.priv_tx_buf[4+len_tx] = addr;
174  Sc18Is600Select();
175  sc18is600_setup_SPI_DMA(len_tx+5);
176 }
177 
181  sc18is600.priv_tx_buf[0] = Sc18Is600_Cmd_Write_To_Reg; // write to register
182  sc18is600.priv_tx_buf[1] = addr;
184  Sc18Is600Select();
186 }
187 
188 
192  sc18is600.priv_tx_buf[0] = Sc18Is600_Cmd_Read_From_Reg; // read from register
193  sc18is600.priv_tx_buf[1] = addr;
194  sc18is600.priv_tx_buf[2] = 0;
195  Sc18Is600Select();
197 }
198 
199 #define ReadI2CStatReg() { \
200  sc18is600.priv_tx_buf[0] = Sc18Is600_Cmd_Read_From_Reg; \
201  sc18is600.priv_tx_buf[1] = Sc18Is600_I2CStat; \
202  sc18is600.priv_tx_buf[2] = 0; \
203  Sc18Is600Select(); \
204  sc18is600_setup_SPI_DMA(3); \
205  }
206 
207 
208 void exti2_irq_handler(void) {
209  /* clear EXTI */
210  if(EXTI_GetITStatus(EXTI_Line2) != RESET)
211  EXTI_ClearITPendingBit(EXTI_Line2);
212  switch (sc18is600.transaction) {
213  case Sc18Is600Receive:
214  case Sc18Is600Transmit:
215  case Sc18Is600Transcieve:
218  ReadI2CStatReg();
219  }
220  break;
223  // should not happen
224  break;
225  default:
226  break;
227  }
228 
229 }
230 
231 
232 
234 
235  DMA_ITConfig(DMA1_Channel4, DMA_IT_TC, DISABLE);
236  /* Disable SPI_2 Rx and TX request */
237  SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Rx, DISABLE);
238  SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, DISABLE);
239  /* Disable DMA1 Channel4 and 5 */
240  DMA_Cmd(DMA1_Channel4, DISABLE);
241  DMA_Cmd(DMA1_Channel5, DISABLE);
242 
243  switch (sc18is600.transaction) {
248  break;
249  case Sc18Is600Transmit:
253  }
258  }
259  break;
260  case Sc18Is600Receive:
261  case Sc18Is600Transcieve:
265  }
269  // debug
270  for (int i=1; i<sc18is600.rx_len+1; i++) sc18is600.priv_tx_buf[i] = 0;
271  Sc18Is600Select();
273  }
277  }
278  break;
279  default:
280  break;
281  }
282 
283 }
uint16_t value
Definition: adc_arch.c:585
uint8_t i2c_status
Definition: sc18i600.h:39
enum Sc18Is600Transaction transaction
Definition: sc18i600.h:35
void sc18is600_transmit(uint8_t addr, uint8_t len)
#define GPIOB
Definition: gpio_arch.h:35
uint8_t priv_tx_buf[SC18IS600_BUF_LEN]
Definition: sc18i600.h:36
void sc18is600_arch_init(void)
static void sc18is600_setup_SPI_DMA(uint8_t _len)
void sc18is600_write_to_register(uint8_t addr, uint8_t value)
#define GPIOD
Definition: gpio_arch.h:35
#define Sc18Is600_Cmd_Read_After_Write
unsigned long uint32_t
Definition: types.h:18
uint8_t rx_len
Definition: sc18i600.h:38
enum Sc18Is600Status status
Definition: sc18i600.h:34
uint8_t priv_rx_buf[SC18IS600_BUF_LEN]
Definition: sc18i600.h:37
#define Sc18Is600_Cmd_Write
struct Sc18Is600 sc18is600
Definition: sc18i600.c:3
unsigned char uint8_t
Definition: types.h:14
void sc18is600_read_from_register(uint8_t addr)
#define Sc18Is600_Cmd_Read_From_Reg
void exti2_irq_handler(void)
#define Sc18Is600_Cmd_Read_Buffer
#define Sc18Is600Unselect()
Definition: sc18is600_arch.h:4
void sc18is600_tranceive(uint8_t addr, uint8_t len_tx, uint8_t len_rx)
void dma1_c4_irq_handler(void)
#define Sc18Is600_Cmd_Write_To_Reg
void sc18is600_receive(uint8_t addr, uint8_t len)
#define RESET
Definition: humid_sht.c:55
#define ReadI2CStatReg()
#define Sc18Is600Select()
Definition: sc18is600_arch.h:5