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max7456_regs.h
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1 #ifndef MAX7456_REGS_H
2 #define MAX7456_REGS_H
3 
4 //OSD REGISTER ADDRESSES
5 #define OSD_VM0_REG 0x00
6 #define OSD_VM1_REG 0x01
7 #define OSD_DMM_REG 0x04
8 #define OSD_DMAH_REG 0x05
9 #define OSD_DMAL_REG 0x06
10 #define OSD_DMDI_REG 0x07
11 #define OSD_OSDBL_REG 0x6C
12 #define OSD_OSDBL_REG_R 0xEC
13 #define OSD_STAT_REG 0xA0
14 
15 //OSD BIT POSITIONS
16 #define OSD_VIDEO_MODE_PAL (1<<6) // Default = NTSC
17 #define OSD_SYNC_INTERNAL ((1<<5)|(1<<4)) // Default = AUTO
18 #define OSD_SYNC_EXTERNAL ((1<<5) // Default = AUTO
19 #define OSD_IMAGE_ENABLE (1<<3) // Default = OSD OFF
20 #define OSD_REFRESH_ON_NEXT_VSYNC (1<<2) // Default = immediately refresh video
21 #define OSD_RESET (1<<1) // VM0 reg, hardware set to 0 after reset
22 #define OSD_VOUT_DISABLE (1<<0) // default= VIDEO OUT ENABLED
23 #define OSD_8BIT_MODE (1<<6) // default= 16 BIT MODE
24 #define OSD_BLINK_CHAR (1<<4) // default= No BLINKING
25 #define OSD_INVERT_PIXELS (1<<3) // default= No INVERSION
26 #define OSD_CLEAR_DISPLAY_MEMORY (1<<2) // DMM reg, default = 0
27 #define OSD_AUTO_INCREMENT_MODE (1<<0) // default = NO AUTO INCREMENT
28 
29 // MAX7456 VIDEO_MODE_0 register
30 #define VIDEO_MODE_0_WRITE 0x00
31 #define VIDEO_MODE_0_READ 0x80
32 #define VIDEO_MODE_0_40_PAL 0x40
33 #define VIDEO_MODE_0_20_NoAutoSync 0x20
34 #define VIDEO_MODE_0_10_SyncInt 0x10
35 #define VIDEO_MODE_0_08_EnOSD 0x08
36 #define VIDEO_MODE_0_04_UpdateVsync 0x04
37 #define VIDEO_MODE_0_02_Reset 0x02
38 #define VIDEO_MODE_0_01_EnVideo 0x01
39 // VIDEO MODE 0 bitmap
40 #define NTSC 0x00
41 #define PAL 0x40
42 #define AUTO_SYNC 0x00
43 #define EXT_SYNC 0x20
44 #define INT_SYNC 0x30
45 #define OSD_EN 0x08
46 #define VERT_SYNC_IMM 0x00
47 #define VERT_SYNC_VSYNC 0x04
48 #define SW_RESET 0x02
49 #define BUF_EN 0x00
50 #define BUF_DI 0x01
51 
52 // MAX7456 VIDEO_MODE_1 register
53 #define VIDEO_MODE_1_WRITE 0x01
54 #define VIDEO_MODE_1_READ 0x81
55 
56 // MAX7456 DM_MODE register
57 #define DM_MODE_WRITE 0x04
58 #define DM_MODE_READ 0x84
59 
60 // MAX7456 DM_ADDRH register
61 #define DM_ADDRH_WRITE 0x05
62 #define DM_ADDRH_READ 0x85
63 
64 // MAX7456 DM_ADDRL register
65 #define DM_ADDRL_WRITE 0x06
66 #define DM_ADDRL_READ 0x87
67 
68 // MAX7456 DM_CODE_IN register
69 #define DM_CODE_IN_WRITE 0x07
70 #define DM_CODE_IN_READ 0x87
71 
72 // MAX7456 DM_CODE_OUT register
73 #define DM_CODE_OUT_READ 0xB0
74 
75 // MAX7456 FM_MODE register
76 #define FM_MODE_WRITE 0x08
77 #define FM_MODE_READ 0x88
78 
79 // MAX7456 FM_ADDRH register
80 #define FM_ADDRH_WRITE 0x09
81 #define FM_ADDRH_READ 0x89
82 
83 // MAX7456 FM_ADDRL register
84 #define FM_ADDRL_WRITE 0x0A
85 #define FM_ADDRL_READ 0x8A
86 
87 // MAX7456 FM_DATA_IN register
88 #define FM_DATA_IN_WRITE 0x0B
89 #define FM_DATA_IN_READ 0x8B
90 
91 // MAX7456 FM_DATA_OUT register
92 #define FM_DATA_OUT_READ 0xC0
93 
94 // MAX7456 STATUS register
95 #define STATUS_READ 0xA0
96 #define STATUS_40_RESET_BUSY 0x40
97 #define STATUS_20_NVRAM_BUSY 0x20
98 #define STATUS_04_LOSS_OF_SYNC 0x04
99 #define STATUS_02_PAL_DETECTED 0x02
100 #define STATUS_01_NTSC_DETECTED 0x01
101 
102 // MAX7456 requires clearing OSD Black Level register bit 0x10 after reset
103 #define OSDBL_WR 0x6C
104 #define OSDBL_RD 0xEC
105 #define OSDBL_10_DisableAutoBlackLevel 0x10
106 
107 #endif //MAX7456_REGS_H