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max11040_hw.c
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1 /*
2  * Copyright (C) 2010 Martin Mueller
3  *
4  * This file is part of paparazzi.
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6  * paparazzi is free software; you can redistribute it and/or modify
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22 
30 #include "armVIC.h"
31 #include "max11040_hw.h"
32 #include "adcs/max11040.h"
33 
34 #ifdef LOGGER
35 extern unsigned int getclock(void);
36 #endif
37 
38 volatile uint8_t num_irqs = 0;
39 
40 static void SSP_ISR(void) __attribute__((naked));
41 static void EXTINT_ISR(void) __attribute__((naked));
42 
43 #warning "This driver should be updated to use the new SPI peripheral"
44 
45 #ifndef SPI1_VIC_SLOT
46 #define SPI1_VIC_SLOT 7
47 #endif
48 
49 static void SSP_ISR(void) {
50  int i;
51  ISR_ENTRY();
52 
53  switch (max11040_status) {
54 
55  case MAX11040_RESET:
56  {
57  /* read dummy control byte reply */
58  uint8_t foo __attribute__ ((unused));
59  foo = SSPDR;
60  foo = SSPDR;
61  /* write configuration register */
62  SSP_Send(0x60); /* wr conf */
63  SSP_Send(0x30); /* adc0: en24bit, xtalen, no faultdis */
64  for (i=1; i<MAXM_NB_ADCS; i++) {
65  SSP_Send(0x20); /* adcx: en24bit, no xtalen, no faultdis */
66  }
68  SSP_ClearRti();
69  }
70  break;
71 
72  case MAX11040_CONF:
73  {
74  /* read dummy control byte reply */
75  uint8_t foo __attribute__ ((unused));
76  foo = SSPDR;
77  for (i=0; i<MAXM_NB_ADCS; i++) {
78  foo = SSPDR;
79  }
80  /* write sampling instant register */
81  SSP_Send(0x40); /* wr instant */
82  for (i=0; i<MAXM_NB_ADCS; i++) {
83  SSP_Send(0); /* adcx: no delay */
84  SSP_Send(0);
85  SSP_Send(0);
86  SSP_Send(0);
87  }
89  SSP_ClearRti();
90  }
91  break;
92 
93  case MAX11040_INSTANT:
94  {
95  /* read dummy control byte reply */
96  uint8_t foo __attribute__ ((unused));
97  foo = SSPDR;
98  for (i=0; i<MAXM_NB_ADCS; i++) {
99  foo = SSPDR;
100  foo = SSPDR;
101  foo = SSPDR;
102  foo = SSPDR;
103  }
104  /* write data rate control register */
105  SSP_Send(0x50); /* wr rate */
106  SSP_Send(0x26); /* adc: 250.1 sps */
107  SSP_Send(0x00);
109  SSP_ClearRti();
110  }
111  break;
112 
113  case MAX11040_RATE:
114  {
115  uint8_t foo __attribute__ ((unused));
116  foo = SSPDR;
117  foo = SSPDR;
118  foo = SSPDR;
119  /* read data register */
120  SSP_Send(0xF0); /* rd data */
121  for (i=0; i<MAXM_NB_ADCS; i++) {
122  SSP_Send(0x00); /* adcx: data */
123  SSP_Send(0x00);
124  SSP_Send(0x00);
125  SSP_Send(0x00);
126  SSP_Send(0x00);
127  SSP_Send(0x00);
128  SSP_Send(0x00);
129  SSP_Send(0x00);
130  SSP_Send(0x00);
131  SSP_Send(0x00);
132  SSP_Send(0x00);
133  SSP_Send(0x00);
134  }
136  SSP_ClearRti();
137  }
138  break;
139 
140  case MAX11040_DATA:
141  {
142  uint8_t foo __attribute__ ((unused));
143  foo = SSPDR;
144  for (i=0; i<MAXM_NB_ADCS; i++) {
145  foo = SSPDR;
146  foo = SSPDR;
147  foo = SSPDR;
148  foo = SSPDR;
149  foo = SSPDR;
150  foo = SSPDR;
151  foo = SSPDR;
152  foo = SSPDR;
153  foo = SSPDR;
154  foo = SSPDR;
155  foo = SSPDR;
156  foo = SSPDR;
157  }
158 
159  /* read data */
160  /* read data register */
161  SSP_Send(0xF0); /* rd data */
162  for (i=0; i<MAXM_NB_ADCS; i++) {
163  SSP_Send(0x00); /* adc0: data */
164  SSP_Send(0x00);
165  SSP_Send(0x00);
166  SSP_Send(0x00);
167  SSP_Send(0x00);
168  SSP_Send(0x00);
169  SSP_Send(0x00);
170  SSP_Send(0x00);
171  SSP_Send(0x00);
172  SSP_Send(0x00);
173  SSP_Send(0x00);
174  SSP_Send(0x00);
175  }
176 
177  SSP_ClearRti();
178  }
179  break;
180 
181  case MAX11040_DATA2:
182  {
183  uint8_t foo __attribute__ ((unused));
184 
185  SSP_ClearRti();
186  SSP_ClearRxi();
187 
188  if (max11040_count <= MAXM_NB_CHAN+2)
189  {
190  SSP_Send(0x00);
191  SSP_Send(0x00);
192  SSP_Send(0x00);
193  SSP_Send(0x00);
194  SSP_Send(0x00);
195  SSP_Send(0x00);
196  }
197 
198  if (max11040_count == 0) foo = SSPDR;
199 
205 
206  max11040_count++;
207 
213 
214  max11040_count++;
215 
217  {
218  MaxmUnselect();
220  i = max11040_buf_in+1;
221  if (i >= MAX11040_BUF_SIZE) i=0;
222  if (i != max11040_buf_out) {
223  max11040_buf_in = i;
224  } else {
225  //throw error;
226  }
227  }
228  }
229  break;
230 
231  }
232 
233  VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
234  ISR_EXIT();
235 }
236 
237 void EXTINT_ISR(void) {
238  ISR_ENTRY();
239 
240  if (num_irqs++ == 5)
241  {
242  /* switch SSEL P0.20 to be used as GPIO */
243  PINSEL1 &= ~(3 << 8);
244  IO0DIR |= 1 << 20;
246  }
247 
249 
250 #ifdef LOGGER
251  max11040_timestamp[max11040_buf_in] = getclock();
252 #endif
253 
254  MaxmSelect();
255 
256  /* read data */
257  SSP_Send(0xF0);
258  SSP_Send(0x00);
259  SSP_Send(0x00);
260  SSP_Send(0x00);
261  SSP_Send(0x00);
262  SSP_Send(0x00);
263  SSP_Send(0x00);
264 
265  max11040_count = 0;
266  }
267 
268  /* clear EINT */
269  SetBit(EXTINT, MAXM_DRDY_EINT);
270 
271  VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
272  ISR_EXIT();
273 }
274 
275 
276 void max11040_hw_init( void ) {
277  int i;
278 
279  /* *** configure SPI *** */
280  /* setup pins for SSP (SCK, MISO, MOSI, SSEL) */
282 
283  /* setup SSP */
284  SSPCR0 = SSPCR0_VAL;;
285  SSPCR1 = SSPCR1_VAL;
286  SSPCPSR = 0x02;
287 
288  /* initialize interrupt vector */
289  VICIntSelect &= ~VIC_BIT( VIC_SPI1 ); /* SPI1 selected as IRQ */
290  VICIntEnable = VIC_BIT( VIC_SPI1 ); /* enable it */
292  _VIC_ADDR(SPI1_VIC_SLOT) = (uint32_t)SSP_ISR; /* address of the ISR */
293 
294 
295  /* *** configure DRDY pin*** */
296  /* connected pin to EXINT */
297  MAXM_DRDY_PINSEL |= MAXM_DRDY_PINSEL_VAL << MAXM_DRDY_PINSEL_BIT;
298  SetBit(EXTMODE, MAXM_DRDY_EINT); /* EINT is edge trigered */
299  ClearBit(EXTPOLAR, MAXM_DRDY_EINT); /* EINT is trigered on falling edge */
300  SetBit(EXTINT, MAXM_DRDY_EINT); /* clear pending EINT */
301 
302  /* initialize interrupt vector */
303  VICIntSelect &= ~VIC_BIT( MAXM_DRDY_VIC_IT ); /* select EINT as IRQ source */
304  VICIntEnable = VIC_BIT( MAXM_DRDY_VIC_IT ); /* enable it */
305  _VIC_CNTL(MAX11040_DRDY_VIC_SLOT) = VIC_ENABLE | MAXM_DRDY_VIC_IT;
306  _VIC_ADDR(MAX11040_DRDY_VIC_SLOT) = (uint32_t)EXTINT_ISR; /* address of the ISR */
307 
308 
309  /* write configuration register */
310  SSP_Send(0x60); /* wr conf */
311  for (i=0; i<MAXM_NB_ADCS; i++) {
312  SSP_Send(0x40); /* adcx: reset */
313  }
314  SSP_Enable();
315  SSP_ClearRti();
316  SSP_EnableRti();
317 }
318 
#define VICIntSelect
Definition: LPC21xx.h:430
#define SSP_PINSEL1_MOSI
Definition: spi_arch.c:367
#define MAX11040_INSTANT
Definition: max11040.h:22
volatile uint8_t num_irqs
Definition: max11040_hw.c:38
#define SSP_ClearRxi()
Definition: max11040_hw.h:48
static void SSP_ISR(void)
Definition: max11040_hw.c:49
#define SSP_Send(_a)
Definition: ssp_hw.h:16
#define SSPCPSR
Definition: LPC21xx.h:226
#define _VIC_CNTL(idx)
Definition: armVIC.h:19
#define SSPCR0_VAL
#define SPI1_VIC_SLOT
Definition: max11040_hw.c:46
#define EXTMODE
Definition: LPC21xx.h:419
#define MaxmSelect()
Definition: max11040_hw.h:56
#define SSPCR1_VAL
#define SSP_Enable()
Definition: max11040_hw.h:44
#define MAX11040_RESET
Definition: max11040.h:20
volatile uint8_t max11040_data
Definition: max11040.c:36
#define MAXM_NB_CHAN
Definition: max11040.h:7
#define SSPCR0
Definition: LPC21xx.h:222
#define MAX11040_CONF
Definition: max11040.h:21
#define _VIC_ADDR(idx)
Definition: armVIC.h:20
#define MAX11040_DATA2
Definition: max11040.h:26
#define EXTPOLAR
Definition: LPC21xx.h:420
#define EXTINT
Definition: LPC21xx.h:417
#define SSP_PINSEL1_SSEL
Definition: spi_arch.c:368
volatile uint32_t max11040_buf_in
Definition: max11040.c:40
#define VICVectAddr
Definition: LPC21xx.h:436
unsigned long uint32_t
Definition: types.h:18
volatile uint32_t max11040_timestamp[MAX11040_BUF_SIZE]
Definition: max11040.c:38
uint16_t foo
Definition: main_demo5.c:54
static void EXTINT_ISR(void)
Definition: max11040_hw.c:237
#define MAXM_NB_ADCS
Definition: max11040.h:8
#define VIC_BIT(chan)
Definition: lpcVIC.h:105
#define SSP_EnableRti()
Definition: max11040_hw.h:52
volatile uint8_t max11040_status
Definition: max11040.c:35
#define IO0DIR
Definition: LPC21xx.h:335
#define MAX11040_DATA
Definition: max11040.h:25
unsigned char uint8_t
Definition: types.h:14
#define SSPDR
Definition: LPC21xx.h:224
#define ISR_EXIT()
Definition: armVIC.h:61
#define SSP_ClearRti()
Definition: max11040_hw.h:54
volatile uint8_t max11040_count
Definition: max11040.c:39
#define SSP_PINSEL1_SCK
Definition: spi_arch.c:365
#define VICIntEnable
Definition: LPC21xx.h:431
#define PINSEL1
Definition: LPC21xx.h:348
#define VIC_SPI1
Definition: lpcVIC.h:81
volatile int32_t max11040_values[MAX11040_BUF_SIZE][MAXM_NB_CHAN]
Definition: max11040.c:37
#define MAX11040_DATA_AVAILABLE
Definition: max11040.h:29
#define MAX11040_BUF_SIZE
Definition: max11040.h:9
#define SSPCR1
Definition: LPC21xx.h:223
#define SSP_PINSEL1_MISO
Definition: spi_arch.c:366
#define ISR_ENTRY()
Definition: armVIC.h:40
#define MAX11040_RATE
Definition: max11040.h:23
#define VIC_ENABLE
Definition: lpcVIC.h:102
volatile uint32_t max11040_buf_out
Definition: max11040.c:41
#define MaxmUnselect()
Definition: max11040_hw.h:57
void max11040_hw_init(void)
Definition: max11040_hw.c:276