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lsm303dlhc_regs.h
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1 /*
2  * Copyright (C) 2014 Federico Ruiz Ugalde
3  *
4  * This file is part of paparazzi.
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20  */
21 
27 #ifndef LSM303DLHC_REGS_H
28 #define LSM303DLHC_REGS_H
29 
30 /* default I2C address */
31 #define LSM303DLHC_ACC_ADDR 0x32
32 #define LSM303DLHC_MAG_ADDR 0x3C
33 
34 /* Registers */
35 #define LSM303DLHC_REG_CTRL_REG1_A 0x20
36 #define LSM303DLHC_REG_CTRL_REG2_A 0x21
37 #define LSM303DLHC_REG_CTRL_REG3_A 0x22
38 #define LSM303DLHC_REG_CTRL_REG4_A 0x23
39 #define LSM303DLHC_REG_CTRL_REG5_A 0x24
40 #define LSM303DLHC_REG_CTRL_REG6_A 0x25
41 #define LSM303DLHC_REG_REF_DATA_CAP_A 0x26
42 #define LSM303DLHC_REG_STATUS_REG_A 0x27
43 #define LSM303DLHC_REG_OUT_X_L_A 0x28
44 #define LSM303DLHC_REG_OUT_X_H_A 0x29
45 #define LSM303DLHC_REG_OUT_Y_L_A 0x2A
46 #define LSM303DLHC_REG_OUT_Y_H_A 0x2B
47 #define LSM303DLHC_REG_OUT_Z_L_A 0x2C
48 #define LSM303DLHC_REG_OUT_Z_H_A 0x2D
49 #define LSM303DLHC_REG_FIFO_CTRL_REG_A 0x2E
50 #define LSM303DLHC_REG_FIFO_SRC_REG_A 0x2F
51 #define LSM303DLHC_REG_INT1_CFG_A 0x30
52 #define LSM303DLHC_REG_INT1_SRC_A 0x31
53 #define LSM303DLHC_REG_INT1_THS_A 0x32
54 #define LSM303DLHC_REG_INT1_DURATION_A 0x33
55 #define LSM303DLHC_REG_INT2_CFG_A 0x34
56 #define LSM303DLHC_REG_INT2_SRC_A 0x35
57 #define LSM303DLHC_REG_INT2_THS_A 0x36
58 #define LSM303DLHC_REG_INT2_DURATION_A 0x37
59 #define LSM303DLHC_REG_CLICK_CFG_A 0x38
60 #define LSM303DLHC_REG_CLICK_SRC_A 0x39
61 #define LSM303DLHC_REG_CLICK_THS_A 0x3A
62 #define LSM303DLHC_REG_TIME_LIMIT_A 0x3B
63 #define LSM303DLHC_REG_TIME_LATENCY_A 0x3C
64 #define LSM303DLHC_REG_TIME_WINDOW_A 0x3D
65 #define LSM303DLHC_REG_CRA_REG_M 0x00
66 #define LSM303DLHC_REG_CRB_REG_M 0x01
67 #define LSM303DLHC_REG_MR_REG_M 0x02
68 #define LSM303DLHC_REG_OUT_X_H_M 0x03
69 #define LSM303DLHC_REG_OUT_X_L_M 0x04
70 #define LSM303DLHC_REG_OUT_Z_H_M 0x05
71 #define LSM303DLHC_REG_OUT_Z_L_M 0x06
72 #define LSM303DLHC_REG_OUT_Y_H_M 0x07
73 #define LSM303DLHC_REG_OUT_Y_L_M 0x08
74 #define LSM303DLHC_REG_SR_REG_M 0x09
75 #define LSM303DLHC_REG_IRA_REG_M 0x0A
76 #define LSM303DLHC_REG_IRB_REG_M 0x0B
77 #define LSM303DLHC_REG_IRC_REG_M 0x0C
78 #define LSM303DLHC_REG_TEMP_OUT_H_M 0x31
79 #define LSM303DLHC_REG_TEMP_OUT_L_M 0x32
80 
81 /* Bit definitions */
82 #define LSM303DLHC_ODR_MASK 0xF0
83 #define LSM303DLHC_LPen (1 << 3)
84 #define LSM303DLHC_Xen (1 << 0)
85 #define LSM303DLHC_Yen (1 << 1)
86 #define LSM303DLHC_Zen (1 << 2)
87 
88 #define LSM303DLHC_FS_MASK 0x30
89 #define LSM303DLHC_HR (1 << 3)
90 #define LSM303DLHC_BDU (1 << 7)
91 
92 #define LSM303DLHC_I1_DRDY1 (1 << 4)
93 
94 #define LSM303DLHC_DO0_MASK 0x1C
95 #define LSM303DLHC_GN_MASK 0xE0
96 #define LSM303DLHC_MD_MASK 0x03
97 
98 
99 
100 #endif // LSM303DLHC_REGS_H