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lpcUART.h
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1 /******************************************************************************
2  *
3  * $RCSfile$
4  * $Revision$
5  *
6  * Header file for Philips LPC ARM Processors.
7  * Copyright 2004 R O SoftWare
8  *
9  * No guarantees, warrantees, or promises, implied or otherwise.
10  * May be used for hobby or commercial purposes provided copyright
11  * notice remains intact.
12  *
13  *****************************************************************************/
14 #ifndef INC_LPC_UART_H
15 #define INC_LPC_UART_H
16 
17 // Universal Asynchronous Receiver Transmitter Registers
18 typedef struct
19 {
20  union
21  {
22  REG_8 rbr; // Receive Buffer Register
23  REG_8 thr; // Transmit Holding Register
24  REG_8 dll; // Divisor Latch Register (LSB)
25  REG_8 _pad0[4];
26  };
27 
28  union
29  {
30  REG_8 ier; // Interrupt Enable Register
31  REG_8 dlm; // Divisor Latch Register (MSB)
32  REG_8 _pad1[4];
33  };
34 
35  union
36  {
37  REG_8 iir; // Interrupt ID Register
38  REG_8 fcr; // FIFO Control Register
39  REG_8 _pad2[4];
40  };
41 
42  REG_8 lcr; // Line Control Registe
43  REG_8 _pad3[3];
44  REG_8 mcr; // MODEM Control Register
45  REG_8 _pad4[3];
46  REG_8 lsr; // Line Status Register
47  REG_8 _pad5[3];
48  REG_8 msr; // MODEM Status Register
49  REG_8 _pad6[3];
50  REG_8 scr; // Scratch Pad Register
51  REG_8 _pad7[3];
52 } uartRegs_t;
53 
55 // UART defines
56 
57 // Interrupt Enable Register bit definitions
58 #define UIER_ERBFI (1 << 0) // Enable Receive Data Available Interrupt
59 #define UIER_ETBEI (1 << 1) // Enable Transmit Holding Register Empty Interrupt
60 #define UIER_ELSI (1 << 2) // Enable Receive Line Status Interrupt
61 #define UIER_EDSSI (1 << 3) // Enable MODEM Status Interrupt
62 
63 // Interrupt ID Register bit definitions
64 #define UIIR_NO_INT (1 << 0) // NO INTERRUPTS PENDING
65 #define UIIR_MS_INT (0 << 1) // MODEM Status
66 #define UIIR_THRE_INT (1 << 1) // Transmit Holding Register Empty
67 #define UIIR_RDA_INT (2 << 1) // Receive Data Available
68 #define UIIR_RLS_INT (3 << 1) // Receive Line Status
69 #define UIIR_CTI_INT (6 << 1) // Character Timeout Indicator
70 #define UIIR_ID_MASK 0x0E
71 
72 // FIFO Control Register bit definitions
73 #define UFCR_FIFO_ENABLE (1 << 0) // FIFO Enable
74 #define UFCR_RX_FIFO_RESET (1 << 1) // Reset Receive FIFO
75 #define UFCR_TX_FIFO_RESET (1 << 2) // Reset Transmit FIFO
76 #define UFCR_FIFO_TRIG1 (0 << 6) // Trigger @ 1 character in FIFO
77 #define UFCR_FIFO_TRIG4 (1 << 6) // Trigger @ 4 characters in FIFO
78 #define UFCR_FIFO_TRIG8 (2 << 6) // Trigger @ 8 characters in FIFO
79 #define UFCR_FIFO_TRIG14 (3 << 6) // Trigger @ 14 characters in FIFO
80 
81 // Line Control Register bit definitions
82 #define ULCR_CHAR_5 (0 << 0) // 5-bit character length
83 #define ULCR_CHAR_6 (1 << 0) // 6-bit character length
84 #define ULCR_CHAR_7 (2 << 0) // 7-bit character length
85 #define ULCR_CHAR_8 (3 << 0) // 8-bit character length
86 #define ULCR_STOP_1 (0 << 2) // 1 stop bit
87 #define ULCR_STOP_2 (1 << 2) // 2 stop bits
88 #define ULCR_PAR_NO (0 << 3) // No Parity
89 #define ULCR_PAR_ODD (1 << 3) // Odd Parity
90 #define ULCR_PAR_EVEN (3 << 3) // Even Parity
91 #define ULCR_PAR_MARK (5 << 3) // MARK "1" Parity
92 #define ULCR_PAR_SPACE (7 << 3) // SPACE "0" Paruty
93 #define ULCR_BREAK_ENABLE (1 << 6) // Output BREAK line condition
94 #define ULCR_DLAB_ENABLE (1 << 7) // Enable Divisor Latch Access
95 
96 // Modem Control Register bit definitions
97 #define UMCR_DTR (1 << 0) // Data Terminal Ready
98 #define UMCR_RTS (1 << 1) // Request To Send
99 #define UMCR_LB (1 << 4) // Loopback
100 
101 // Line Status Register bit definitions
102 #define ULSR_RDR (1 << 0) // Receive Data Ready
103 #define ULSR_OE (1 << 1) // Overrun Error
104 #define ULSR_PE (1 << 2) // Parity Error
105 #define ULSR_FE (1 << 3) // Framing Error
106 #define ULSR_BI (1 << 4) // Break Interrupt
107 #define ULSR_THRE (1 << 5) // Transmit Holding Register Empty
108 #define ULSR_TEMT (1 << 6) // Transmitter Empty
109 #define ULSR_RXFE (1 << 7) // Error in Receive FIFO
110 #define ULSR_ERR_MASK 0x1E
111 
112 // Modem Status Register bit definitions
113 #define UMSR_DCTS (1 << 0) // Delta Clear To Send
114 #define UMSR_DDSR (1 << 1) // Delta Data Set Ready
115 #define UMSR_TERI (1 << 2) // Trailing Edge Ring Indicator
116 #define UMSR_DDCD (1 << 3) // Delta Data Carrier Detect
117 #define UMSR_CTS (1 << 4) // Clear To Send
118 #define UMSR_DSR (1 << 5) // Data Set Ready
119 #define UMSR_RI (1 << 6) // Ring Indicator
120 #define UMSR_DCD (1 << 7) // Data Carrier Detect
121 
122 #endif
#define REG_8
Definition: LPC21xx.h:18
REG_8 lcr
Definition: lpcUART.h:42
REG_8 dll
Definition: lpcUART.h:24
REG_8 lsr
Definition: lpcUART.h:46
REG_8 iir
Definition: lpcUART.h:37
REG_8 fcr
Definition: lpcUART.h:38
REG_8 mcr
Definition: lpcUART.h:44
REG_8 msr
Definition: lpcUART.h:48
REG_8 scr
Definition: lpcUART.h:50
REG_8 thr
Definition: lpcUART.h:23
REG_8 dlm
Definition: lpcUART.h:31
REG_8 ier
Definition: lpcUART.h:30
REG_8 rbr
Definition: lpcUART.h:22