Paparazzi UAS  v5.2.2_stable-0-gd6b9f29
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l3gd20_spi.c
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1 /*
2  * Copyright (C) 2013 Felix Ruess <felix.ruess@gmail.com>
3  *
4  * This file is part of paparazzi.
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20  */
21 
28 #include "peripherals/l3gd20_spi.h"
29 
30 void l3gd20_spi_init(struct L3gd20_Spi *l3g, struct spi_periph *spi_p, uint8_t slave_idx)
31 {
32  /* set spi_peripheral */
33  l3g->spi_p = spi_p;
34 
35  /* configure spi transaction */
38  l3g->spi_trans.dss = SPIDss8bit;
40  l3g->spi_trans.cdiv = SPIDiv64;
41 
43  l3g->spi_trans.slave_idx = slave_idx;
44  l3g->spi_trans.output_length = 2;
45  l3g->spi_trans.input_length = 8;
46  // callback currently unused
47  l3g->spi_trans.before_cb = NULL;
48  l3g->spi_trans.after_cb = NULL;
49  l3g->spi_trans.input_buf = &(l3g->rx_buf[0]);
50  l3g->spi_trans.output_buf = &(l3g->tx_buf[0]);
51 
52  /* set inital status: Success or Done */
54 
55  /* set default L3GD20 config options */
57 
58  l3g->initialized = FALSE;
59  l3g->data_available = FALSE;
61 }
62 
63 
64 static void l3gd20_spi_write_to_reg(struct L3gd20_Spi *l3g, uint8_t _reg, uint8_t _val) {
65  l3g->spi_trans.output_length = 2;
66  l3g->spi_trans.input_length = 0;
67  l3g->tx_buf[0] = _reg;
68  l3g->tx_buf[1] = _val;
69  spi_submit(l3g->spi_p, &(l3g->spi_trans));
70 }
71 
72 // Configuration function called once before normal use
73 static void l3gd20_spi_send_config(struct L3gd20_Spi *l3g)
74 {
75  uint8_t reg_val = 0;
76 
77  switch (l3g->init_status) {
78  case L3G_CONF_WHO_AM_I:
79  /* query device id */
80  l3g->spi_trans.output_length = 1;
81  l3g->spi_trans.input_length = 2;
82  /* set read bit then reg address */
83  l3g->tx_buf[0] = (1<<7 | L3GD20_REG_WHO_AM_I);
84  if (spi_submit(l3g->spi_p, &(l3g->spi_trans)))
85  l3g->init_status++;
86  break;
87  case L3G_CONF_REG4:
88  /* set SPI mode, Filtered Data Selection */
89  reg_val = (l3g->config.spi_3_wire << 0) | (l3g->config.full_scale << 4);
91  l3g->init_status++;
92  break;
93  case L3G_CONF_ENABLE:
94  /* set data rate, range, enable measurement, is in standby after power up */
95  reg_val = (l3g->config.drbw << 4) |
96  L3GD20_PD | // Power Down Control to active mode
97  L3GD20_Xen | L3GD20_Yen | L3GD20_Zen; // enable z,y,x axes
99  l3g->init_status++;
100  break;
101  case L3G_CONF_DONE:
102  l3g->initialized = TRUE;
104  break;
105  default:
106  break;
107  }
108 }
109 
111 {
112  if (l3g->init_status == L3G_CONF_UNINIT) {
113  l3g->init_status++;
114  if (l3g->spi_trans.status == SPITransSuccess || l3g->spi_trans.status == SPITransDone) {
116  }
117  }
118 }
119 
120 void l3gd20_spi_read(struct L3gd20_Spi *l3g)
121 {
122  if (l3g->initialized && l3g->spi_trans.status == SPITransDone) {
123  l3g->spi_trans.output_length = 1;
124  l3g->spi_trans.input_length = 8;
125  /* set read bit and multiple byte bit, then address */
126  l3g->tx_buf[0] = (1<<7|1<<6|L3GD20_REG_STATUS_REG);
127  spi_submit(l3g->spi_p, &(l3g->spi_trans));
128  }
129 }
130 
131 #define Int16FromBuf(_buf,_idx) ((int16_t)((_buf[_idx+1]<<8) | _buf[_idx]))
132 
133 void l3gd20_spi_event(struct L3gd20_Spi *l3g)
134 {
135  if (l3g->initialized) {
136  if (l3g->spi_trans.status == SPITransFailed) {
138  }
139  else if (l3g->spi_trans.status == SPITransSuccess) {
140  // Successfull reading
141  if (bit_is_set(l3g->rx_buf[1], 3)) {
142  // new xyz data available
143  l3g->data_rates.rates.p = Int16FromBuf(l3g->rx_buf,2);
144  l3g->data_rates.rates.q = Int16FromBuf(l3g->rx_buf,4);
145  l3g->data_rates.rates.r = Int16FromBuf(l3g->rx_buf,6);
146  l3g->data_available = TRUE;
147  }
149  }
150  }
151  else if (l3g->init_status != L3G_CONF_UNINIT) { // Configuring but not yet initialized
152  switch (l3g->spi_trans.status) {
153  case SPITransFailed:
154  l3g->init_status--; // Retry config (TODO max retry)
155  case SPITransSuccess:
156  if (l3g->init_status == L3G_CONF_WHO_AM_I_OK) {
157  if (l3g->rx_buf[1] == L3GD20_WHO_AM_I) {
158  l3g->init_status++;
159  }
160  else {
162  }
163  }
164  case SPITransDone:
167  break;
168  default:
169  break;
170  }
171  }
172 }
enum SPIBitOrder bitorder
MSB/LSB order.
Definition: spi.h:152
#define L3GD20_Xen
Definition: l3gd20_regs.h:53
enum SPIClockPolarity cpol
clock polarity control
Definition: spi.h:149
struct spi_periph * spi_p
Definition: l3gd20_spi.h:39
#define L3GD20_REG_CTRL_REG1
Definition: l3gd20_regs.h:33
#define L3GD20_Zen
Definition: l3gd20_regs.h:55
uint8_t input_length
number of data words to read
Definition: spi.h:145
void l3gd20_spi_start_configure(struct L3gd20_Spi *l3g)
Definition: l3gd20_spi.c:110
void l3gd20_spi_event(struct L3gd20_Spi *l3g)
Definition: l3gd20_spi.c:133
bool_t initialized
config done flag
Definition: l3gd20_spi.h:44
enum SPIClockPhase cpha
clock phase control
Definition: spi.h:150
CPHA = 1.
Definition: spi.h:69
bool_t spi_3_wire
Set 3-wire SPI mode, if FALSE: 4-wire SPI mode.
Definition: l3gd20.h:44
enum L3gd20ConfStatus init_status
init status
Definition: l3gd20_spi.h:43
union L3gd20_Spi::@32 data_rates
volatile uint8_t * input_buf
pointer to receive buffer for DMA
Definition: spi.h:143
CPOL = 1.
Definition: spi.h:78
void l3gd20_spi_init(struct L3gd20_Spi *l3g, struct spi_periph *spi_p, uint8_t slave_idx)
Definition: l3gd20_spi.c:30
#define L3GD20_PD
Definition: l3gd20_regs.h:52
#define L3GD20_Yen
Definition: l3gd20_regs.h:54
enum SPISlaveSelect select
slave selection behavior
Definition: spi.h:148
#define FALSE
Definition: imu_chimu.h:141
enum SPITransactionStatus status
Definition: spi.h:156
struct Int16Rates rates
data vector in accel coordinate system
Definition: l3gd20_spi.h:47
static void l3gd20_set_default_config(struct L3gd20Config *c)
Definition: l3gd20.h:50
Definition: spi.h:84
Driver for L3GD20 3-axis gyroscope from ST using SPI.
enum SPIClockDiv cdiv
prescaler of main clock to use as SPI clock
Definition: spi.h:153
bool_t spi_submit(struct spi_periph *p, struct spi_transaction *t)
Submit a spi transaction.
Definition: spi_arch.c:470
enum L3gd20FullScale full_scale
gyro full scale
Definition: l3gd20.h:46
enum SPIDataSizeSelect dss
data transfer word size
Definition: spi.h:151
uint8_t output_length
number of data words to write
Definition: spi.h:146
static void l3gd20_spi_send_config(struct L3gd20_Spi *l3g)
Definition: l3gd20_spi.c:73
struct L3gd20Config config
Definition: l3gd20_spi.h:50
static void l3gd20_spi_write_to_reg(struct L3gd20_Spi *l3g, uint8_t _reg, uint8_t _val)
Definition: l3gd20_spi.c:64
#define L3GD20_WHO_AM_I
L3GD20 device identifier contained in L3GD20_REG_WHO_AM_I.
Definition: l3gd20_regs.h:46
#define TRUE
Definition: imu_chimu.h:144
#define Int16FromBuf(_buf, _idx)
Definition: l3gd20_spi.c:131
volatile uint8_t tx_buf[2]
Definition: l3gd20_spi.h:41
SPI peripheral structure.
Definition: spi.h:168
enum L3gd20DRBW drbw
Data rate and bandwidth.
Definition: l3gd20.h:47
unsigned char uint8_t
Definition: types.h:14
slave is selected before transaction and unselected after
Definition: spi.h:57
uint8_t slave_idx
slave id: SPI_SLAVE0 to SPI_SLAVE4
Definition: spi.h:147
#define L3GD20_REG_STATUS_REG
Definition: l3gd20_regs.h:37
#define L3GD20_REG_WHO_AM_I
Definition: l3gd20_regs.h:32
volatile bool_t data_available
data ready flag
Definition: l3gd20_spi.h:45
Definition: spi.h:119
#define L3GD20_REG_CTRL_REG4
Definition: l3gd20_regs.h:36
volatile uint8_t rx_buf[8]
Definition: l3gd20_spi.h:42
void l3gd20_spi_read(struct L3gd20_Spi *l3g)
Definition: l3gd20_spi.c:120
volatile uint8_t * output_buf
pointer to transmit buffer for DMA
Definition: spi.h:144
struct spi_transaction spi_trans
Definition: l3gd20_spi.h:40
SPICallback before_cb
NULL or function called before the transaction.
Definition: spi.h:154
SPICallback after_cb
NULL or function called after the transaction.
Definition: spi.h:155