Paparazzi UAS  v5.18.0_stable
Paparazzi is a free software Unmanned Aircraft System.
mcu_arch.c
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1 /*
2  * Copyright (C) 2010-2012 The Paparazzi team
3  *
4  * This file is part of Paparazzi.
5  *
6  * Paparazzi is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2, or (at your option)
9  * any later version.
10  *
11  * Paparazzi is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with Paparazzi; see the file COPYING. If not, write to
18  * the Free Software Foundation, 59 Temple Place - Suite 330,
19  * Boston, MA 02111-1307, USA.
20  *
21  */
22 
29 #include "mcu.h"
30 
31 #include BOARD_CONFIG
32 
33 #include <inttypes.h>
34 #include <libopencm3/stm32/gpio.h>
35 #include <libopencm3/stm32/rcc.h>
36 #include <libopencm3/stm32/timer.h>
37 #include <libopencm3/stm32/flash.h>
38 #include <libopencm3/cm3/scb.h>
39 #include <libopencm3/stm32/rtc.h>
40 #include <libopencm3/stm32/pwr.h>
41 
42 #include "std.h"
43 
44 #if defined(STM32F4)
45 /* untested, should go into libopencm3 */
46 const struct rcc_clock_scale rcc_hse_24mhz_3v3[RCC_CLOCK_3V3_END] = {
47  { /* 48MHz */
48  .pllm = 24,
49  .plln = 96,
50  .pllp = 2,
51  .pllq = 2,
52  .hpre = RCC_CFGR_HPRE_DIV_NONE,
53  .ppre1 = RCC_CFGR_PPRE_DIV_4,
54  .ppre2 = RCC_CFGR_PPRE_DIV_2,
55  .power_save = 1,
56  .flash_config = FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS,
57  .ahb_frequency = 48000000,
58  .apb1_frequency = 12000000,
59  .apb2_frequency = 24000000,
60  },
61  { /* 84MHz */
62  .pllm = 24,
63  .plln = 336,
64  .pllp = 4,
65  .pllq = 7,
66  .hpre = RCC_CFGR_HPRE_DIV_NONE,
67  .ppre1 = RCC_CFGR_PPRE_DIV_2,
68  .ppre2 = RCC_CFGR_PPRE_DIV_NONE,
69  .power_save = 1,
70  .flash_config = FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_2WS,
71  .ahb_frequency = 84000000,
72  .apb1_frequency = 42000000,
73  .apb2_frequency = 84000000,
74  },
75  { /* 120MHz */
76  .pllm = 24,
77  .plln = 240,
78  .pllp = 2,
79  .pllq = 5,
80  .hpre = RCC_CFGR_HPRE_DIV_NONE,
81  .ppre1 = RCC_CFGR_PPRE_DIV_4,
82  .ppre2 = RCC_CFGR_PPRE_DIV_2,
83  .power_save = 1,
84  .flash_config = FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS,
85  .ahb_frequency = 120000000,
86  .apb1_frequency = 30000000,
87  .apb2_frequency = 60000000,
88  },
89  { /* 168MHz */
90  .pllm = 24,
91  .plln = 336,
92  .pllp = 2,
93  .pllq = 7,
94  .hpre = RCC_CFGR_HPRE_DIV_NONE,
95  .ppre1 = RCC_CFGR_PPRE_DIV_4,
96  .ppre2 = RCC_CFGR_PPRE_DIV_2,
97  .flash_config = FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_5WS,
98  .ahb_frequency = 168000000,
99  .apb1_frequency = 42000000,
100  .apb2_frequency = 84000000,
101  },
102 };
103 #endif
104 
105 #if defined(STM32F1)
106 /*---------------------------------------------------------------------------*/
110 void rcc_clock_setup_in_hse_24mhz_out_24mhz_pprz(void);
111 void rcc_clock_setup_in_hse_24mhz_out_24mhz_pprz(void)
112 {
113  /* Enable internal high-speed oscillator. */
114  rcc_osc_on(RCC_HSI);
115  rcc_wait_for_osc_ready(RCC_HSI);
116 
117  /* Select HSI as SYSCLK source. */
118  rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
119 
120  /* Enable external high-speed oscillator 24MHz. */
121  rcc_osc_on(RCC_HSE);
122  rcc_wait_for_osc_ready(RCC_HSE);
123  rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK);
124 
125  /*
126  * Set prescalers for AHB, ADC, ABP1, ABP2.
127  * Do this before touching the PLL (TODO: why?).
128  */
129  rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 24MHz Max. 72MHz */
130  rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2); /* Set. 12MHz Max. 14MHz */
131  rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_NODIV); /* Set. 24MHz Max. 36MHz */
132  rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 24MHz Max. 72MHz */
133 
134  /*
135  * Sysclk runs with 24MHz -> 0 waitstates.
136  * 0WS from 0-24MHz
137  * 1WS from 24-48MHz
138  * 2WS from 48-72MHz
139  */
140  flash_set_ws(FLASH_ACR_LATENCY_0WS);
141 
142  /*
143  * Set the PLL multiplication factor to 2.
144  * 24MHz (external) * 2 (multiplier) / 2 (RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2) = 24MHz
145  */
146  rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL2);
147 
148  /* Select HSE as PLL source. */
149  rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK);
150 
151  /*
152  * External frequency divide by 2 before entering PLL
153  * (only valid/needed for HSE).
154  */
155  rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2);
156 
157  rcc_osc_on(RCC_PLL);
158  rcc_wait_for_osc_ready(RCC_PLL);
159 
160  /* Select PLL as SYSCLK source. */
161  rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
162 
163  /* Set the peripheral clock frequencies used */
164  rcc_ahb_frequency = 24000000;
165  rcc_apb1_frequency = 24000000;
166  rcc_apb2_frequency = 24000000;
167 }
168 #endif
169 
170 
171 #ifdef SYSTEM_MEMORY_BASE
172 void reset_to_dfu(void) {
173  // Request DFU at boot (init_dfu)
174  pwr_disable_backup_domain_write_protect();
175  RTC_BKPXR(0) = 0xFF;
176  pwr_enable_backup_domain_write_protect();
177  // Reset
178  scb_reset_system();
179 }
180 
181 typedef void resetHandler_t(void);
182 
183 typedef struct isrVector_s {
184  volatile uint32_t stackEnd;
185  resetHandler_t *resetHandler;
186 } isrVector_t;
187 
188 static isrVector_t *system_isr_vector_table_base = (isrVector_t *) SYSTEM_MEMORY_BASE; // Find in ST AN2606. Defined in board header.
189 
190 static void init_dfu(void) {
191  /* Reset to DFU if requested */
192  rcc_periph_clock_enable(RCC_RTC);
193  rcc_periph_clock_enable(RCC_PWR);
194  if (RTC_BKPXR(0) == 0xFF) {
195  // DFU request
196  // 0. Reset request
197  pwr_disable_backup_domain_write_protect();
198  RTC_BKPXR(0) = 0x00;
199  pwr_enable_backup_domain_write_protect();
200  // 1. Set MSP to system_isr_vector_table_base.stackEnd
201  // (betaflight system_stm32f4xx.c::75)
202  // (betaflight cmsis_armcc.h::226
203  register uint32_t __regMainStackPointer __asm("msp") __attribute__((unused)); // Note: declared unused to suppress gcc warning, not actually unused!
204  __regMainStackPointer = system_isr_vector_table_base->stackEnd; // = topOfMainStack;
205  // 2. system_isr_vector_table_base.resetHandler() (betaflight system_stm32f4xx.c::76)
206  system_isr_vector_table_base->resetHandler();
207  while (1);
208  }
209 }
210 #endif // SYSTEM_MEMORY_BASE
211 
212 
213 void mcu_arch_init(void)
214 {
215 #ifdef SYSTEM_MEMORY_BASE
216  init_dfu();
217 #endif
218 
219 #if LUFTBOOT
220  PRINT_CONFIG_MSG("We are running luftboot, the interrupt vector is being relocated.")
221 #if defined STM32F4
222  SCB_VTOR = 0x00004000;
223 #else
224  SCB_VTOR = 0x00002000;
225 #endif
226 #endif
227 #if EXT_CLK == 8000000
228 #if defined(STM32F1)
229  PRINT_CONFIG_MSG("Using 8MHz external clock to PLL it to 72MHz.")
230  rcc_clock_setup_in_hse_8mhz_out_72mhz();
231 #elif defined(STM32F4)
232 #if AHB_CLK == 84000000
233  PRINT_CONFIG_MSG("Using 8MHz external clock to PLL it to 84MHz.")
234  rcc_clock_setup_hse_3v3(&rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_84MHZ]);
235 #else
236  PRINT_CONFIG_MSG("Using 8MHz external clock to PLL it to 168MHz.")
237  rcc_clock_setup_hse_3v3(&rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_168MHZ]);
238 #endif
239 #endif
240 #elif EXT_CLK == 12000000
241 #if defined(STM32F1)
242  PRINT_CONFIG_MSG("Using 12MHz external clock to PLL it to 72MHz.")
243  rcc_clock_setup_in_hse_12mhz_out_72mhz();
244 #elif defined(STM32F4)
245  PRINT_CONFIG_MSG("Using 12MHz external clock to PLL it to 168MHz.")
246  rcc_clock_setup_hse_3v3(&rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_168MHZ]);
247 #endif
248 #elif EXT_CLK == 16000000
249 #if defined(STM32F4)
250  PRINT_CONFIG_MSG("Using 16MHz external clock to PLL it to 168MHz.")
251  rcc_clock_setup_hse_3v3(&rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_168MHZ]);
252 #endif
253 #elif EXT_CLK == 24000000
254 #if defined(STM32F4)
255  PRINT_CONFIG_MSG("Using 24MHz external clock to PLL it to 168MHz.")
256  rcc_clock_setup_hse_3v3(&rcc_hse_24mhz_3v3[RCC_CLOCK_3V3_168MHZ]);
257 #elif defined(STM32F1)
258  rcc_clock_setup_in_hse_24mhz_out_24mhz_pprz();
259 #endif
260 #elif EXT_CLK == 25000000
261 #if defined(STM32F4)
262  PRINT_CONFIG_MSG("Using 25MHz external clock to PLL it to 168MHz.")
263  rcc_clock_setup_hse_3v3(&rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_168MHZ]);
264 #endif
265 #else
266 #error EXT_CLK is either set to an unsupported frequency or not defined at all. Please check!
267 #endif
268 
269  /* Configure priority grouping 0 bits for pre-emption priority and 4 bits for sub-priority.
270  * this was previously in i2c driver
271  * FIXME is it really needed ?
272  */
273  scb_set_priority_grouping(SCB_AIRCR_PRIGROUP_NOGROUP_SUB16);
274 }
275 
276 #if defined(STM32F1)
277 #define RCC_CFGR_PPRE2_SHIFT 11
278 #define RCC_CFGR_PPRE2 (7 << RCC_CFGR_PPRE2_SHIFT)
279 
280 #define RCC_CFGR_PPRE1_SHIFT 8
281 #define RCC_CFGR_PPRE1 (7 << RCC_CFGR_PPRE1_SHIFT)
282 
283 static inline uint32_t rcc_get_ppre1(void)
284 {
285  return RCC_CFGR & RCC_CFGR_PPRE1;
286 }
287 
288 static inline uint32_t rcc_get_ppre2(void)
289 {
290  return RCC_CFGR & RCC_CFGR_PPRE2;
291 }
292 #elif defined(STM32F4)
293 static inline uint32_t rcc_get_ppre1(void)
294 {
295  return RCC_CFGR & ((1 << 10) | (1 << 11) | (1 << 12));
296 }
297 
298 static inline uint32_t rcc_get_ppre2(void)
299 {
300  return RCC_CFGR & ((1 << 13) | (1 << 14) | (1 << 15));
301 }
302 #endif
303 
311 uint32_t timer_get_frequency(uint32_t timer_peripheral)
312 {
313  switch (timer_peripheral) {
314  // Timers on high speed APB2
315  case TIM1:
316  case TIM8:
317 #ifdef TIM9
318  case TIM9:
319 #endif
320 #ifdef TIM10
321  case TIM10:
322 #endif
323 #ifdef TIM11
324  case TIM11:
325 #endif
326  if (!rcc_get_ppre2()) {
327  /* without APB2 prescaler, runs at APB2 freq */
328  return rcc_apb2_frequency;
329  } else {
330  /* with any ABP2 prescaler, runs at 2 * APB2 freq */
331  return rcc_apb2_frequency * 2;
332  }
333 
334  // timers on low speed APB1
335  case TIM2:
336  case TIM3:
337  case TIM4:
338  case TIM5:
339  case TIM6:
340  case TIM7:
341 #ifdef TIM12
342  case TIM12:
343 #endif
344 #ifdef TIM13
345  case TIM13:
346 #endif
347 #ifdef TIM14
348  case TIM14:
349 #endif
350  if (!rcc_get_ppre1()) {
351  /* without APB1 prescaler, runs at APB1 freq */
352  return rcc_apb1_frequency;
353  } else {
354  /* with any ABP1 prescaler, runs at 2 * APB1 freq */
355  return rcc_apb1_frequency * 2;
356  }
357  default:
358  // other timers currently not supported
359  break;
360  }
361  return 0;
362 }
timer_get_frequency
uint32_t timer_get_frequency(uint32_t timer_peripheral)
Get Timer clock frequency (before prescaling) Only valid if using the internal clock for the timer.
Definition: mcu_arch.c:311
uint32_t
unsigned long uint32_t
Definition: types.h:18
std.h
mcu.h
Arch independent mcu ( Micro Controller Unit ) utilities.
mcu_arch_init
void mcu_arch_init(void)
Definition: mcu_arch.c:109
PRINT_CONFIG_MSG
PRINT_CONFIG_MSG("USE_INS_NAV_INIT defaulting to TRUE")
inttypes.h
SYSTEM_MEMORY_BASE
#define SYSTEM_MEMORY_BASE
System memory base - for DFU bootloader.
Definition: crazybee_f4_1.0.h:13