Paparazzi UAS  v5.10_stable-5-g83a0da5-dirty
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i2c_arch.c
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22 
29 #include "mcu_periph/i2c.h"
30 
31 #include BOARD_CONFIG
32 
33 #include <libopencm3/stm32/rcc.h>
34 #include <libopencm3/stm32/gpio.h>
35 #include <libopencm3/cm3/nvic.h>
36 #include <libopencm3/cm3/scb.h>
37 
38 #include "mcu_periph/gpio.h"
39 
40 
41 #ifdef I2C_DEBUG_LED
42 #include "i2c_debug_led.h"
43 #endif // I2C_DEBUG_LED
44 
47 
48 
49 // Error bit mask
50 // XXX: consider moving this define into libopencm3
51 #define I2C_SR1_ERR_MASK (I2C_SR1_SMBALERT | \
52  I2C_SR1_TIMEOUT | \
53  I2C_SR1_PECERR | \
54  I2C_SR1_OVR | \
55  I2C_SR1_AF | \
56  I2C_SR1_ARLO | \
57  I2C_SR1_BERR)
58 
59 // Bit Control
60 
61 #define BIT_X_IS_SET_IN_REG(X,REG) (((REG) & (X)) == (X))
62 
63 // disable and enable irq functions are not implemented in libopencm3 defining them here
64 // XXX: consider moving this definitions into libopencm3
65 static inline void __disable_irq(void) { asm volatile("cpsid i"); }
66 static inline void __enable_irq(void) { asm volatile("cpsie i"); }
67 
68 // Critical Zones
69 
70 #define __I2C_REG_CRITICAL_ZONE_START __disable_irq();
71 #define __I2C_REG_CRITICAL_ZONE_STOP __enable_irq();
72 
73 
74 #ifndef NVIC_I2C_IRQ_PRIO
75 #define NVIC_I2C1_IRQ_PRIO 0
76 #define NVIC_I2C2_IRQ_PRIO 0
77 #define NVIC_I2C3_IRQ_PRIO 0
78 #else
79 #define NVIC_I2C1_IRQ_PRIO NVIC_I2C_IRQ_PRIO
80 #define NVIC_I2C2_IRQ_PRIO NVIC_I2C_IRQ_PRIO
81 #define NVIC_I2C3_IRQ_PRIO NVIC_I2C_IRQ_PRIO
82 #endif
83 
84 #if USE_I2C1 || USE_I2C2 || USE_I2C3
85 #if defined(STM32F1)
86 static void i2c_setup_gpio(uint32_t i2c)
87 {
88  switch (i2c) {
89 #if USE_I2C1
90  case I2C1:
92  gpio_set_mode(I2C1_GPIO_PORT, GPIO_MODE_OUTPUT_2_MHZ,
93  GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN,
95  break;
96 #endif
97 #if USE_I2C2
98  case I2C2:
100  gpio_set_mode(I2C2_GPIO_PORT, GPIO_MODE_OUTPUT_2_MHZ,
101  GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN,
103  break;
104 #endif
105  default:
106  break;
107  }
108 }
109 
110 #elif defined(STM32F4)
111 
112 static void i2c_setup_gpio(uint32_t i2c)
113 {
114  switch (i2c) {
115 #if USE_I2C1
116  case I2C1:
118  gpio_mode_setup(I2C1_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE,
120  gpio_set_output_options(GPIOB, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ,
123  break;
124 #endif
125 #if USE_I2C2
126  case I2C2:
128  gpio_mode_setup(I2C2_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE,
130  gpio_set_output_options(I2C2_GPIO_PORT, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ,
132  gpio_set_af(I2C2_GPIO_PORT, GPIO_AF4,
134  break;
135 #endif
136 #if USE_I2C3
137  case I2C3:
139  gpio_mode_setup(I2C3_GPIO_PORT_SCL, GPIO_MODE_AF, GPIO_PUPD_NONE, I2C3_GPIO_SCL);
140  gpio_set_output_options(I2C3_GPIO_PORT_SCL, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ,
141  I2C3_GPIO_SCL);
143 
145  gpio_mode_setup(I2C3_GPIO_PORT_SDA, GPIO_MODE_AF, GPIO_PUPD_NONE, I2C3_GPIO_SDA);
146  gpio_set_output_options(I2C3_GPIO_PORT_SDA, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ,
147  I2C3_GPIO_SDA);
149  break;
150 #endif
151  default:
152  break;
153  }
154 }
155 #endif
156 #endif // USE_I2Cx
157 
158 static inline void PPRZ_I2C_SEND_STOP(uint32_t i2c)
159 {
160  // Man: p722: Stop generation after the current byte transfer or after the current Start condition is sent.
161  i2c_send_stop(i2c);
162 
163 #ifdef I2C_DEBUG_LED
164  LED2_ON();
165  LED1_ON();
166  LED1_OFF();
167  LED2_OFF();
168 #endif
169 }
170 
171 // (RE)START
172 
173 static inline void PPRZ_I2C_SEND_START(struct i2c_periph *periph)
174 {
175  uint32_t i2c = (uint32_t) periph->reg_addr;
176 
177  // Reset the buffer pointer to the first byte
178  periph->idx_buf = 0;
179  periph->watchdog = 0;
180 
181 #ifdef I2C_DEBUG_LED
182  LED_SHOW_ACTIVE_BITS(regs);
183 
184  LED2_ON();
185  LED1_ON();
186  LED1_OFF();
187  LED1_ON();
188  LED1_OFF();
189  LED1_ON();
190  LED1_OFF();
191  LED2_OFF();
192 #endif
193 
194  // Enable Error IRQ, Event IRQ but disable Buffer IRQ
195  i2c_enable_interrupt(i2c, I2C_CR2_ITERREN);
196  i2c_enable_interrupt(i2c, I2C_CR2_ITEVTEN);
197  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
198 
199  // Issue a new start
200  i2c_nack_current(i2c);
201  i2c_disable_ack(i2c);
202  i2c_clear_stop(i2c);
203  i2c_peripheral_enable(i2c);
204  i2c_send_start(i2c);
205  periph->status = I2CStartRequested;
206 
207 }
208 
209 // STOP
210 
213 //
214 // SUBTRANSACTION SEQUENCES
215 // -We arrive here every time a ISR is called with no error
216 
222 };
223 
224 // Doc ID 13902 Rev 11 p 710/1072
225 // Transfer Sequence Diagram for Master Transmitter
226 static inline enum STMI2CSubTransactionStatus stmi2c_send(uint32_t i2c, struct i2c_periph *periph,
227  struct i2c_transaction *trans)
228 {
229  uint16_t SR1 = I2C_SR1(i2c);
230 
231  // Start Condition Was Just Generated
232  if (BIT_X_IS_SET_IN_REG(I2C_SR1_SB, SR1)) {
233  // Disable buffer interrupt
234  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
235  // Send Slave address and wait for ADDR interrupt
236  i2c_send_data(i2c, trans->slave_addr);
237  // Document the current Status
238  periph->status = I2CAddrWrSent;
239  }
240  // Address Was Sent
241  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1)) {
242  // Now read SR2 to clear the ADDR status Bit
243  uint16_t SR2 __attribute__((unused)) = I2C_SR2(i2c);
244 
245  // Maybe check we are transmitting (did not loose arbitration for instance)
246  // if (! BIT_X_IS_SET_IN_REG(I2C_SR2_TRA, SR2)) { }
247  // update: this should be caught by the ARLO error: so we will not arrive here
248 
249  // Send First max 2 bytes
250  i2c_send_data(i2c, trans->buf[0]);
251  if (trans->len_w > 1) {
252  i2c_send_data(i2c, trans->buf[1]);
253  periph->idx_buf = 2;
254  } else {
255  periph->idx_buf = 1;
256  }
257 
258  // Enable buffer-space available interrupt
259  // only if there is more to send: wait for TXE, no more to send: wait for BTF
260  if (periph->idx_buf < trans->len_w) {
261  i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN);
262  }
263 
264  // Document the current Status
265  periph->status = I2CSendingByte;
266  }
267  // The buffer is not full anymore AND we were not waiting for BTF
268  else if ((BIT_X_IS_SET_IN_REG(I2C_SR1_TxE, SR1)) && (BIT_X_IS_SET_IN_REG(I2C_CR2_ITBUFEN, I2C_CR2(i2c)))) {
269  // Send the next byte
270  i2c_send_data(i2c, trans->buf[periph->idx_buf]);
271  periph->idx_buf++;
272 
273  // All bytes Sent? Then wait for BTF instead
274  if (periph->idx_buf >= trans->len_w) {
275  // Not interested anymore to know the buffer has space left
276  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
277  // Next interrupt will be BTF (or error)
278  }
279  }
280  // BTF: means last byte was sent
281  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1)) {
282  if (trans->type == I2CTransTx) {
283  // Tell the driver we are ready
284  trans->status = I2CTransSuccess;
285  }
286  // Otherwise we still need to do the receiving part
287 
288  return STMI2C_SubTra_Ready;
289  } else { // Event Logic Error
290  return STMI2C_SubTra_Error;
291  }
292 
293  return STMI2C_SubTra_Busy;
294 }
295 
296 // Doc ID 13902 Rev 11 p 714/1072
297 // Transfer Sequence Diagram for Master Receiver for N=1
298 static inline enum STMI2CSubTransactionStatus stmi2c_read1(uint32_t i2c, struct i2c_periph *periph,
299  struct i2c_transaction *trans)
300 {
301  uint16_t SR1 = I2C_SR1(i2c);
302 
303  // Start Condition Was Just Generated
304  if (BIT_X_IS_SET_IN_REG(I2C_SR1_SB, SR1)) {
305  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
306  i2c_send_data(i2c, trans->slave_addr | 0x01);
307 
308  // Document the current Status
309  periph->status = I2CAddrRdSent;
310  }
311  // Address Was Sent
312  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1)) {
313  // First Clear the ACK bit: after the next byte we do not want new bytes
314  i2c_nack_current(i2c);
315  i2c_disable_ack(i2c);
316 
317  // --- next to steps MUST be executed together to avoid missing the stop
319 
320  // Only after setting ACK, read SR2 to clear the ADDR (next byte will start arriving)
321  uint16_t SR2 __attribute__((unused)) = I2C_SR2(i2c);
322 
323  // Schedule a Stop
324  PPRZ_I2C_SEND_STOP(i2c);
325 
327  // --- end of critical zone -----------
328 
329  // Enable the RXNE: it will trigger as soon as the 1 byte is received to get the result
330  i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN);
331 
332  // Document the current Status
333  periph->status = I2CReadingLastByte;
334  }
335  // As soon as there is 1 byte ready to read, we have our byte
336  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_RxNE, SR1)) {
337  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
338  trans->buf[0] = I2C_DR(i2c);
339 
340  // We got all the results (stop condition might still be in progress but this is the last interrupt)
341  trans->status = I2CTransSuccess;
342 
343  // Document the current Status:
344  // -the stop was actually already requested in the previous step
345  periph->status = I2CStopRequested;
346 
348  } else { // Event Logic Error
349  return STMI2C_SubTra_Error;
350  }
351 
352  return STMI2C_SubTra_Busy;
353 }
354 
355 // Doc ID 13902 Rev 11 p 713/1072
356 // Transfer Sequence Diagram for Master Receiver for N=2
357 static inline enum STMI2CSubTransactionStatus stmi2c_read2(uint32_t i2c, struct i2c_periph *periph,
358  struct i2c_transaction *trans)
359 {
360  uint16_t SR1 = I2C_SR1(i2c);
361 
362  // Start Condition Was Just Generated
363  if (BIT_X_IS_SET_IN_REG(I2C_SR1_SB, SR1)) {
364  // according to the datasheet: instantly shedule a NAK on the second received byte:
365  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
366  i2c_enable_ack(i2c);
367  i2c_nack_next(i2c);
368  i2c_send_data(i2c, trans->slave_addr | 0x01);
369 
370  // Document the current Status
371  periph->status = I2CAddrRdSent;
372  }
373  // Address Was Sent
374  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1)) {
375  // --- make absolutely sure this command is not delayed too much after the previous:
376  // --- the NAK bits must be set before the first byte arrived: allow other interrupts here
378 
379  // if transfer of DR was finished already then we will get too many bytes
380  // BEFORE clearing ACK, read SR2 to clear the ADDR (next byte will start arriving)
381  // clearing ACK after the byte transfer has already started will NACK the next (2nd)
382  uint16_t SR2 __attribute__((unused)) = I2C_SR2(i2c);
383 
384  // NOT First Clear the ACK bit but only AFTER clearing ADDR
385  i2c_disable_ack(i2c);
386 
387  // Disable the RXNE and wait for BTF
388  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
389 
391  // --- end of critical zone -----------
392 
393  // We do not set the RxE but wait for both bytes to arrive using BTF
394 
395  // Document the current Status
396  periph->status = I2CReadingByte;
397  }
398  // Receive buffer if full, master is halted: BTF
399  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1)) {
400  // Stop condition MUST be set BEFORE reading the DR
401  // otherwise since there is new buffer space a new byte will be read
402  PPRZ_I2C_SEND_STOP(i2c);
403 
404  // Document the current Status
405  periph->status = I2CStopRequested;
406 
407  trans->buf[0] = I2C_DR(i2c);
408  trans->buf[1] = I2C_DR(i2c);
409 
410  // We got all the results
411  trans->status = I2CTransSuccess;
412 
414  } else { // Event Logic Error
415  return STMI2C_SubTra_Error;
416  }
417 
418  return STMI2C_SubTra_Busy;
419 }
420 
421 // Doc ID 13902 Rev 11 p 712/1072
422 // Transfer Sequence Diagram for Master Receiver for N>2
423 static inline enum STMI2CSubTransactionStatus stmi2c_readmany(uint32_t i2c, struct i2c_periph *periph,
424  struct i2c_transaction *trans)
425 {
426  uint16_t SR1 = I2C_SR1(i2c);
427 
428  // Start Condition Was Just Generated
429  if (BIT_X_IS_SET_IN_REG(I2C_SR1_SB, SR1)) {
430  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
431  // The first data byte will be acked in read many so the slave knows it should send more
432  i2c_nack_current(i2c);
433  i2c_enable_ack(i2c);
434  // Clear the SB flag
435  i2c_send_data(i2c, trans->slave_addr | 0x01);
436 
437  // Document the current Status
438  periph->status = I2CAddrRdSent;
439  }
440  // Address Was Sent
441  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1)) {
442  periph->idx_buf = 0;
443 
444  // Enable RXNE: receive an interrupt any time a byte is available
445  // only enable if MORE than 3 bytes need to be read
446  if (periph->idx_buf < (trans->len_r - 3)) {
447  i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN);
448  }
449 
450  // ACK is still on to get more DATA
451  // Read SR2 to clear the ADDR (next byte will start arriving)
452  uint16_t SR2 __attribute__((unused)) = I2C_SR2(i2c);
453 
454  // Document the current Status
455  periph->status = I2CReadingByte;
456  }
457  // one or more bytes are available AND we were interested in Buffer interrupts
458  else if ((BIT_X_IS_SET_IN_REG(I2C_SR1_RxNE, SR1)) && (BIT_X_IS_SET_IN_REG(I2C_CR2_ITBUFEN, I2C_CR2(i2c)))) {
459  // read byte until 3 bytes remain to be read (e.g. len_r = 6, -> idx=3 means idx 3,4,5 = 3 remain to be read
460  if (periph->idx_buf < (trans->len_r - 3)) {
461  trans->buf[periph->idx_buf] = I2C_DR(i2c);
462  periph->idx_buf ++;
463  }
464  // from : 3bytes -> last byte: do nothing
465  //
466  // finally: this was the last byte
467  else if (periph->idx_buf >= (trans->len_r - 1)) {
468  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
469 
470  // Last Value
471  trans->buf[periph->idx_buf] = i2c_get_data(i2c);
472  periph->idx_buf ++;
473 
474  // We got all the results
475  trans->status = I2CTransSuccess;
476 
478  }
479 
480  // Check for end of transaction: start waiting for BTF instead of RXNE
481  if (periph->idx_buf < (trans->len_r - 3)) {
482  i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN);
483  } else { // idx >= len-3: there are 3 bytes to be read
484  // We want to halt I2C to have sufficient time to clear ACK, so:
485  // Stop listening to RXNE as it will be triggered infinitely since we did not empty the buffer
486  // on the next (second in buffer) received byte BTF will be set (buffer full and I2C halted)
487  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN);
488  }
489  }
490  // Buffer is full while this was not a RXNE interrupt
491  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1)) {
492  // Now the shift register and data register contain data(n-2) and data(n-1)
493  // And I2C is halted so we have time
494 
495  // --- Make absolutely sure the next 2 I2C actions are performed with no delay
497 
498  // First we clear the ACK while the SCL is held low by BTF
499  i2c_disable_ack(i2c);
500 
501  // Now that ACK is cleared we read one byte: instantly the last byte is being clocked in...
502  trans->buf[periph->idx_buf] = i2c_get_data(i2c);
503  periph->idx_buf ++;
504 
505  // Now the last byte is being clocked. Stop in MUST be set BEFORE the transfer of the last byte is complete
506  PPRZ_I2C_SEND_STOP(i2c);
507 
509 
510 
511  // --- end of critical zone -----------
512 
513  // Document the current Status
514  periph->status = I2CStopRequested;
515 
516  // read the byte2 we had in the buffer (BTF means 2 bytes available)
517  trans->buf[periph->idx_buf] = i2c_get_data(i2c);
518  periph->idx_buf ++;
519 
520  // Ask for an interrupt to read the last byte (which is normally still busy now)
521  // The last byte will be received with RXNE
522  i2c_enable_interrupt(i2c, I2C_CR2_ITBUFEN);
523  } else { // Event Logic Error
524  return STMI2C_SubTra_Error;
525  }
526 
527  return STMI2C_SubTra_Busy;
528 }
529 
531 // Restore bus conditions to normal after errors
532 
533 static inline void i2c_error(struct i2c_periph *periph)
534 {
535 #ifdef I2C_DEBUG_LED
536  uint8_t err_nr = 0;
537 #endif
538  periph->errors->er_irq_cnt++;
539  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_AF) != 0) { /* Acknowledge failure */
540  periph->errors->ack_fail_cnt++;
541  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_AF;
542 #ifdef I2C_DEBUG_LED
543  err_nr = 1;
544 #endif
545  }
546  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_BERR) != 0) { /* Misplaced Start or Stop condition */
547  periph->errors->miss_start_stop_cnt++;
548  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_BERR;
549 #ifdef I2C_DEBUG_LED
550  err_nr = 2;
551 #endif
552  }
553  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_ARLO) != 0) { /* Arbitration lost */
554  periph->errors->arb_lost_cnt++;
555  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_ARLO;
556 #ifdef I2C_DEBUG_LED
557  err_nr = 3;
558 #endif
559  }
560  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_OVR) != 0) { /* Overrun/Underrun */
561  periph->errors->over_under_cnt++;
562  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_OVR;
563 #ifdef I2C_DEBUG_LED
564  err_nr = 4;
565 #endif
566  }
567  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_PECERR) != 0) { /* PEC Error in reception */
568  periph->errors->pec_recep_cnt++;
569  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_PECERR;
570 #ifdef I2C_DEBUG_LED
571  err_nr = 5;
572 #endif
573  }
574  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_TIMEOUT) != 0) { /* Timeout or Tlow error */
575  periph->errors->timeout_tlow_cnt++;
576  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_TIMEOUT;
577 #ifdef I2C_DEBUG_LED
578  err_nr = 6;
579 #endif
580  }
581  if ((I2C_SR1((uint32_t)periph->reg_addr) & I2C_SR1_SMBALERT) != 0) { /* SMBus alert */
582  periph->errors->smbus_alert_cnt++;
583  I2C_SR1((uint32_t)periph->reg_addr) &= ~I2C_SR1_SMBALERT;
584 #ifdef I2C_DEBUG_LED
585  err_nr = 7;
586 #endif
587  }
588 
589 #ifdef I2C_DEBUG_LED
590  LED_ERROR(20, err_nr);
591 #endif
592 
593  return;
594 }
595 
596 
598 {
599  uint16_t SR1 = I2C_SR1(i2c);
600 
601  // Certainly do not wait for buffer interrupts:
602  // -------------------------------------------
603  i2c_disable_interrupt(i2c, I2C_CR2_ITBUFEN); // Disable TXE, RXNE
604 
605  // Error interrupts are handled separately:
606  // ---------------------------------------
607 
608  // Clear Event interrupt conditions:
609  // --------------------------------
610 
611  // Start Condition Was Generated
612  if (BIT_X_IS_SET_IN_REG(I2C_SR1_SB, SR1)) {
613  // SB: cleared by software when reading SR1 and writing to DR
614  i2c_send_data(i2c, 0x00);
615  }
616  // Address Was Sent
617  if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1)) {
618  // ADDR: Cleared by software when reading SR1 and then SR2
619  uint16_t SR2 __attribute__((unused)) = I2C_SR2(i2c);
620  }
621  // Byte Transfer Finished
622  if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1)) {
623  // SB: cleared by software when reading SR1 and reading/writing to DR
624  uint8_t dummy __attribute__((unused)) = i2c_get_data(i2c);
625  i2c_send_data(i2c, 0x00);
626  }
627 
628 }
629 
630 
632 // Restore bus conditions to normal after errors
633 
634 static inline void i2c_irq(struct i2c_periph *periph)
635 {
636 
637  /*
638  There are 7 possible event reasons to get here + all errors
639 
640  If IT_EV_FEN
641  -------------------------
642 
643  We are always interested in all IT_EV_FEV: all are required.
644 
645  1) SB // Start Condition Success in Master mode
646  2) ADDR // Address sent received Acknowledge
647  [ADDR10] // -- 10bit address stuff: not used
648  [STOPF] // -- only for slaves: master has no stop interrupt: not used
649  3) BTF // I2C has stopped working (it is waiting for new data, all buffers are tx_empty/rx_full)
650 
651  // Beware: using the buffered I2C has some interesting properties:
652  - in master receive mode: BTF only occurs after the 2nd received byte: after the first byte is received it is
653  in RD but the I2C can still receive a second byte. Only when the 2nd byte is received while the RxNE is 1
654  then a BTF occurs (I2C can not continue receiving bytes or they will get lost). During BTF I2C is halted (SCL held low)
655  - in master transmit mode: when writing a byte to WD, you instantly get a new TxE interrupt while the first is not
656  transmitted yet. The byte was pushed to the I2C shift register and the buffer is ready for more. You can already
657  fill new data in the buffer while the first is still being transmitted for max performance transmission.
658 
659  // Beware: besides data buffering you can/must plan several consecutive actions. You can send 2 bytes to the buffer, ask for a stop and
660  a new start in one go.
661 
662  - thanks to / because of this buffering and event sheduling there is not 1 interrupt per start / byte / stop
663  This also means you must think more in advance and a transaction could be popped from the transaction stack even before it's
664  stop condition is actually generated.
665 
666  // Beware: the order in which Status (and other register) is read determines how flags are cleared.
667  You should NOT simply read SR1 & SR2 every time
668 
669  If IT_EV_FEN AND IT_EV_BUF
670  --------------------------
671 
672  Buffer event are not always wanted and are typically switched on during longer data transfers. Make sure to turn off in time.
673 
674  4) RxNE
675  5) TxE
676 
677  --------------------------------------------------------------------------------------------------
678 
679  The STM waits indefinitely (holding SCL low) for user interaction:
680  a) after a master-start (waiting for address)
681  b) after an address (waiting for data)
682  not during data sending when using buffered
683  c) after the last byte is transmitted (waiting for either stop or restart)
684  not during data receiving when using buffered
685  not after the last byte is received
686 
687  - The STM I2C stalls indefinitely when a stop condition was attempted that
688  did not succeed. The BUSY flag remains on.
689  - There is no STOP interrupt.
690 
691  Caution Reading the status:
692  - Caution: this clears several flags and can start transmissions etc...
693  - Certain flags like STOP / (N)ACK need to be guaranteed to be set before
694  the transmission of the byte is finished. At higher clock rates that can be
695  quite fast: so we allow no other interrupt to be triggered in between
696  reading the status and setting all needed flags
697 
698  */
699 
700  // Here we go ...
701 
702  // Apparently we got an I2C interrupt: EVT BUF or ERR
703 
704 #ifdef I2C_DEBUG_LED
705  // Notify ISR is triggered
706  LED1_ON();
707  LED1_OFF();
708 #endif
709 
710  // Save Some Direct Access to the I2C Registers ...
711  uint32_t i2c = (uint32_t) periph->reg_addr;
712 
714  // Check if we were ready ...
715  if (periph->trans_extract_idx == periph->trans_insert_idx) {
716  // Nothing Left To Do
717 
718 #ifdef I2C_DEBUG_LED
719  LED2_ON();
720  LED1_ON();
721  LED2_OFF();
722  LED1_OFF();
723 
724  // no transaction and also an error?
725  LED_SHOW_ACTIVE_BITS(regs);
726 #endif
727 
728  // If we still get an interrupt but there are no more things to do
729  // (which can happen if an event was sheduled just before a bus error occurs)
730  // (or can happen if both error and event interrupts were called together [the 2nd will then get this error])
731 
732  // since there is nothing more to do: its easy: just stop: clear all interrupt generating bits
733 
734  // Count The Errors
735  i2c_error(periph);
736 
737  // Clear Running Events
739 
740  // Mark this as a special error
741  periph->errors->last_unexpected_event++;
742 
743  // Document the current Status
744  periph->status = I2CIdle;
745 
746  // There are no transactions anymore: return
747  // further-on in this routine we need a transaction pointer: so we are not allowed to continue
748  return;
749  }
750 
751  // get the I2C transaction we were working on ...
752 
753  enum STMI2CSubTransactionStatus ret = 0;
754  struct i2c_transaction *trans = periph->trans[periph->trans_extract_idx];
755 
757  // If there was an error:
758  if ((I2C_SR1(i2c) & I2C_SR1_ERR_MASK) != 0x0000) {
759 
760 #ifdef I2C_DEBUG_LED
761  LED1_ON();
762  LED2_ON();
763  LED1_OFF();
764  LED2_OFF();
765 
766  LED_SHOW_ACTIVE_BITS(regs);
767 #endif
768 
769  // Notify everyone about the error ...
770 
771  // Set result in transaction
772  trans->status = I2CTransFailed;
773 
774  // Document the current Status
775  periph->status = I2CFailed;
776 
777  // Make sure a TxRx does not Restart
778  trans->type = I2CTransRx;
779 
780  // Count The Errors
781  i2c_error(periph);
782 
783  // Clear Running Events
785 
786  // Now continue as if everything was normal from now on
787  ret = STMI2C_SubTra_Ready;
788 
789  }
790 
792  // Normal Event:
793  else {
794 
797  //
798  // SUB-TRANSACTION HANDLER
799 
800  if (trans->type == I2CTransRx) { // TxRx are converted to Rx after the Tx Part
801  switch (trans->len_r) {
802  case 1:
803  ret = stmi2c_read1(i2c, periph, trans);
804  break;
805  case 2:
806  ret = stmi2c_read2(i2c, periph, trans);
807  break;
808  default:
809  ret = stmi2c_readmany(i2c, periph, trans);
810  break;
811  }
812  } else { // TxRx or Tx
813  ret = stmi2c_send(i2c, periph, trans);
814  }
815  }
816 
818  // Sub-transaction has finished
819  if (ret != STMI2C_SubTra_Busy) {
820  // Ready or SubTraError
821  // -ready: with or without stop already asked
822 
823  // In case of unexpected event condition during subtransaction handling:
824  if (ret == STMI2C_SubTra_Error) {
825  // Tell everyone about the subtransaction error:
826  // this is the previously called SPURRIOUS INTERRUPT
827  periph->status = I2CFailed;
828  trans->type = I2CTransRx; // Avoid possible restart
829  trans->status = I2CTransFailed; // Notify Ready
830  periph->errors->unexpected_event_cnt++;
831 
832  // Error
833 #ifdef I2C_DEBUG_LED
834  LED2_ON();
835  LED1_ON();
836  LED2_OFF();
837  LED1_OFF();
838 
839  LED_SHOW_ACTIVE_BITS(regs);
840 #endif
841 
842  // Clear Running Events
844  }
845 
846  // RxTx -> Restart and do Rx part
847  if (trans->type == I2CTransTxRx) {
848  trans->type = I2CTransRx;
849  periph->status = I2CStartRequested;
850  i2c_send_start(i2c);
851 
852  // Silent any BTF that would occur before SB
853  i2c_send_data(i2c, 0x00);
854  }
855  // If a restart is not needed: Rx part or Tx-only
856  else {
857  // Ready, no stop condition set yet
858  if (ret == STMI2C_SubTra_Ready) {
859 
860  // Program a stop
861  PPRZ_I2C_SEND_STOP(i2c);
862 
863  // Silent any BTF that would occur before STOP is executed
864  i2c_send_data(i2c, 0x00);
865  }
866 
867  // Jump to the next transaction
868  periph->trans_extract_idx++;
870  periph->trans_extract_idx = 0;
871  }
872 
873  // Tell everyone we are ready
874  periph->status = I2CIdle;
875 
876 
877  // if we have no more transaction to process, stop here
878  if (periph->trans_extract_idx == periph->trans_insert_idx) {
879 
880  periph->watchdog = -1; // stop watchdog
881 #ifdef I2C_DEBUG_LED
882  LED2_ON();
883  LED1_ON();
884  LED1_OFF();
885  LED1_ON();
886  LED1_OFF();
887  LED2_OFF();
888 #endif
889  }
890  // if not, start next transaction
891  else {
892  // Restart transaction doing the Rx part now
893  // --- moved to idle function
894  PPRZ_I2C_SEND_START(periph);
895  // ------
896  }
897  }
898  }
899 
900  return;
901 }
902 
903 
904 /*
905 // Make sure the bus is free before resetting (p722)
906 if (regs->SR2 & (I2C_FLAG_BUSY >> 16)) {
907 // Reset the I2C block
908 I2C_SoftwareResetCmd(periph->reg_addr, ENABLE);
909 I2C_SoftwareResetCmd(periph->reg_addr, DISABLE);
910 }
911 */
912 
913 
914 #if USE_I2C0
915 #error "The STM32 doesn't have I2C0, use I2C1 or I2C2"
916 #endif
917 
918 #if USE_I2C1
919 
921 #ifndef I2C1_CLOCK_SPEED
922 #define I2C1_CLOCK_SPEED 200000
923 #endif
924 PRINT_CONFIG_VAR(I2C1_CLOCK_SPEED)
925 
926 struct i2c_errors i2c1_errors;
927 
928 void i2c1_hw_init(void)
929 {
930 
931  i2c1.reg_addr = (void *)I2C1;
932  i2c1.init_struct = NULL;
933  i2c1.errors = &i2c1_errors;
934  i2c1.watchdog = -1;
935 
936  /* zeros error counter */
937  ZEROS_ERR_COUNTER(i2c1_errors);
938 
939  // Extra
940 #ifdef I2C_DEBUG_LED
941  LED_INIT();
942 #else
943 
944  /* reset peripheral to default state ( sometimes not achieved on reset :( ) */
945  //rcc_periph_reset_pulse(RST_I2C1);
946 
947  /* Configure and enable I2C1 event interrupt --------------------------------*/
948  nvic_set_priority(NVIC_I2C1_EV_IRQ, NVIC_I2C1_IRQ_PRIO);
949  nvic_enable_irq(NVIC_I2C1_EV_IRQ);
950 
951  /* Configure and enable I2C1 err interrupt ----------------------------------*/
952  nvic_set_priority(NVIC_I2C1_ER_IRQ, NVIC_I2C1_IRQ_PRIO + 1);
953  nvic_enable_irq(NVIC_I2C1_ER_IRQ);
954 
955  /* Enable peripheral clocks -------------------------------------------------*/
956  /* Enable I2C1 clock */
957  rcc_periph_clock_enable(RCC_I2C1);
958  /* setup gpio clock and pins */
959  i2c_setup_gpio(I2C1);
960 
961  rcc_periph_reset_pulse(RST_I2C1);
962 
963  // enable peripheral
964  i2c_peripheral_enable(I2C1);
965 
966  i2c_set_own_7bit_slave_address(I2C1, 0);
967 
968  // enable error interrupts
969  i2c_enable_interrupt(I2C1, I2C_CR2_ITERREN);
970 
972 #endif
973 }
974 
975 void i2c1_ev_isr(void)
976 {
977  uint32_t i2c = (uint32_t) i2c1.reg_addr;
978  i2c_disable_interrupt(i2c, I2C_CR2_ITERREN);
979  i2c1.watchdog = 0; // restart watchdog
980  i2c_irq(&i2c1);
981  i2c_enable_interrupt(i2c, I2C_CR2_ITERREN);
982 }
983 
984 void i2c1_er_isr(void)
985 {
986  uint32_t i2c = (uint32_t) i2c1.reg_addr;
987  i2c_disable_interrupt(i2c, I2C_CR2_ITEVTEN);
988  i2c1.watchdog = 0; // restart watchdog
989  i2c_irq(&i2c1);
990  i2c_enable_interrupt(i2c, I2C_CR2_ITEVTEN);
991 }
992 
993 #endif /* USE_I2C1 */
994 
995 #if USE_I2C2
996 
998 #ifndef I2C2_CLOCK_SPEED
999 #define I2C2_CLOCK_SPEED 300000
1000 #endif
1001 PRINT_CONFIG_VAR(I2C2_CLOCK_SPEED)
1002 
1003 struct i2c_errors i2c2_errors;
1004 
1005 void i2c2_hw_init(void)
1006 {
1007 
1008  i2c2.reg_addr = (void *)I2C2;
1009  i2c2.init_struct = NULL;
1010  i2c2.errors = &i2c2_errors;
1011  i2c2.watchdog = -1;
1012 
1013  /* zeros error counter */
1014  ZEROS_ERR_COUNTER(i2c2_errors);
1015 
1016  /* reset peripheral to default state ( sometimes not achieved on reset :( ) */
1017  //rcc_periph_reset_pulse(RST_I2C2);
1018 
1019  /* Configure and enable I2C2 event interrupt --------------------------------*/
1020  nvic_set_priority(NVIC_I2C2_EV_IRQ, NVIC_I2C2_IRQ_PRIO);
1021  nvic_enable_irq(NVIC_I2C2_EV_IRQ);
1022 
1023  /* Configure and enable I2C2 err interrupt ----------------------------------*/
1024  nvic_set_priority(NVIC_I2C2_ER_IRQ, NVIC_I2C2_IRQ_PRIO + 1);
1025  nvic_enable_irq(NVIC_I2C2_ER_IRQ);
1026 
1027  /* Enable peripheral clocks -------------------------------------------------*/
1028  /* Enable I2C2 clock */
1029  rcc_periph_clock_enable(RCC_I2C2);
1030 
1031  /* setup gpio clock and pins */
1032  i2c_setup_gpio(I2C2);
1033 
1034  rcc_periph_reset_pulse(RST_I2C2);
1035 
1036  // enable peripheral
1037  i2c_peripheral_enable(I2C2);
1038 
1039  i2c_set_own_7bit_slave_address(I2C2, 0);
1040 
1041  // enable error interrupts
1042  i2c_enable_interrupt(I2C2, I2C_CR2_ITERREN);
1043 
1045 }
1046 
1047 void i2c2_ev_isr(void)
1048 {
1049  uint32_t i2c = (uint32_t) i2c2.reg_addr;
1050  i2c_disable_interrupt(i2c, I2C_CR2_ITERREN);
1051  i2c2.watchdog = 0; // restart watchdog
1052  i2c_irq(&i2c2);
1053  i2c_enable_interrupt(i2c, I2C_CR2_ITERREN);
1054 }
1055 
1056 void i2c2_er_isr(void)
1057 {
1058  uint32_t i2c = (uint32_t) i2c2.reg_addr;
1059  i2c_disable_interrupt(i2c, I2C_CR2_ITEVTEN);
1060  i2c2.watchdog = 0; // restart watchdog
1061  i2c_irq(&i2c2);
1062  i2c_enable_interrupt(i2c, I2C_CR2_ITEVTEN);
1063 }
1064 
1065 #endif /* USE_I2C2 */
1066 
1067 
1068 #if USE_I2C3 && defined STM32F4
1069 
1071 #ifndef I2C3_CLOCK_SPEED
1072 #define I2C3_CLOCK_SPEED 300000
1073 #endif
1074 PRINT_CONFIG_VAR(I2C3_CLOCK_SPEED)
1075 
1076 struct i2c_errors i2c3_errors;
1077 
1078 void i2c3_hw_init(void)
1079 {
1080 
1081  i2c3.reg_addr = (void *)I2C3;
1082  i2c3.init_struct = NULL;
1083  i2c3.errors = &i2c3_errors;
1084  i2c3.watchdog = -1;
1085 
1086  /* zeros error counter */
1087  ZEROS_ERR_COUNTER(i2c3_errors);
1088 
1089  /* reset peripheral to default state ( sometimes not achieved on reset :( ) */
1090  //rcc_periph_reset_pulse(RST_I2C3);
1091 
1092  /* Configure and enable I2C3 event interrupt --------------------------------*/
1093  nvic_set_priority(NVIC_I2C3_EV_IRQ, NVIC_I2C3_IRQ_PRIO);
1094  nvic_enable_irq(NVIC_I2C3_EV_IRQ);
1095 
1096  /* Configure and enable I2C3 err interrupt ----------------------------------*/
1097  nvic_set_priority(NVIC_I2C3_ER_IRQ, NVIC_I2C3_IRQ_PRIO + 1);
1098  nvic_enable_irq(NVIC_I2C3_ER_IRQ);
1099 
1100  /* Enable peripheral clocks -------------------------------------------------*/
1101  /* Enable I2C3 clock */
1102  rcc_periph_clock_enable(RCC_I2C3);
1103 
1104  /* setup gpio clock and pins */
1105  i2c_setup_gpio(I2C3);
1106 
1107  rcc_periph_reset_pulse(RST_I2C3);
1108 
1109  // enable peripheral
1110  i2c_peripheral_enable(I2C3);
1111 
1112  i2c_set_own_7bit_slave_address(I2C3, 0);
1113 
1114  // enable error interrupts
1115  i2c_enable_interrupt(I2C3, I2C_CR2_ITERREN);
1116 
1117  i2c_setbitrate(&i2c3, I2C3_CLOCK_SPEED);
1118 }
1119 
1120 void i2c3_ev_isr(void)
1121 {
1122  uint32_t i2c = (uint32_t) i2c3.reg_addr;
1123  i2c_disable_interrupt(i2c, I2C_CR2_ITERREN);
1124  i2c3.watchdog = 0; // restart watchdog
1125  i2c_irq(&i2c3);
1126  i2c_enable_interrupt(i2c, I2C_CR2_ITERREN);
1127 }
1128 
1129 void i2c3_er_isr(void)
1130 {
1131  uint32_t i2c = (uint32_t) i2c3.reg_addr;
1132  i2c_disable_interrupt(i2c, I2C_CR2_ITEVTEN);
1133  i2c3.watchdog = 0; // restart watchdog
1134  i2c_irq(&i2c3);
1135  i2c_enable_interrupt(i2c, I2C_CR2_ITEVTEN);
1136 }
1137 
1138 #endif /* USE_I2C3 */
1139 
1141 // Set Bitrate to Match your application:
1142 // -short wires, low capacitance bus: IMU: high speed
1143 // -long wires with a lot of capacitance: motor controller: put speed as low as possible
1144 
1145 void i2c_setbitrate(struct i2c_periph *periph, int bitrate)
1146 {
1147  // If NOT Busy
1148  if (i2c_idle(periph)) {
1149  volatile int devider;
1150  volatile int risetime;
1151 
1152  uint32_t i2c = (uint32_t) periph->reg_addr;
1153 
1154  /*****************************************************
1155  Bitrate:
1156 
1157  -CR2 + CCR + TRISE registers
1158  -only change when PE=0
1159 
1160  e.g.
1161 
1162  10kHz: 36MHz + Standard 0x708 + 0x25
1163  70kHz: 36MHz + Standard 0x101 +
1164  400kHz: 36MHz + Fast 0x1E + 0xb
1165 
1166  // 1) Program peripheral input clock CR2: to get correct timings
1167  // 2) Configure clock control registers
1168  // 3) Configure rise time register
1169  ******************************************************/
1170 
1171  if (bitrate < 3000) {
1172  bitrate = 3000;
1173  }
1174 
1175  // rcc_apb1_frequency is normally configured to max: 36MHz on F1 and 42MHz on F4
1176  // in fast mode: 2counts low 1 count high -> / 3:
1177  // in standard mode: 1 count low, 1 count high -> /2:
1178  devider = (rcc_apb1_frequency / 2000) / (bitrate / 1000);
1179 
1180  // never allow faster than 600kbps
1181  if (devider < 20) {
1182  devider = 20;
1183  }
1184 
1185  // no overflow either
1186  if (devider >= 4095) {
1187  devider = 4095;
1188  }
1189 
1190  // risetime can be up to 1/6th of the period
1191  risetime = 1000000 / (bitrate / 1000) / 6 / 28;
1192 
1193  if (risetime < 10) {
1194  risetime = 10;
1195  }
1196 
1197  // more will overflow the register: for more you should lower the FREQ
1198  if (risetime >= 31) {
1199  risetime = 31;
1200  }
1201 
1202  // we do not expect an interrupt as the interface should have been idle, but just in case...
1203  __disable_irq(); // this code is in user space:
1204 
1205  // CCR can only be written when PE is disabled
1206  // p731 note 5
1207  i2c_peripheral_disable(i2c);
1208 
1209  // 1)
1210 #ifdef STM32F1
1211  i2c_set_clock_frequency(i2c, I2C_CR2_FREQ_36MHZ);
1212 #else // STM32F4
1213  i2c_set_clock_frequency(i2c, I2C_CR2_FREQ_42MHZ);
1214 #endif
1215  // 2)
1216  //i2c_set_fast_mode(i2c);
1217  i2c_set_ccr(i2c, devider);
1218  // 3)
1219  i2c_set_trise(i2c, risetime);
1220 
1221  // Re-Enable
1222  i2c_peripheral_enable(i2c);
1223 
1224  __enable_irq();
1225 
1226 #ifdef I2C_DEBUG_LED
1227  __disable_irq(); // this code is in user space:
1228 
1229  LED2_ON();
1230  LED1_ON();
1231  LED2_OFF();
1232  LED1_OFF();
1233  LED2_ON();
1234  LED1_ON();
1235  LED2_OFF();
1236  LED1_OFF();
1237 
1238  __enable_irq();
1239 #endif
1240 
1241  }
1242 }
1243 
1244 #define WD_DELAY 20 // number of ticks with 2ms - 40ms delay before resetting the bus
1245 #define WD_RECOVERY_TICKS 18 // number of generated SCL clocking pulses
1246 
1247 #if USE_I2C1 || USE_I2C2 || USE_I2C3
1248 static inline void i2c_scl_set(uint32_t i2c)
1249 {
1250 #if USE_I2C1
1251  if (i2c == I2C1) {
1253  }
1254 #endif
1255 #if USE_I2C2
1256  if (i2c == I2C2) {
1258  }
1259 #endif
1260 #if USE_I2C3
1261  if (i2c == I2C3) {
1263  }
1264 #endif
1265 }
1266 
1267 static inline void i2c_scl_toggle(uint32_t i2c)
1268 {
1269 #if USE_I2C1
1270  if (i2c == I2C1) {
1272  }
1273 #endif
1274 #if USE_I2C2
1275  if (i2c == I2C2) {
1277  }
1278 #endif
1279 #if USE_I2C3
1280  if (i2c == I2C3) {
1282  }
1283 #endif
1284 }
1285 
1286 static inline bool i2c_sda_get(uint32_t i2c)
1287 {
1288  bool res = false;
1289 #if USE_I2C1
1290  if (i2c == I2C1) {
1292  }
1293 #endif
1294 #if USE_I2C2
1295  if (i2c == I2C2) {
1297  }
1298 #endif
1299 #if USE_I2C3
1300  if (i2c == I2C3) {
1302  }
1303 #endif
1304  return res;
1305 }
1306 
1307 static void i2c_wd_check(struct i2c_periph *periph)
1308 {
1309  uint32_t i2c = (uint32_t) periph->reg_addr;
1310 
1311  if (periph->watchdog > WD_DELAY) {
1312  if (periph->watchdog == WD_DELAY + 1) {
1313 
1314  i2c_disable_interrupt(i2c, I2C_CR2_ITEVTEN);
1315  i2c_disable_interrupt(i2c, I2C_CR2_ITERREN);
1316 
1317  periph->trans_insert_idx = 0;
1318  periph->trans_extract_idx = 0;
1319  periph->status = I2CIdle;
1320  struct i2c_transaction *trans;
1321  for (uint8_t i = 0; i < I2C_TRANSACTION_QUEUE_LEN; i++) {
1322  trans = periph->trans[i];
1323  trans->status = I2CTransFailed;
1324  }
1325 
1326  i2c_peripheral_disable(i2c);
1327 
1328 #if USE_I2C1
1329  if (i2c == I2C1) {
1332  }
1333 #endif
1334 #if USE_I2C2
1335  if (i2c == I2C2) {
1338  }
1339 #endif
1340 #if USE_I2C3
1341  if (i2c == I2C3) {
1344  }
1345 #endif
1346 
1347  i2c_scl_set(i2c);
1348  } else if (periph->watchdog < WD_DELAY + WD_RECOVERY_TICKS) {
1349  if (i2c_sda_get(i2c)) {
1350  periph->watchdog = WD_DELAY + WD_RECOVERY_TICKS;
1351  }
1352  i2c_scl_toggle(i2c);
1353  } else {
1354  i2c_scl_set(i2c);
1355 
1356  /* setup gpios for normal i2c operation again */
1357  i2c_setup_gpio(i2c);
1358 
1359  i2c_reset(i2c);
1360 
1361  i2c_peripheral_enable(i2c);
1362  i2c_set_own_7bit_slave_address(i2c, 0);
1363  i2c_enable_interrupt(i2c, I2C_CR2_ITERREN);
1364 
1365 #if USE_I2C1
1366  if (i2c == I2C1) {
1368  }
1369 #endif
1370 #if USE_I2C2
1371  if (i2c == I2C2) {
1373  }
1374 #endif
1375 #if USE_I2C3
1376  if (i2c == I2C3) {
1377  i2c_setbitrate(periph, I2C3_CLOCK_SPEED);
1378  }
1379 #endif
1380 
1381  periph->watchdog = 0; // restart watchdog
1382 
1383  periph->errors->wd_reset_cnt++;
1384 
1385  return;
1386  }
1387  }
1388  if (periph->watchdog >= 0) {
1389  periph->watchdog++;
1390  }
1391 }
1392 #endif // USE_I2Cx
1393 
1394 #include "mcu_periph/sys_time.h"
1395 
1396 void i2c_event(void)
1397 {
1398  static uint32_t i2c_wd_timer;
1399 
1400  if (SysTimeTimer(i2c_wd_timer) > 2000) { // 2ms (500Hz) periodic watchdog check
1401  SysTimeTimerStart(i2c_wd_timer);
1402 #if USE_I2C1
1403  i2c_wd_check(&i2c1);
1404 #endif
1405 
1406 #if USE_I2C2
1407  i2c_wd_check(&i2c2);
1408 #endif
1409 #if USE_I2C3
1410  i2c_wd_check(&i2c3);
1411 #endif
1412  }
1413 }
1414 
1416 // Implement Interface Functions
1417 
1418 bool i2c_submit(struct i2c_periph *periph, struct i2c_transaction *t)
1419 {
1420  if (periph->watchdog > WD_DELAY) {
1421  return false;
1422  }
1423 
1424  uint8_t temp;
1425  temp = periph->trans_insert_idx + 1;
1426  if (temp >= I2C_TRANSACTION_QUEUE_LEN) { temp = 0; }
1427  if (temp == periph->trans_extract_idx) {
1428  // queue full
1429  periph->errors->queue_full_cnt++;
1430  t->status = I2CTransFailed;
1431  return false;
1432  }
1433 
1434  t->status = I2CTransPending;
1435 
1436  __disable_irq();
1437  /* put transacation in queue */
1438  periph->trans[periph->trans_insert_idx] = t;
1439  periph->trans_insert_idx = temp;
1440 
1441  /* if peripheral is idle, start the transaction */
1442  // if (PPRZ_I2C_IS_IDLE(p))
1443  if (periph->status == I2CIdle) {
1444  //if (i2c_idle(periph))
1445  {
1446 #ifdef I2C_DEBUG_LED
1447 #if USE_I2C1
1448  if (periph == &i2c1) {
1449 
1450  } else
1451 #endif
1452 #endif
1453  {
1454 #ifdef I2C_DEBUG_LED
1455  LED2_ON();
1456  LED2_OFF();
1457 #endif
1458  PPRZ_I2C_SEND_START(periph);
1459  }
1460  }
1461  }
1462  /* else it will be started by the interrupt handler when the previous transactions completes */
1463  __enable_irq();
1464 
1465  return true;
1466 }
1467 
1468 bool i2c_idle(struct i2c_periph *periph)
1469 {
1470  // This is actually a difficult function:
1471  // -simply reading the status flags can clear bits and corrupt the transaction
1472 
1473  uint32_t i2c = (uint32_t) periph->reg_addr;
1474 
1475 #ifdef I2C_DEBUG_LED
1476 #if USE_I2C1
1477  if (periph == &i2c1) {
1478  return true;
1479  }
1480 #endif
1481 #endif
1482 
1483  // First we check if the software thinks it is ready
1484  if (periph->status == I2CIdle) {
1485  return !(BIT_X_IS_SET_IN_REG(I2C_SR2_BUSY, I2C_SR2(i2c)));
1486  } else {
1487  return false;
1488  }
1489 }
static void LED2_OFF(void)
Definition: debug_led.h:18
unsigned short uint16_t
Definition: types.h:16
volatile uint16_t arb_lost_cnt
Definition: i2c.h:159
volatile uint8_t idx_buf
Definition: i2c.h:145
#define I2C_TRANSACTION_QUEUE_LEN
I2C transaction queue length.
Definition: i2c.h:133
I2C errors counter.
Definition: i2c.h:154
#define I2C3_GPIO_SCL
Definition: krooz_sd.h:134
#define I2C3_GPIO_PORT_SCL
Definition: krooz_sd.h:132
#define I2C1
Definition: LPC21xx.h:166
volatile uint16_t miss_start_stop_cnt
Definition: i2c.h:158
volatile uint8_t buf[I2C_BUF_LEN]
Transaction buffer With I2C_BUF_LEN number of bytes.
Definition: i2c.h:122
uint16_t len_r
Number of bytes to read/receive.
Definition: i2c.h:110
static void __enable_irq(void)
Definition: i2c_arch.c:66
transaction successfully finished by I2C driver
Definition: i2c.h:57
static void i2c_irq(struct i2c_periph *periph)
Definition: i2c_arch.c:634
#define I2C2_GPIO_PORT
Definition: apogee_1.0.h:214
#define I2C3_GPIO_SDA
Definition: krooz_sd.h:135
Some architecture independent helper functions for GPIOs.
transmit and receive transaction
Definition: i2c.h:49
uint8_t trans_extract_idx
Definition: i2c.h:142
#define WD_DELAY
Definition: i2c_arch.c:1244
bool i2c_idle(struct i2c_periph *p)
i2c_idle() function
Definition: i2c_arch.c:355
static void __disable_irq(void)
Definition: i2c_arch.c:65
Definition: i2c.h:66
volatile uint16_t queue_full_cnt
Definition: i2c.h:156
#define GPIOB
Definition: gpio_arch.h:35
#define BIT_X_IS_SET_IN_REG(X, REG)
Definition: i2c_arch.c:61
void i2c_setbitrate(struct i2c_periph *p, int bitrate)
i2c_setbitrate() function
Definition: i2c_arch.c:297
struct i2c_errors * errors
Definition: i2c.h:148
#define __I2C_REG_CRITICAL_ZONE_STOP
Definition: i2c_arch.c:71
#define LED_INIT(i)
Definition: led_hw.h:48
enum I2CStatus status
Definition: i2c.h:144
static enum STMI2CSubTransactionStatus stmi2c_readmany(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
Definition: i2c_arch.c:423
void gpio_setup_output(ioportid_t port, uint16_t gpios)
Setup one or more pins of the given GPIO port as outputs.
Definition: gpio_arch.c:33
volatile uint32_t er_irq_cnt
Definition: i2c.h:166
static void LED1_ON(void)
Definition: debug_led.h:3
static void gpio_toggle(ioportid_t port, uint16_t pin)
Toggle a gpio output to low level.
Definition: gpio_arch.h:113
#define I2C3_GPIO_PORT_SDA
Definition: krooz_sd.h:133
void * reg_addr
Definition: i2c.h:146
static void LED_SHOW_ACTIVE_BITS(I2C_TypeDef *regs)
Definition: debug_led.h:47
static void LED2_ON(void)
Definition: debug_led.h:13
#define I2C1_GPIO_SDA
Definition: apogee_1.0.h:212
void gpio_enable_clock(uint32_t port)
Enable the relevant clock.
Definition: gpio_arch.c:34
#define __I2C_REG_CRITICAL_ZONE_START
Definition: i2c_arch.c:70
#define I2C_SR1_ERR_MASK
Definition: i2c_arch.c:51
uint8_t len_w
Number of bytes to write/transmit.
Definition: i2c.h:116
#define NVIC_I2C1_IRQ_PRIO
Definition: i2c_arch.c:75
static void LED_ERROR(uint8_t base, uint8_t nr)
Definition: debug_led.h:37
#define ZEROS_ERR_COUNTER(_i2c_err)
Definition: i2c.h:170
static enum STMI2CSubTransactionStatus stmi2c_read2(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
Definition: i2c_arch.c:357
Architecture independent timing functions.
static void i2c_error(struct i2c_periph *periph)
Definition: i2c_arch.c:533
unsigned long uint32_t
Definition: types.h:18
struct i2c_transaction * trans[I2C_TRANSACTION_QUEUE_LEN]
Definition: i2c.h:140
volatile uint16_t over_under_cnt
Definition: i2c.h:160
bool i2c_submit(struct i2c_periph *p, struct i2c_transaction *t)
i2c_submit() function
Definition: i2c_arch.c:316
transaction failed
Definition: i2c.h:58
Definition: i2c.h:77
static enum STMI2CSubTransactionStatus stmi2c_read1(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
Definition: i2c_arch.c:298
I2C transaction structure.
Definition: i2c.h:93
enum I2CTransactionStatus status
Transaction status.
Definition: i2c.h:126
#define SysTimeTimer(_t)
Definition: sys_time.h:219
#define NVIC_I2C2_IRQ_PRIO
Definition: i2c_arch.c:76
volatile uint16_t unexpected_event_cnt
Definition: i2c.h:164
uint8_t slave_addr
Slave address.
Definition: i2c.h:104
I2C peripheral structure.
Definition: i2c.h:138
static uint8_t gpio_get(ioportid_t port, uint16_t pin)
Get level of a gpio.
Definition: gpio_arch.h:83
unsigned char uint8_t
Definition: types.h:14
STMI2CSubTransactionStatus
Definition: i2c_arch.c:217
#define NVIC_I2C3_IRQ_PRIO
Definition: i2c_arch.c:77
transmit only transaction
Definition: i2c.h:47
volatile int16_t watchdog
Definition: i2c.h:149
volatile uint32_t last_unexpected_event
Definition: i2c.h:165
#define I2C2_GPIO_SCL
Definition: apogee_1.0.h:215
static enum STMI2CSubTransactionStatus stmi2c_send(uint32_t i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
Definition: i2c_arch.c:226
#define GPIO_AF4
Definition: gpio_def.h:68
volatile uint16_t wd_reset_cnt
Definition: i2c.h:155
volatile uint16_t smbus_alert_cnt
Definition: i2c.h:163
#define WD_RECOVERY_TICKS
Definition: i2c_arch.c:1245
#define I2C2_GPIO_SDA
Definition: apogee_1.0.h:216
static void LED1_OFF(void)
Definition: debug_led.h:8
void i2c_event(void)
i2c_event() function
Definition: i2c_arch.c:289
enum I2CTransactionType type
Transaction type.
Definition: i2c.h:98
#define I2C1_CLOCK_SPEED
I2C defines.
Definition: board.h:944
#define SysTimeTimerStart(_t)
Definition: sys_time.h:218
uint8_t trans_insert_idx
Definition: i2c.h:141
volatile uint16_t pec_recep_cnt
Definition: i2c.h:161
#define I2C1_GPIO_SCL
Definition: apogee_1.0.h:211
void gpio_setup_input(ioportid_t port, uint16_t gpios)
Setup one or more pins of the given GPIO port as inputs.
Definition: gpio_arch.c:40
static void PPRZ_I2C_SEND_START(struct i2c_periph *periph)
Definition: i2c_arch.c:173
receive only transaction
Definition: i2c.h:48
#define I2C2_CLOCK_SPEED
Definition: board.h:951
static void gpio_set(ioportid_t port, uint16_t pin)
Set a gpio output to high level.
Definition: gpio_arch.h:93
transaction is pending in queue
Definition: i2c.h:55
static void stmi2c_clear_pending_interrupts(uint32_t i2c)
Definition: i2c_arch.c:597
#define I2C1_GPIO_PORT
Definition: apogee_1.0.h:210
static void PPRZ_I2C_SEND_STOP(uint32_t i2c)
Definition: i2c_arch.c:158
volatile uint16_t ack_fail_cnt
Definition: i2c.h:157
volatile uint16_t timeout_tlow_cnt
Definition: i2c.h:162
Architecture independent I2C (Inter-Integrated Circuit Bus) API.
if(PrimarySpektrumState.SpektrumTimer)