Paparazzi UAS  v5.0.5_stable-7-g4b8bbb7
Paparazzi is a free software Unmanned Aircraft System.
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i2c_arch.c
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1 /*
2  * Copyright (C) 2009-2012 The Paparazzi Team
3  *
4  * This file is part of paparazzi.
5  *
6  * paparazzi is free software; you can redistribute it and/or modify
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14  * GNU General Public License for more details.
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21  */
22 
29 #include "mcu_periph/i2c.h"
30 
31 #include BOARD_CONFIG
32 
33 #include <libopencm3/stm32/rcc.h>
34 #include <libopencm3/stm32/gpio.h>
35 #include <libopencm3/cm3/nvic.h>
36 #include <libopencm3/cm3/scb.h>
37 
38 #include "mcu_periph/gpio.h"
39 
40 
41 #ifdef I2C_DEBUG_LED
42 #include "i2c_debug_led.h"
43 #endif // I2C_DEBUG_LED
44 
47 
48 
49 // Error bit mask
50 // XXX: consider moving this define into libopencm3
51 #define I2C_SR1_ERR_MASK (I2C_SR1_SMBALERT | \
52  I2C_SR1_TIMEOUT | \
53  I2C_SR1_PECERR | \
54  I2C_SR1_OVR | \
55  I2C_SR1_AF | \
56  I2C_SR1_ARLO | \
57  I2C_SR1_BERR)
58 
59 // Bit Control
60 
61 #define BIT_X_IS_SET_IN_REG(X,REG) (((REG) & (X)) == (X))
62 
63 // disable and enable irq functions are not implemented in libopencm3 defining them here
64 // XXX: consider moving this definitions into libopencm3
65 static inline void __disable_irq(void) { asm volatile ("cpsid i"); }
66 static inline void __enable_irq(void) { asm volatile ("cpsie i"); }
67 
68 // Critical Zones
69 
70 #define __I2C_REG_CRITICAL_ZONE_START __disable_irq();
71 #define __I2C_REG_CRITICAL_ZONE_STOP __enable_irq();
72 
73 
74 static inline void PPRZ_I2C_SEND_STOP(u32 i2c)
75 {
76  // Man: p722: Stop generation after the current byte transfer or after the current Start condition is sent.
77  I2C_CR1(i2c) |= I2C_CR1_STOP;
78 
79 #ifdef I2C_DEBUG_LED
80  LED2_ON();
81  LED1_ON();
82  LED1_OFF();
83  LED2_OFF();
84 #endif
85 }
86 
87 // (RE)START
88 
89 static inline void PPRZ_I2C_SEND_START(struct i2c_periph *periph)
90 {
91  u32 i2c = (u32) periph->reg_addr;
92 
93  // Reset the buffer pointer to the first byte
94  periph->idx_buf = 0;
95 
96 #ifdef I2C_DEBUG_LED
98 
99  LED2_ON();
100  LED1_ON();
101  LED1_OFF();
102  LED1_ON();
103  LED1_OFF();
104  LED1_ON();
105  LED1_OFF();
106  LED2_OFF();
107 #endif
108 
109  // Enable Error IRQ, Event IRQ but disable Buffer IRQ
110  I2C_CR2(i2c) |= I2C_CR2_ITERREN;
111  I2C_CR2(i2c) |= I2C_CR2_ITEVTEN;
112  I2C_CR2(i2c) &= ~ I2C_CR2_ITBUFEN;
113 
114  // Issue a new start
115  I2C_CR1(i2c) = (I2C_CR1_START | I2C_CR1_PE);
116  periph->status = I2CStartRequested;
117 
118 }
119 
120 // STOP
121 
124 //
125 // SUBTRANSACTION SEQUENCES
126 // -We arrive here every time a ISR is called with no error
127 
133 };
134 
135 // Doc ID 13902 Rev 11 p 710/1072
136 // Transfer Sequence Diagram for Master Transmitter
137 static inline enum STMI2CSubTransactionStatus stmi2c_send(u32 i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
138 {
139  uint16_t SR1 = I2C_SR1(i2c);
140 
141  // Start Condition Was Just Generated
142  if (BIT_X_IS_SET_IN_REG( I2C_SR1_SB, SR1 ) )
143  {
144  // Disable buffer interrupt
145  I2C_CR2(i2c) &= ~ I2C_CR2_ITBUFEN;
146  // Send Slave address and wait for ADDR interrupt
147  I2C_DR(i2c) = trans->slave_addr;
148  // Document the current Status
149  periph->status = I2CAddrWrSent;
150  }
151  // Address Was Sent
152  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1) )
153  {
154  // Now read SR2 to clear the ADDR status Bit
155  uint16_t SR2 __attribute__ ((unused)) = I2C_SR2(i2c);
156 
157  // Maybe check we are transmitting (did not loose arbitration for instance)
158  // if (! BIT_X_IS_SET_IN_REG(I2C_SR2_TRA, SR2)) { }
159  // update: this should be caught by the ARLO error: so we will not arrive here
160 
161  // Send First max 2 bytes
162  I2C_DR(i2c) = trans->buf[0];
163  if (trans->len_w > 1)
164  {
165  I2C_DR(i2c) = trans->buf[1];
166  periph->idx_buf = 2;
167  }
168  else
169  {
170  periph->idx_buf = 1;
171  }
172 
173  // Enable buffer-space available interrupt
174  // only if there is more to send: wait for TXE, no more to send: wait for BTF
175  if ( periph->idx_buf < trans->len_w)
176  I2C_CR2(i2c) |= I2C_CR2_ITBUFEN;
177 
178  // Document the current Status
179  periph->status = I2CSendingByte;
180  }
181  // The buffer is not full anymore AND we were not waiting for BTF
182  else if ((BIT_X_IS_SET_IN_REG(I2C_SR1_TxE, SR1) ) && (BIT_X_IS_SET_IN_REG(I2C_CR2_ITBUFEN, I2C_CR2(i2c))) )
183  {
184  // Send the next byte
185  I2C_DR(i2c) = trans->buf[periph->idx_buf];
186  periph->idx_buf++;
187 
188  // All bytes Sent? Then wait for BTF instead
189  if ( periph->idx_buf >= trans->len_w)
190  {
191  // Not interested anymore to know the buffer has space left
192  I2C_CR2(i2c) &= ~ I2C_CR2_ITBUFEN;
193  // Next interrupt will be BTF (or error)
194  }
195  }
196  // BTF: means last byte was sent
197  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1) )
198  {
199  if (trans->type == I2CTransTx)
200  {
201  // Tell the driver we are ready
202  trans->status = I2CTransSuccess;
203  }
204  // Otherwise we still need to do the receiving part
205 
206  return STMI2C_SubTra_Ready;
207  }
208  else // Event Logic Error
209  {
210  return STMI2C_SubTra_Error;
211  }
212 
213  return STMI2C_SubTra_Busy;
214 }
215 
216 // Doc ID 13902 Rev 11 p 714/1072
217 // Transfer Sequence Diagram for Master Receiver for N=1
218 static inline enum STMI2CSubTransactionStatus stmi2c_read1(u32 i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
219 {
220  uint16_t SR1 = I2C_SR1(i2c);
221 
222  // Start Condition Was Just Generated
223  if (BIT_X_IS_SET_IN_REG( I2C_SR1_SB, SR1 ) )
224  {
225  I2C_CR2(i2c) &= ~ I2C_CR2_ITBUFEN;
226  I2C_DR(i2c) = trans->slave_addr | 0x01;
227 
228  // Document the current Status
229  periph->status = I2CAddrRdSent;
230  }
231  // Address Was Sent
232  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1) )
233  {
234  // First Clear the ACK bit: after the next byte we do not want new bytes
235  I2C_CR1(i2c) &= ~ I2C_CR1_POS;
236  I2C_CR1(i2c) &= ~ I2C_CR1_ACK;
237 
238  // --- next to steps MUST be executed together to avoid missing the stop
240 
241  // Only after setting ACK, read SR2 to clear the ADDR (next byte will start arriving)
242  uint16_t SR2 __attribute__ ((unused)) = I2C_SR2(i2c);
243 
244  // Schedule a Stop
245  PPRZ_I2C_SEND_STOP(i2c);
246 
248  // --- end of critical zone -----------
249 
250  // Enable the RXNE: it will trigger as soon as the 1 byte is received to get the result
251  I2C_CR2(i2c) |= I2C_CR2_ITBUFEN;
252 
253  // Document the current Status
254  periph->status = I2CReadingLastByte;
255  }
256  // As soon as there is 1 byte ready to read, we have our byte
257  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_RxNE, SR1) )
258  {
259  I2C_CR2(i2c) &= ~ I2C_CR2_ITBUFEN;
260  trans->buf[0] = I2C_DR(i2c);
261 
262  // We got all the results (stop condition might still be in progress but this is the last interrupt)
263  trans->status = I2CTransSuccess;
264 
265  // Document the current Status:
266  // -the stop was actually already requested in the previous step
267  periph->status = I2CStopRequested;
268 
270  }
271  else // Event Logic Error
272  {
273  return STMI2C_SubTra_Error;
274  }
275 
276  return STMI2C_SubTra_Busy;
277 }
278 
279 // Doc ID 13902 Rev 11 p 713/1072
280 // Transfer Sequence Diagram for Master Receiver for N=2
281 static inline enum STMI2CSubTransactionStatus stmi2c_read2(u32 i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
282 {
283  uint16_t SR1 = I2C_SR1(i2c);
284 
285  // Start Condition Was Just Generated
286  if (BIT_X_IS_SET_IN_REG( I2C_SR1_SB, SR1 ) )
287  {
288  // according to the datasheet: instantly shedule a NAK on the second received byte:
289  I2C_CR2(i2c) &= ~ I2C_CR2_ITBUFEN;
290  I2C_CR1(i2c) |= I2C_CR1_ACK;
291  I2C_CR1(i2c) |= I2C_CR1_POS;
292  I2C_DR(i2c) = trans->slave_addr | 0x01;
293 
294  // Document the current Status
295  periph->status = I2CAddrRdSent;
296  }
297  // Address Was Sent
298  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1) )
299  {
300  // --- make absolutely sure this command is not delayed too much after the previous:
301  // --- the NAK bits must be set before the first byte arrived: allow other interrupts here
303 
304  // if transfer of DR was finished already then we will get too many bytes
305  // BEFORE clearing ACK, read SR2 to clear the ADDR (next byte will start arriving)
306  // clearing ACK after the byte transfer has already started will NACK the next (2nd)
307  uint16_t SR2 __attribute__ ((unused)) = I2C_SR2(i2c);
308 
309  // NOT First Clear the ACK bit but only AFTER clearing ADDR
310  I2C_CR1(i2c) &= ~ I2C_CR1_ACK;
311 
312  // Disable the RXNE and wait for BTF
313  I2C_CR2(i2c) &= ~ I2C_CR2_ITBUFEN;
314 
316  // --- end of critical zone -----------
317 
318  // We do not set the RxE but wait for both bytes to arrive using BTF
319 
320  // Document the current Status
321  periph->status = I2CReadingByte;
322  }
323  // Receive buffer if full, master is halted: BTF
324  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1) )
325  {
326  // Stop condition MUST be set BEFORE reading the DR
327  // otherwise since there is new buffer space a new byte will be read
328  PPRZ_I2C_SEND_STOP(i2c);
329 
330  // Document the current Status
331  periph->status = I2CStopRequested;
332 
333  trans->buf[0] = I2C_DR(i2c);
334  trans->buf[1] = I2C_DR(i2c);
335 
336  // We got all the results
337  trans->status = I2CTransSuccess;
338 
340  }
341  else // Event Logic Error
342  {
343  return STMI2C_SubTra_Error;
344  }
345 
346  return STMI2C_SubTra_Busy;
347 }
348 
349 // Doc ID 13902 Rev 11 p 712/1072
350 // Transfer Sequence Diagram for Master Receiver for N>2
351 static inline enum STMI2CSubTransactionStatus stmi2c_readmany(u32 i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
352 {
353  uint16_t SR1 = I2C_SR1(i2c);
354 
355  // Start Condition Was Just Generated
356  if (BIT_X_IS_SET_IN_REG( I2C_SR1_SB, SR1 ) )
357  {
358  I2C_CR2(i2c) &= ~ I2C_CR2_ITBUFEN;
359  // The first data byte will be acked in read many so the slave knows it should send more
360  I2C_CR1(i2c) &= ~ I2C_CR1_POS;
361  I2C_CR1(i2c) |= I2C_CR1_ACK;
362  // Clear the SB flag
363  I2C_DR(i2c) = trans->slave_addr | 0x01;
364 
365  // Document the current Status
366  periph->status = I2CAddrRdSent;
367  }
368  // Address Was Sent
369  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1) )
370  {
371  periph->idx_buf = 0;
372 
373  // Enable RXNE: receive an interrupt any time a byte is available
374  // only enable if MORE than 3 bytes need to be read
375  if (periph->idx_buf < (trans->len_r - 3))
376  {
377  I2C_CR2(i2c) |= I2C_CR2_ITBUFEN;
378  }
379 
380  // ACK is still on to get more DATA
381  // Read SR2 to clear the ADDR (next byte will start arriving)
382  uint16_t SR2 __attribute__ ((unused)) = I2C_SR2(i2c);
383 
384  // Document the current Status
385  periph->status = I2CReadingByte;
386  }
387  // one or more bytes are available AND we were interested in Buffer interrupts
388  else if ( (BIT_X_IS_SET_IN_REG(I2C_SR1_RxNE, SR1) ) && (BIT_X_IS_SET_IN_REG(I2C_CR2_ITBUFEN, I2C_CR2(i2c))) )
389  {
390  // read byte until 3 bytes remain to be read (e.g. len_r = 6, -> idx=3 means idx 3,4,5 = 3 remain to be read
391  if (periph->idx_buf < (trans->len_r - 3))
392  {
393  trans->buf[periph->idx_buf] = I2C_DR(i2c);
394  periph->idx_buf ++;
395  }
396  // from : 3bytes -> last byte: do nothing
397  //
398  // finally: this was the last byte
399  else if (periph->idx_buf >= (trans->len_r - 1))
400  {
401  I2C_CR2(i2c) &= ~ I2C_CR2_ITBUFEN;
402 
403  // Last Value
404  trans->buf[periph->idx_buf] = I2C_DR(i2c);
405  periph->idx_buf ++;
406 
407  // We got all the results
408  trans->status = I2CTransSuccess;
409 
411  }
412 
413  // Check for end of transaction: start waiting for BTF instead of RXNE
414  if (periph->idx_buf < (trans->len_r - 3))
415  {
416  I2C_CR2(i2c) |= I2C_CR2_ITBUFEN;
417  }
418  else // idx >= len-3: there are 3 bytes to be read
419  {
420  // We want to halt I2C to have sufficient time to clear ACK, so:
421  // Stop listening to RXNE as it will be triggered infinitely since we did not empty the buffer
422  // on the next (second in buffer) received byte BTF will be set (buffer full and I2C halted)
423  I2C_CR2(i2c) &= ~ I2C_CR2_ITBUFEN;
424  }
425  }
426  // Buffer is full while this was not a RXNE interrupt
427  else if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1) )
428  {
429  // Now the shift register and data register contain data(n-2) and data(n-1)
430  // And I2C is halted so we have time
431 
432  // --- Make absolutely sure the next 2 I2C actions are performed with no delay
434 
435  // First we clear the ACK while the SCL is held low by BTF
436  I2C_CR1(i2c) &= ~ I2C_CR1_ACK;
437 
438  // Now that ACK is cleared we read one byte: instantly the last byte is being clocked in...
439  trans->buf[periph->idx_buf] = I2C_DR(i2c);
440  periph->idx_buf ++;
441 
442  // Now the last byte is being clocked. Stop in MUST be set BEFORE the transfer of the last byte is complete
443  PPRZ_I2C_SEND_STOP(i2c);
444 
446  // --- end of critical zone -----------
447 
448  // Document the current Status
449  periph->status = I2CStopRequested;
450 
451  // read the byte2 we had in the buffer (BTF means 2 bytes available)
452  trans->buf[periph->idx_buf] = I2C_DR(i2c);
453  periph->idx_buf ++;
454 
455  // Ask for an interrupt to read the last byte (which is normally still busy now)
456  // The last byte will be received with RXNE
457  I2C_CR2(i2c) |= I2C_CR2_ITBUFEN;
458  }
459  else // Event Logic Error
460  {
461  return STMI2C_SubTra_Error;
462  }
463 
464  return STMI2C_SubTra_Busy;
465 }
466 
468 // Restore bus conditions to normal after errors
469 
470 static inline void i2c_error(struct i2c_periph *periph)
471 {
472 #ifdef I2C_DEBUG_LED
473  uint8_t err_nr = 0;
474 #endif
475  periph->errors->er_irq_cnt;
476  if ((I2C_SR1((u32)periph->reg_addr) & I2C_SR1_AF) != 0) { /* Acknowledge failure */
477  periph->errors->ack_fail_cnt++;
478  I2C_SR1((u32)periph->reg_addr) &= ~I2C_SR1_AF;
479 #ifdef I2C_DEBUG_LED
480  err_nr = 1;
481 #endif
482  }
483  if ((I2C_SR1((u32)periph->reg_addr) & I2C_SR1_BERR) != 0) { /* Misplaced Start or Stop condition */
484  periph->errors->miss_start_stop_cnt++;
485  I2C_SR1((u32)periph->reg_addr) &= ~I2C_SR1_BERR;
486 #ifdef I2C_DEBUG_LED
487  err_nr = 2;
488 #endif
489  }
490  if ((I2C_SR1((u32)periph->reg_addr) & I2C_SR1_ARLO) != 0) { /* Arbitration lost */
491  periph->errors->arb_lost_cnt++;
492  I2C_SR1((u32)periph->reg_addr) &= ~I2C_SR1_ARLO;
493 #ifdef I2C_DEBUG_LED
494  err_nr = 3;
495 #endif
496  }
497  if ((I2C_SR1((u32)periph->reg_addr) & I2C_SR1_OVR) != 0) { /* Overrun/Underrun */
498  periph->errors->over_under_cnt++;
499  I2C_SR1((u32)periph->reg_addr) &= ~I2C_SR1_OVR;
500 #ifdef I2C_DEBUG_LED
501  err_nr = 4;
502 #endif
503  }
504  if ((I2C_SR1((u32)periph->reg_addr) & I2C_SR1_PECERR) != 0) { /* PEC Error in reception */
505  periph->errors->pec_recep_cnt++;
506  I2C_SR1((u32)periph->reg_addr) &= ~I2C_SR1_PECERR;
507 #ifdef I2C_DEBUG_LED
508  err_nr = 5;
509 #endif
510  }
511  if ((I2C_SR1((u32)periph->reg_addr) & I2C_SR1_TIMEOUT) != 0) { /* Timeout or Tlow error */
512  periph->errors->timeout_tlow_cnt++;
513  I2C_SR1((u32)periph->reg_addr) &= ~I2C_SR1_TIMEOUT;
514 #ifdef I2C_DEBUG_LED
515  err_nr = 6;
516 #endif
517  }
518  if ((I2C_SR1((u32)periph->reg_addr) & I2C_SR1_SMBALERT) != 0) { /* SMBus alert */
519  periph->errors->smbus_alert_cnt++;
520  I2C_SR1((u32)periph->reg_addr) &= ~I2C_SR1_SMBALERT;
521 #ifdef I2C_DEBUG_LED
522  err_nr = 7;
523 #endif
524  }
525 
526 #ifdef I2C_DEBUG_LED
527  LED_ERROR(20, err_nr);
528 #endif
529 
530  return;
531 }
532 
533 
534 static inline void stmi2c_clear_pending_interrupts(u32 i2c)
535 {
536  uint16_t SR1 = I2C_SR1(i2c);
537 
538  // Certainly do not wait for buffer interrupts:
539  // -------------------------------------------
540  I2C_CR2(i2c) &= ~ I2C_CR2_ITBUFEN; // Disable TXE, RXNE
541 
542  // Error interrupts are handled separately:
543  // ---------------------------------------
544 
545  // Clear Event interrupt conditions:
546  // --------------------------------
547 
548  // Start Condition Was Generated
549  if (BIT_X_IS_SET_IN_REG( I2C_SR1_SB, SR1 ) )
550  {
551  // SB: cleared by software when reading SR1 and writing to DR
552  I2C_DR(i2c) = 0x00;
553  }
554  // Address Was Sent
555  if (BIT_X_IS_SET_IN_REG(I2C_SR1_ADDR, SR1) )
556  {
557  // ADDR: Cleared by software when reading SR1 and then SR2
558  uint16_t SR2 __attribute__ ((unused)) = I2C_SR2(i2c);
559  }
560  // Byte Transfer Finished
561  if (BIT_X_IS_SET_IN_REG(I2C_SR1_BTF, SR1) )
562  {
563  // SB: cleared by software when reading SR1 and reading/writing to DR
564  uint8_t dummy __attribute__ ((unused)) = I2C_DR(i2c);
565  I2C_DR(i2c) = 0x00;
566  }
567 
568 }
569 
570 
572 // Restore bus conditions to normal after errors
573 
574 static inline void i2c_irq(struct i2c_periph *periph)
575 {
576 
577  /*
578  There are 7 possible event reasons to get here + all errors
579 
580  If IT_EV_FEN
581  -------------------------
582 
583  We are always interested in all IT_EV_FEV: all are required.
584 
585  1) SB // Start Condition Success in Master mode
586  2) ADDR // Address sent received Acknoledge
587  [ADDR10] // -- 10bit address stuff: not used
588  [STOPF] // -- only for slaves: master has no stop interrupt: not used
589  3) BTF // I2C has stopped working (it is waiting for new data, all buffers are tx_empty/rx_full)
590 
591  // Beware: using the buffered I2C has some interesting properties:
592  - in master receive mode: BTF only occurs after the 2nd received byte: after the first byte is received it is
593  in RD but the I2C can still receive a second byte. Only when the 2nd byte is received while the RxNE is 1
594  then a BTF occurs (I2C can not continue receiving bytes or they will get lost). During BTF I2C is halted (SCL held low)
595  - in master transmit mode: when writing a byte to WD, you instantly get a new TxE interrupt while the first is not
596  transmitted yet. The byte was pushed to the I2C shift register and the buffer is ready for more. You can already
597  fill new data in the buffer while the first is still being transmitted for max performance transmission.
598 
599  // Beware: besides data buffering you can/must plan several consecutive actions. You can send 2 bytes to the buffer, ask for a stop and
600  a new start in one go.
601 
602  - thanks to / because of this buffering and event sheduling there is not 1 interrupt per start / byte / stop
603  This also means you must think more in advance and a transaction could be popped from the transaction stack even before it's
604  stop condition is actually generated.
605 
606  // Beware: the order in which Status (and other register) is read determines how flags are cleared.
607  You should NOT simply read SR1 & SR2 every time
608 
609  If IT_EV_FEN AND IT_EV_BUF
610  --------------------------
611 
612  Buffer event are not always wanted and are typically switched on during longer data transfers. Make sure to turn off in time.
613 
614  4) RxNE
615  5) TxE
616 
617  --------------------------------------------------------------------------------------------------
618 
619  The STM waits indefinately (holding SCL low) for user interaction:
620  a) after a master-start (waiting for address)
621  b) after an address (waiting for data)
622  not during data sending when using buffered
623  c) after the last byte is transmitted (waiting for either stop or restart)
624  not during data receiving when using buffered
625  not after the last byte is received
626 
627  - The STM I2C stalls indefinately when a stop condition was attempted that
628  did not succeed. The BUSY flag remains on.
629  - There is no STOP interrupt.
630 
631  Caution Reading the status:
632  - Caution: this clears several flags and can start transmissions etc...
633  - Certain flags like STOP / (N)ACK need to be guaranteed to be set before
634  the transmission of the byte is finished. At higher clock rates that can be
635  quite fast: so we allow no other interrupt to be triggered in between
636  reading the status and setting all needed flags
637 
638  */
639 
640  // Here we go ...
641 
642  // Apparently we got an I2C interrupt: EVT BUF or ERR
643 
644 #ifdef I2C_DEBUG_LED
645  // Notify ISR is triggered
646  LED1_ON();
647  LED1_OFF();
648 #endif
649 
650  // Save Some Direct Access to the I2C Registers ...
651  u32 i2c = (u32) periph->reg_addr;
652 
654  // Check if we were ready ...
655  if (periph->trans_extract_idx == periph->trans_insert_idx)
656  {
657  // Nothing Left To Do
658 
659 #ifdef I2C_DEBUG_LED
660  LED2_ON();
661  LED1_ON();
662  LED2_OFF();
663  LED1_OFF();
664 
665  // no transaction and also an error?
666  LED_SHOW_ACTIVE_BITS(regs);
667 #endif
668 
669  // If we still get an interrupt but there are no more things to do
670  // (which can happen if an event was sheduled just before a bus error occurs)
671  // (or can happen if both error and event interrupts were called together [the 2nd will then get this error])
672 
673  // since there is nothing more to do: its easy: just stop: clear all interrupt generating bits
674 
675  // Count The Errors
676  i2c_error(periph);
677 
678  // Clear Running Events
680 
681  // Mark this as a special error
682  periph->errors->last_unexpected_event++;
683 
684  // Document the current Status
685  periph->status = I2CIdle;
686 
687  // There are no transactions anymore: return
688  // further-on in this routine we need a transaction pointer: so we are not allowed to continue
689  return;
690  }
691 
692  // get the I2C transaction we were working on ...
693 
694  enum STMI2CSubTransactionStatus ret = 0;
695  struct i2c_transaction* trans = periph->trans[periph->trans_extract_idx];
696 
698  // If there was an error:
699  if (( I2C_SR1(i2c) & I2C_SR1_ERR_MASK ) != 0x0000)
700  {
701 
702 #ifdef I2C_DEBUG_LED
703  LED1_ON();
704  LED2_ON();
705  LED1_OFF();
706  LED2_OFF();
707 
708  LED_SHOW_ACTIVE_BITS(regs);
709 #endif
710 
711  // Notify everyone about the error ...
712 
713  // Set result in transaction
714  trans->status = I2CTransFailed;
715 
716  // Document the current Status
717  periph->status = I2CFailed;
718 
719  // Make sure a TxRx does not Restart
720  trans->type = I2CTransRx;
721 
722  // Count The Errors
723  i2c_error(periph);
724 
725  // Clear Running Events
727 
728  // Now continue as if everything was normal from now on
729  ret = STMI2C_SubTra_Ready;
730 
731  }
732 
734  // Normal Event:
735  else
736  {
737 
740  //
741  // SUB-TRANSACTION HANDLER
742 
743  if (trans->type == I2CTransRx) // TxRx are converted to Rx after the Tx Part
744  {
745  switch (trans->len_r)
746  {
747  case 1:
748  ret = stmi2c_read1(i2c,periph,trans);
749  break;
750  case 2:
751  ret = stmi2c_read2(i2c,periph,trans);
752  break;
753  default:
754  ret = stmi2c_readmany(i2c,periph,trans);
755  break;
756  }
757  }
758  else // TxRx or Tx
759  {
760  ret = stmi2c_send(i2c,periph,trans);
761  }
762  }
763 
765  // Sub-transaction has finished
766  if (ret != STMI2C_SubTra_Busy)
767  {
768  // Ready or SubTraError
769  // -ready: with or without stop already asked
770 
771  // In case of unexpected event condition during subtransaction handling:
772  if (ret == STMI2C_SubTra_Error)
773  {
774  // Tell everyone about the subtransaction error:
775  // this is the previously called SPURRIOUS INTERRUPT
776  periph->status = I2CFailed;
777  trans->type = I2CTransRx; // Avoid possible restart
778  trans->status = I2CTransFailed; // Notify Ready
779  periph->errors->unexpected_event_cnt++;
780 
781  // Error
782 #ifdef I2C_DEBUG_LED
783  LED2_ON();
784  LED1_ON();
785  LED2_OFF();
786  LED1_OFF();
787 
788  LED_SHOW_ACTIVE_BITS(regs);
789 #endif
790 
791  // Clear Running Events
793  }
794 
795  // RxTx -> Restart and do Rx part
796  if (trans->type == I2CTransTxRx)
797  {
798  trans->type = I2CTransRx;
799  periph->status = I2CStartRequested;
800  I2C_CR1(i2c) |= I2C_CR1_START;
801 
802  // Silent any BTF that would occur before SB
803  I2C_DR(i2c) = 0x00;
804  }
805  // If a restart is not needed: Rx part or Tx-only
806  else
807  {
808  // Ready, no stop condition set yet
809  if (ret == STMI2C_SubTra_Ready)
810  {
811 
812  // Program a stop
813  PPRZ_I2C_SEND_STOP(i2c);
814 
815  // Silent any BTF that would occur before STOP is executed
816  I2C_DR(i2c) = 0x00;
817  }
818 
819  // Jump to the next transaction
820  periph->trans_extract_idx++;
822  periph->trans_extract_idx = 0;
823 
824  // Tell everyone we are ready
825  periph->status = I2CIdle;
826 
827 
828  // if we have no more transaction to process, stop here
829  if (periph->trans_extract_idx == periph->trans_insert_idx)
830  {
831 
832 #ifdef I2C_DEBUG_LED
833  LED2_ON();
834  LED1_ON();
835  LED1_OFF();
836  LED1_ON();
837  LED1_OFF();
838  LED2_OFF();
839 #endif
840  }
841  // if not, start next transaction
842  else
843  {
844  // Restart transaction doing the Rx part now
845  // --- moved to idle function
846  PPRZ_I2C_SEND_START(periph);
847  // ------
848  }
849  }
850  }
851 
852  return;
853 }
854 
855 
856 /*
857 // Make sure the bus is free before resetting (p722)
858 if (regs->SR2 & (I2C_FLAG_BUSY >> 16)) {
859 // Reset the I2C block
860 I2C_SoftwareResetCmd(periph->reg_addr, ENABLE);
861 I2C_SoftwareResetCmd(periph->reg_addr, DISABLE);
862 }
863 */
864 
865 
866 #ifdef USE_I2C0
867 #error "The STM32 doesn't have I2C0, use I2C1 or I2C2"
868 #endif
869 
870 #ifdef USE_I2C1
871 
873 #ifndef I2C1_CLOCK_SPEED
874 #define I2C1_CLOCK_SPEED 200000
875 #endif
876 PRINT_CONFIG_VAR(I2C1_CLOCK_SPEED)
877 
878 struct i2c_errors i2c1_errors;
879 volatile uint32_t i2c1_watchdog_counter;
880 
881 void i2c1_hw_init(void) {
882 
883  i2c1.reg_addr = (void *)I2C1;
884  i2c1.init_struct = NULL;
885  i2c1.errors = &i2c1_errors;
886  i2c1_watchdog_counter = 0;
887 
888  /* zeros error counter */
889  ZEROS_ERR_COUNTER(i2c1_errors);
890 
891  // Extra
892 #ifdef I2C_DEBUG_LED
893  LED_INIT();
894 #else
895 
896  /* reset peripheral to default state ( sometimes not achieved on reset :( ) */
897  //i2c_reset(I2C1);
898 
899  /* Configure priority grouping 0 bits for pre-emption priority and 4 bits for sub-priority. */
900  scb_set_priority_grouping(SCB_AIRCR_PRIGROUP_NOGROUP_SUB16);
901 
902  /* Configure and enable I2C1 event interrupt --------------------------------*/
903  nvic_set_priority(NVIC_I2C1_EV_IRQ, 0);
904  nvic_enable_irq(NVIC_I2C1_EV_IRQ);
905 
906  /* Configure and enable I2C1 err interrupt ----------------------------------*/
907  nvic_set_priority(NVIC_I2C1_ER_IRQ, 1);
908  nvic_enable_irq(NVIC_I2C1_ER_IRQ);
909 
910  /* Enable peripheral clocks -------------------------------------------------*/
911  /* Enable I2C1 clock */
912  rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_I2C1EN);
913  /* Enable GPIO clock */
915 #if defined(STM32F1)
916  gpio_set_mode(I2C1_GPIO_PORT, GPIO_MODE_OUTPUT_2_MHZ,
917  GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN,
919 #elif defined(STM32F4)
920  gpio_mode_setup(I2C1_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE,
922  gpio_set_output_options(GPIOB, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ,
924  gpio_set_af(I2C1_GPIO_PORT, GPIO_AF4, I2C1_GPIO_SCL | I2C1_GPIO_SDA);
925 #endif
926 
927  i2c_reset(I2C1);
928 
929  // enable peripheral
930  i2c_peripheral_enable(I2C1);
931 
932  /*
933  * XXX: there is a function to do that already in libopencm3 but I am not
934  * sure if it is correct, using direct register instead (esden)
935  */
936  //i2c_set_own_7bit_slave_address(I2C1, 0);
937  I2C_OAR1(I2C1) = 0 | 0x4000;
938 
939  // enable error interrupts
940  I2C_CR2(I2C1) |= I2C_CR2_ITERREN;
941 
942  i2c_setbitrate(&i2c1, I2C1_CLOCK_SPEED);
943 #endif
944 }
945 
946 void i2c1_ev_isr(void) {
947  u32 i2c = (u32) i2c1.reg_addr;
948  I2C_CR2(i2c) &= ~I2C_CR2_ITERREN;
949  i2c_irq(&i2c1);
950  i2c1_watchdog_counter = 0;
951  I2C_CR2(i2c) |= I2C_CR2_ITERREN;
952 }
953 
954 void i2c1_er_isr(void) {
955  u32 i2c = (u32) i2c1.reg_addr;
956  I2C_CR2(i2c) &= ~I2C_CR2_ITEVTEN;
957  i2c_irq(&i2c1);
958  i2c1_watchdog_counter = 0;
959  I2C_CR2(i2c) |= I2C_CR2_ITEVTEN;
960 }
961 
962 #endif /* USE_I2C1 */
963 
964 #ifdef USE_I2C2
965 
967 #ifndef I2C2_CLOCK_SPEED
968 #define I2C2_CLOCK_SPEED 300000
969 #endif
970 PRINT_CONFIG_VAR(I2C2_CLOCK_SPEED)
971 
972 struct i2c_errors i2c2_errors;
973 volatile uint32_t i2c2_watchdog_counter;
974 
975 void i2c2_hw_init(void) {
976 
977  i2c2.reg_addr = (void *)I2C2;
978  i2c2.init_struct = NULL;
979  i2c2.errors = &i2c2_errors;
980  i2c2_watchdog_counter = 0;
981 
982  /* zeros error counter */
983  ZEROS_ERR_COUNTER(i2c2_errors);
984 
985  /* reset peripheral to default state ( sometimes not achieved on reset :( ) */
986  //i2c_reset(I2C2);
987 
988  /* Configure priority grouping 0 bits for pre-emption priority and 4 bits for sub-priority. */
989  scb_set_priority_grouping(SCB_AIRCR_PRIGROUP_NOGROUP_SUB16);
990 
991  /* Configure and enable I2C2 event interrupt --------------------------------*/
992  nvic_set_priority(NVIC_I2C2_EV_IRQ, 0);
993  nvic_enable_irq(NVIC_I2C2_EV_IRQ);
994 
995  /* Configure and enable I2C2 err interrupt ----------------------------------*/
996  nvic_set_priority(NVIC_I2C2_ER_IRQ, 1);
997  nvic_enable_irq(NVIC_I2C2_ER_IRQ);
998 
999  /* Enable peripheral clocks -------------------------------------------------*/
1000  /* Enable I2C2 clock */
1001  rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_I2C2EN);
1002  /* Enable GPIO clock */
1004 #if defined(STM32F1)
1005  gpio_set_mode(I2C2_GPIO_PORT, GPIO_MODE_OUTPUT_2_MHZ,
1006  GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN,
1008 #elif defined(STM32F4)
1009  gpio_mode_setup(I2C2_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE,
1011  gpio_set_output_options(I2C2_GPIO_PORT, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ,
1013  gpio_set_af(I2C2_GPIO_PORT, GPIO_AF4,
1015 #endif
1016 
1017  i2c_reset(I2C2);
1018 
1019  // enable peripheral
1020  i2c_peripheral_enable(I2C2);
1021 
1022  /*
1023  * XXX: there is a function to do that already in libopencm3 but I am not
1024  * sure if it is correct, using direct register instead (esden)
1025  */
1026  //i2c_set_own_7bit_slave_address(I2C2, 0);
1027  I2C_OAR1(I2C2) = 0 | 0x4000;
1028 
1029  // enable error interrupts
1030  I2C_CR2(I2C2) |= I2C_CR2_ITERREN;
1031 
1032  i2c_setbitrate(&i2c2, I2C2_CLOCK_SPEED);
1033 }
1034 
1035 void i2c2_ev_isr(void) {
1036  u32 i2c = (u32) i2c2.reg_addr;
1037  I2C_CR2(i2c) &= ~I2C_CR2_ITERREN;
1038  i2c_irq(&i2c2);
1039  i2c2_watchdog_counter = 0;
1040  I2C_CR2(i2c) |= I2C_CR2_ITERREN;
1041 }
1042 
1043 void i2c2_er_isr(void) {
1044  u32 i2c = (u32) i2c2.reg_addr;
1045  I2C_CR2(i2c) &= ~I2C_CR2_ITEVTEN;
1046  i2c_irq(&i2c2);
1047  i2c2_watchdog_counter = 0;
1048  I2C_CR2(i2c) |= I2C_CR2_ITEVTEN;
1049 }
1050 
1051 #endif /* USE_I2C2 */
1052 
1053 
1054 #if defined USE_I2C3 && defined STM32F4
1055 
1057 #ifndef I2C3_CLOCK_SPEED
1058 #define I2C3_CLOCK_SPEED 300000
1059 #endif
1060 PRINT_CONFIG_VAR(I2C3_CLOCK_SPEED)
1061 
1062 struct i2c_errors i2c3_errors;
1063 volatile uint32_t i2c3_watchdog_counter;
1064 
1065 void i2c3_hw_init(void) {
1066 
1067  i2c3.reg_addr = (void *)I2C3;
1068  i2c3.init_struct = NULL;
1069  i2c3.errors = &i2c3_errors;
1070  i2c3_watchdog_counter = 0;
1071 
1072  /* zeros error counter */
1073  ZEROS_ERR_COUNTER(i2c3_errors);
1074 
1075  /* reset peripheral to default state ( sometimes not achieved on reset :( ) */
1076  //i2c_reset(I2C3);
1077 
1078  /* Configure priority grouping 0 bits for pre-emption priority and 4 bits for sub-priority. */
1079  scb_set_priority_grouping(SCB_AIRCR_PRIGROUP_NOGROUP_SUB16);
1080 
1081  /* Configure and enable I2C3 event interrupt --------------------------------*/
1082  nvic_set_priority(NVIC_I2C3_EV_IRQ, 0);
1083  nvic_enable_irq(NVIC_I2C3_EV_IRQ);
1084 
1085  /* Configure and enable I2C3 err interrupt ----------------------------------*/
1086  nvic_set_priority(NVIC_I2C3_ER_IRQ, 1);
1087  nvic_enable_irq(NVIC_I2C3_ER_IRQ);
1088 
1089  /* Enable peripheral clocks -------------------------------------------------*/
1090  /* Enable I2C3 clock */
1091  rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_I2C3EN);
1092  /* Enable GPIO clock */
1093  gpio_enable_clock(I2C3_GPIO_PORT_SCL);
1094  gpio_mode_setup(I2C3_GPIO_PORT_SCL, GPIO_MODE_AF, GPIO_PUPD_NONE, I2C3_GPIO_SCL);
1095  gpio_set_output_options(I2C3_GPIO_PORT_SCL, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ,
1096  I2C3_GPIO_SCL);
1097  gpio_set_af(I2C3_GPIO_PORT_SCL, GPIO_AF4, I2C3_GPIO_SCL);
1098 
1099  gpio_enable_clock(I2C3_GPIO_PORT_SDA);
1100  gpio_mode_setup(I2C3_GPIO_PORT_SDA, GPIO_MODE_AF, GPIO_PUPD_NONE, I2C3_GPIO_SDA);
1101  gpio_set_output_options(I2C3_GPIO_PORT_SDA, GPIO_OTYPE_OD, GPIO_OSPEED_25MHZ,
1102  I2C3_GPIO_SDA);
1103  gpio_set_af(I2C3_GPIO_PORT_SDA, GPIO_AF4, I2C3_GPIO_SDA);
1104 
1105  i2c_reset(I2C3);
1106 
1107  // enable peripheral
1108  i2c_peripheral_enable(I2C3);
1109 
1110  /*
1111  * XXX: there is a function to do that already in libopencm3 but I am not
1112  * sure if it is correct, using direct register instead (esden)
1113  */
1114  //i2c_set_own_7bit_slave_address(I2C3, 0);
1115  I2C_OAR1(I2C3) = 0 | 0x4000;
1116 
1117  // enable error interrupts
1118  I2C_CR2(I2C3) |= I2C_CR2_ITERREN;
1119 
1120  i2c_setbitrate(&i2c3, I2C3_CLOCK_SPEED);
1121 }
1122 
1123 void i2c3_ev_isr(void) {
1124  u32 i2c = (u32) i2c3.reg_addr;
1125  I2C_CR2(i2c) &= ~I2C_CR2_ITERREN;
1126  i2c_irq(&i2c3);
1127  i2c3_watchdog_counter = 0;
1128  I2C_CR2(i2c) |= I2C_CR2_ITERREN;
1129 }
1130 
1131 void i2c3_er_isr(void) {
1132  u32 i2c = (u32) i2c3.reg_addr;
1133  I2C_CR2(i2c) &= ~I2C_CR2_ITEVTEN;
1134  i2c_irq(&i2c3);
1135  i2c3_watchdog_counter = 0;
1136  I2C_CR2(i2c) |= I2C_CR2_ITEVTEN;
1137 }
1138 
1139 #endif /* USE_I2C3 */
1140 
1142 // Set Bitrate to Match your application:
1143 // -short wires, low capacitance bus: IMU: high speed
1144 // -long wires with a lot of capacitance: motor controller: put speed as low as possible
1145 
1146 void i2c_setbitrate(struct i2c_periph *periph, int bitrate)
1147 {
1148  // If NOT Busy
1149  if (i2c_idle(periph))
1150  {
1151  volatile int devider;
1152  volatile int risetime;
1153 
1154  u32 i2c = (u32) periph->reg_addr;
1155 
1156  /*****************************************************
1157  Bitrate:
1158 
1159  -CR2 + CCR + TRISE registers
1160  -only change when PE=0
1161 
1162  e.g.
1163 
1164  10kHz: 36MHz + Standard 0x708 + 0x25
1165  70kHz: 36MHz + Standard 0x101 +
1166  400kHz: 36MHz + Fast 0x1E + 0xb
1167 
1168  // 1) Program peripheral input clock CR2: to get correct timings
1169  // 2) Configure clock control registers
1170  // 3) Configure rise time register
1171  ******************************************************/
1172 
1173  if (bitrate < 3000)
1174  bitrate = 3000;
1175 
1176  // 36MHz, fast scl: 2counts low 1 count high -> / 3:
1177  devider = 18000 / (bitrate/1000);
1178 
1179  // never allow faster than 600kbps
1180  if (devider < 20)
1181  devider = 20;
1182 
1183  // no overflow either
1184  if (devider >=4095)
1185  devider = 4095;
1186 
1187  // risetime can be up to 1/6th of the period
1188  risetime = 1000000 / (bitrate/1000) / 6 / 28;
1189 
1190  if (risetime < 10)
1191  risetime = 10;
1192 
1193  // more will overflow the register: for more you should lower the FREQ
1194  if (risetime >=31)
1195  risetime = 31;
1196 
1197  // we do not expect an interrupt as the interface should have been idle, but just in case...
1198  __disable_irq(); // this code is in user space:
1199 
1200  // CCR can only be written when PE is disabled
1201  // p731 note 5
1202  I2C_CR1(i2c) &= ~ I2C_CR1_PE;
1203 
1204  // 1)
1205  I2C_CR2(i2c) = 0x0324;
1206  // 2)
1207  //I2C_CCR(i2c) = 0x8000 + devider;
1208  I2C_CCR(i2c) = 0x0000 + devider;
1209  // 3)
1210  I2C_TRISE(i2c) = risetime;
1211 
1212  // Re-Enable
1213  I2C_CR1(i2c) |= I2C_CR1_PE;
1214 
1215  __enable_irq();
1216 
1217 #ifdef I2C_DEBUG_LED
1218  __disable_irq(); // this code is in user space:
1219 
1220  LED2_ON();
1221  LED1_ON();
1222  LED2_OFF();
1223  LED1_OFF();
1224  LED2_ON();
1225  LED1_ON();
1226  LED2_OFF();
1227  LED1_OFF();
1228 
1229  __enable_irq();
1230 #endif
1231 
1232  }
1233 }
1234 
1235 
1237 void i2c_event(void)
1238 {
1239 #ifdef USE_I2C1
1240  i2c1_watchdog_counter++;
1241 #endif
1242 
1243 #ifdef USE_I2C2
1244  i2c2_watchdog_counter++;
1245 
1246  if (i2c2_watchdog_counter > 10000)
1247  {
1248  i2c2.errors->timeout_tlow_cnt++;
1249  i2c2_watchdog_counter = 0;
1250  }
1251 
1252 
1253 #ifdef I2C_DEBUG_LED
1254  if (i2c2_watchdog_counter == 0)
1255  {
1256  __disable_irq();
1257 
1258  LED2_ON();
1259  LED1_ON();
1260  LED1_OFF();
1261  LED1_ON();
1262  LED1_OFF();
1263  LED1_ON();
1264  LED1_OFF();
1265  LED1_ON();
1266  LED1_OFF();
1267  if (i2c2.status == I2CIdle)
1268  {
1269  LED1_ON();
1270  LED1_OFF();
1271  }
1272  else if (i2c2.status == I2CStartRequested)
1273  {
1274  LED1_ON();
1275  LED1_OFF();
1276  LED1_ON();
1277  LED1_OFF();
1278 
1279  }
1280  LED2_OFF();
1281 
1282  //regs = (I2C_TypeDef *) i2c2.reg_addr;
1283  //LED_SHOW_ACTIVE_BITS(regs);
1284 
1285  __enable_irq();
1286  }
1287 #endif
1288 
1289 
1290  //if (i2c2.status == I2CIdle)
1291  {
1292  //if (i2c_idle(&i2c2))
1293  {
1294  //__disable_irq();
1295  // More work to do
1296  //if (i2c2.trans_extract_idx != i2c2.trans_insert_idx)
1297  {
1298  // Restart transaction doing the Rx part now
1299  //PPRZ_I2C_SEND_START(&i2c2);
1300  }
1301  //__enable_irq();
1302  }
1303  }
1304 #endif
1305 
1306 #ifdef USE_I2C3
1307  i2c3_watchdog_counter++;
1308 #endif
1309 }
1310 
1312 // Implement Interface Functions
1313 
1314 bool_t i2c_submit(struct i2c_periph* periph, struct i2c_transaction* t) {
1315 
1316  uint8_t temp;
1317  temp = periph->trans_insert_idx + 1;
1318  if (temp >= I2C_TRANSACTION_QUEUE_LEN) temp = 0;
1319  if (temp == periph->trans_extract_idx)
1320  return FALSE; // queue full
1321 
1322  t->status = I2CTransPending;
1323 
1324  __disable_irq();
1325  /* put transacation in queue */
1326  periph->trans[periph->trans_insert_idx] = t;
1327  periph->trans_insert_idx = temp;
1328 
1329  /* if peripheral is idle, start the transaction */
1330  // if (PPRZ_I2C_IS_IDLE(p))
1331  if (periph->status == I2CIdle)
1332  {
1333  //if (i2c_idle(periph))
1334  {
1335 #ifdef I2C_DEBUG_LED
1336 #ifdef USE_I2C1
1337  if (periph == &i2c1)
1338  {
1339 
1340  }
1341  else
1342 #endif
1343 #endif
1344  {
1345 #ifdef I2C_DEBUG_LED
1346  LED2_ON();
1347  LED2_OFF();
1348 #endif
1349  PPRZ_I2C_SEND_START(periph);
1350  }
1351  }
1352  }
1353  /* else it will be started by the interrupt handler when the previous transactions completes */
1354  __enable_irq();
1355 
1356  return TRUE;
1357 }
1358 
1359 bool_t i2c_idle(struct i2c_periph* periph)
1360 {
1361  // This is actually a difficult function:
1362  // -simply reading the status flags can clear bits and corrupt the transaction
1363 
1364  u32 i2c = (u32) periph->reg_addr;
1365 
1366 #ifdef I2C_DEBUG_LED
1367 #ifdef USE_I2C1
1368  if (periph == &i2c1)
1369  {
1370  return TRUE;
1371  }
1372 #endif
1373 #endif
1374 
1375  // First we check if the software thinks it is ready
1376  if (periph->status == I2CIdle)
1377  return ! (BIT_X_IS_SET_IN_REG( I2C_SR2_BUSY, I2C_SR2(i2c) ) );
1378  else
1379  return FALSE;
1380 }
static void LED2_OFF(void)
Definition: debug_led.h:18
unsigned short uint16_t
Definition: types.h:16
#define I2C_TRANSACTION_QUEUE_LEN
Definition: i2c.h:87
bool_t i2c_submit(struct i2c_periph *p, struct i2c_transaction *t)
Definition: i2c_arch.c:333
#define I2C1
Definition: LPC21xx.h:166
static void __enable_irq(void)
Definition: i2c_arch.c:66
void * reg_addr
Definition: i2c.h:98
uint8_t trans_extract_idx
Definition: i2c.h:94
volatile uint16_t ack_fail_cnt
Definition: i2c.h:105
static void i2c_irq(struct i2c_periph *periph)
Definition: i2c_arch.c:574
Some architecture independent helper functions for GPIOs.
static void stmi2c_clear_pending_interrupts(u32 i2c)
Definition: i2c_arch.c:534
static enum STMI2CSubTransactionStatus stmi2c_read1(u32 i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
Definition: i2c_arch.c:218
#define I2C1_GPIO_SDA
Definition: apogee_0.99.h:148
static void PPRZ_I2C_SEND_STOP(u32 i2c)
Definition: i2c_arch.c:74
static void __disable_irq(void)
Definition: i2c_arch.c:65
static enum STMI2CSubTransactionStatus stmi2c_send(u32 i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
Definition: i2c_arch.c:137
Definition: i2c.h:59
#define BIT_X_IS_SET_IN_REG(X, REG)
Definition: i2c_arch.c:61
void i2c_setbitrate(struct i2c_periph *p, int bitrate)
Definition: i2c_arch.c:366
#define __I2C_REG_CRITICAL_ZONE_STOP
Definition: i2c_arch.c:71
static void LED1_ON(void)
Definition: debug_led.h:3
if(PrimarySpektrumState.SpektrumTimer)--PrimarySpektrumState.SpektrumTimer
volatile uint8_t idx_buf
Definition: i2c.h:97
enum I2CStatus status
Definition: i2c.h:96
uint8_t slave_addr
Definition: i2c.h:79
#define FALSE
Definition: imu_chimu.h:141
static void LED_SHOW_ACTIVE_BITS(I2C_TypeDef *regs)
Definition: debug_led.h:48
volatile uint16_t smbus_alert_cnt
Definition: i2c.h:111
static void LED2_ON(void)
Definition: debug_led.h:13
#define I2C2_GPIO_SCL
Definition: apogee_0.99.h:151
volatile uint16_t timeout_tlow_cnt
Definition: i2c.h:110
#define __I2C_REG_CRITICAL_ZONE_START
Definition: i2c_arch.c:70
#define I2C_SR1_ERR_MASK
Definition: i2c_arch.c:51
static void LED_ERROR(uint8_t base, uint8_t nr)
Definition: debug_led.h:37
#define ZEROS_ERR_COUNTER(_i2c_err)
Definition: i2c.h:128
#define I2C1_GPIO_PORT
Definition: apogee_0.99.h:146
volatile uint16_t miss_start_stop_cnt
Definition: i2c.h:106
static void i2c_error(struct i2c_periph *periph)
Definition: i2c_arch.c:470
unsigned long uint32_t
Definition: types.h:18
volatile uint16_t unexpected_event_cnt
Definition: i2c.h:112
Definition: i2c.h:70
enum I2CTransactionStatus status
Definition: i2c.h:83
void gpio_enable_clock(uint32_t port)
volatile uint16_t over_under_cnt
Definition: i2c.h:108
volatile uint16_t pec_recep_cnt
Definition: i2c.h:109
#define I2C1_GPIO_SCL
Definition: apogee_0.99.h:147
#define TRUE
Definition: imu_chimu.h:144
volatile uint32_t er_irq_cnt
Definition: i2c.h:114
volatile uint8_t buf[I2C_BUF_LEN]
Definition: i2c.h:82
uint8_t len_w
Definition: i2c.h:81
uint16_t len_r
Definition: i2c.h:80
unsigned char uint8_t
Definition: types.h:14
static enum STMI2CSubTransactionStatus stmi2c_read2(u32 i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
Definition: i2c_arch.c:281
STMI2CSubTransactionStatus
Definition: i2c_arch.c:128
volatile uint16_t arb_lost_cnt
Definition: i2c.h:107
uint8_t trans_insert_idx
Definition: i2c.h:93
#define LED_INIT(i)
Definition: led_hw.h:26
struct i2c_errors * errors
Definition: i2c.h:100
Definition: i2c.h:90
#define I2C2_GPIO_PORT
Definition: apogee_0.99.h:150
Definition: i2c.h:45
enum I2CTransactionType type
Definition: i2c.h:78
static void LED1_OFF(void)
Definition: debug_led.h:8
void i2c_event(void)
Definition: i2c_arch.c:364
static enum STMI2CSubTransactionStatus stmi2c_readmany(u32 i2c, struct i2c_periph *periph, struct i2c_transaction *trans)
Definition: i2c_arch.c:351
static void PPRZ_I2C_SEND_START(struct i2c_periph *periph)
Definition: i2c_arch.c:89
Definition: i2c.h:46
bool_t i2c_idle(struct i2c_periph *p)
Definition: i2c_arch.c:329
volatile uint32_t last_unexpected_event
Definition: i2c.h:113
struct i2c_transaction * trans[I2C_TRANSACTION_QUEUE_LEN]
Definition: i2c.h:92
#define I2C2_GPIO_SDA
Definition: apogee_0.99.h:152
Architecture independent I2C (Inter-Integrated Circuit Bus) API.