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spi_slave_hs_arch.c
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1 /*
2  * Copyright (C) 2011 The Paparazzi Team
3  *
4  * This file is part of paparazzi.
5  *
6  * paparazzi is free software; you can redistribute it and/or modify
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13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
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20  */
21 
29 #include "spi_slave_hs_arch.h"
30 #include "mcu_periph/spi.h"
31 
32 #include BOARD_CONFIG
33 #include "interrupt_hw.h"
34 #include "std.h"
35 #include "mcu.h"
36 #include "led.h"
37 #include "LPC21xx.h"
38 #include "ssp_hw.h"
39 #include "pprz_debug.h"
40 #include "armVIC.h"
41 
42 
43 /* High Speed SPI Slave Circular Buffer */
48 
49 /* Prototypes */
50 static void SSP_ISR(void) __attribute__((naked));
51 
52 /* SSPCR0 settings */
53 #define SSP_DDS 0x07 << 0 /* data size : 8 bits */
54 //#define SSP_DDS 0x0F << 0 /* data size : 16 bits */
55 #define SSP_FRF 0x00 << 4 /* frame format : SPI */
56 #define SSP_CPOL 0x00 << 6 /* clock polarity : data captured on first clock transition */
57 #define SSP_CPHA 0x00 << 7 /* clock phase : SCK idles low */
58 #define SSP_SCR 0x00 << 8 /* serial clock rate : divide by 1 */
59 
60 #define SSPCR0_VAL (SSP_DDS | SSP_FRF | SSP_CPOL | SSP_CPHA | SSP_SCR )
61 
62 /* SSPCR1 settings */
63 #define SSP_LBM 0x00 << 0 /* loopback mode : disabled */
64 #define SSP_SSE 0x00 << 1 /* SSP enable : enable later when init ready */
65 #define SSP_MS 0x01 << 2 /* master slave mode : slave */
66 #define SSP_SOD 0x00 << 3 /* slave output disable : don't care when master */
67 
68 #define SSPCR1_VAL (SSP_LBM | SSP_SSE | SSP_MS | SSP_SOD )
69 
70 /* SSPCPSR settings
71  * min value as master: 2
72  * min value as slave: 12
73  */
74 #if (PCLK == 15000000)
75 #define CPSDVSR 12
76 #else
77 
78 #if (PCLK == 30000000)
79 #define CPSDVSR 24
80 #else
81 
82 #if (PCLK == 60000000)
83 #define CPSDVSR 28
84 #else
85 
86 #error unknown PCLK frequency
87 #endif
88 #endif
89 #endif
90 
91 #define SSP_PINSEL1_SCK (2<<2)
92 #define SSP_PINSEL1_MISO (2<<4)
93 #define SSP_PINSEL1_MOSI (2<<6)
94 #define SSP_PINSEL1_SSEL (2<<8)
95 
96 
97 #define SSP_Write(X) SSPDR=(X)
98 #define SSP_Read() SSPDR
99 #define SSP_Status() SSPSR
100 
102 #ifndef SPI1_VIC_SLOT
103 #define SPI1_VIC_SLOT 7
104 #endif
105 
106 
107 void spi_slave_hs_init(void) {
108 
109  /* setup pins for SSP (SCK, MISO, MOSI) */
111 
112  /* setup SSP */
113  // Control Registers
114  SSPCR0 = SSPCR0_VAL;
115  SSPCR1 = SSPCR1_VAL;
116  // Clock Prescale Registers
117  SSPCPSR = CPSDVSR;
118 
119  /* initialize interrupt vector */
120  VICIntSelect &= ~VIC_BIT( VIC_SPI1 ); /* SPI1 selected as IRQ */
121  VICIntEnable = VIC_BIT( VIC_SPI1 ); /* enable it */
123  _VIC_ADDR(SPI1_VIC_SLOT) = (uint32_t)SSP_ISR; /* address of the ISR */
124 
125 
126  // Enable SPI Slave
127  SetBit(SSPCR1, SSE);
128 
129  // Enable Receive interrupt
130  SetBit(SSPIMSC, RXIM);
131 
132 }
133 
134 /*
135  * SSP Status:
136  *
137  * ROVR Read Overrun
138  * WCOL Write Collision (send new byte during a transfer in progress
139  * ABRT SSEL inactive before end of transfer
140  *
141  *
142  */
143 
144 
145 static void SSP_ISR(void) {
146  ISR_ENTRY();
147 
148  //LED_TOGGLE(3);
149 
150  // If any TX bytes are pending
152  {
155  SSP_Write(ret);
156  }
157  else
158  {
159  SSP_Write(0x00);
160  }
161 
162 
163  //do
164  {
165  uint16_t temp;
166 
167  // calc next insert index & store character
170 
171  // check for more room in queue
172  if (temp != spi_slave_hs_rx_extract_idx)
173  spi_slave_hs_rx_insert_idx = temp; // update insert index
174 
175  // else overrun
176  }
177  // while FIFO not empty
178  //while (SSPSR & RNE);
179 
180 /*
181  // loop until not more interrupt sources
182  while (((iid = U0IIR) & UIIR_NO_INT) == 0)
183  while (U0LSR & ULSR_THRE)
184  {
185  // check if more data to send
186  if (uart0_tx_insert_idx != uart0_tx_extract_idx)
187  {
188  U0THR = uart0_tx_buffer[uart0_tx_extract_idx];
189  uart0_tx_extract_idx++;
190  uart0_tx_extract_idx %= UART0_TX_BUFFER_SIZE;
191  }
192  else
193  {
194  // no
195  uart0_tx_running = 0; // clear running flag
196  break;
197  }
198  }
199 
200 */
201  VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
202  ISR_EXIT();
203 }
204 
#define VICIntSelect
Definition: LPC21xx.h:430
#define SPI1_VIC_SLOT
default initial settings
unsigned short uint16_t
Definition: types.h:16
#define SSPCPSR
Definition: LPC21xx.h:226
#define _VIC_CNTL(idx)
Definition: armVIC.h:19
#define SSPCR0_VAL
uint8_t spi_slave_hs_rx_buffer[SPI_SLAVE_HS_RX_BUFFER_SIZE]
#define RXIM
Definition: LPC21xx.h:273
#define SSPCR1_VAL
void spi_slave_hs_init(void)
#define SSP_PINSEL1_SSEL
#define SSPCR0
Definition: LPC21xx.h:222
uint16_t spi_slave_hs_rx_extract_idx
#define _VIC_ADDR(idx)
Definition: armVIC.h:20
Architecture independent SPI (Serial Peripheral Interface) API.
#define SSP_PINSEL1_SCK
#define SSP_Write(X)
#define SPI_SLAVE_HS_TX_BUFFER_SIZE
#define VICVectAddr
Definition: LPC21xx.h:436
unsigned long uint32_t
Definition: types.h:18
static void SSP_ISR(void)
uint8_t spi_slave_hs_tx_extract_idx
#define VIC_BIT(chan)
Definition: lpcVIC.h:105
uint8_t spi_slave_hs_tx_insert_idx
Arch independent mcu ( Micro Controller Unit ) utilities.
#define SPI_SLAVE_HS_RX_BUFFER_SIZE
unsigned char uint8_t
Definition: types.h:14
uint8_t spi_slave_hs_tx_buffer[SPI_SLAVE_HS_TX_BUFFER_SIZE]
#define ISR_EXIT()
Definition: armVIC.h:61
#define VICIntEnable
Definition: LPC21xx.h:431
#define PINSEL1
Definition: LPC21xx.h:348
#define SSP_PINSEL1_MOSI
#define VIC_SPI1
Definition: lpcVIC.h:81
arch independent LED (Light Emitting Diodes) API
Highspeed SPI Slave Interface.
#define SSP_PINSEL1_MISO
#define SSPCR1
Definition: LPC21xx.h:223
#define SSE
Definition: LPC21xx.h:266
#define SSP_Read()
uint16_t spi_slave_hs_rx_insert_idx
#define SSPIMSC
Definition: LPC21xx.h:227
#define ISR_ENTRY()
Definition: armVIC.h:40
#define VIC_ENABLE
Definition: lpcVIC.h:102