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max3100_hw.c
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2  * Copyright (C) 2009 ENAC
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4  * This file is part of paparazzi.
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21  */
22 
23 #include "LPC21xx.h"
24 #include "interrupt_hw.h"
25 #include "max3100_hw.h"
26 
27 #include "ap_downlink.h"
28 #include "mcu_periph/uart.h"
29 
30 
32 bool volatile max3100_data_available;
34 
37 
40 
41 
42 bool read_bytes = false;
43 
44 
45 static void EXTINT_ISR(void) __attribute__((naked));
46 static void SPI1_ISR(void) __attribute__((naked));
47 
48 #define PINSEL1_SCK (2 << 2)
49 #define PINSEL1_MISO (2 << 4)
50 #define PINSEL1_MOSI (2 << 6)
51 #define PINSEL1_SSEL (2 << 8)
52 
53 /* SSPCR0 settings */
54 #define SSP_DSS 0x0F << 0 /* data size : 16 bits */
55 // #define SSP_DSS 0x07 << 0 /* data size : 8 bits */
56 #define SSP_FRF 0x00 << 4 /* frame format : SPI */
57 #define SSP_CPOL 0x00 << 6 /* clock polarity : idle low */
58 #define SSP_CPHA 0x00 << 7 /* clock phase : 0 */
59 #define SSP_SCR 0x0F << 8 /* serial clock rate : 29.3kHz, SSP input clock / 16 */
60 
61 /* SSPCR1 settings */
62 #define SSP_LBM 0x00 << 0 /* loopback mode : disabled */
63 #define SSP_SSE 0x00 << 1 /* SSP enable : disabled */
64 #define SSP_MS 0x00 << 2 /* master slave mode : master */
65 #define SSP_SOD 0x00 << 3 /* slave output disable : don't care when master */
66 
67 #ifndef SSPCPSR_VAL
68 #define SSPCPSR_VAL 0x04
69 #endif
70 
71 #warning "This driver should be updated to use the new SPI peripheral"
72 
73 #ifndef SPI1_VIC_SLOT
74 #define SPI1_VIC_SLOT 7
75 #endif
76 
77 
78 void max3100_init( void ) {
80  max3100_data_available = false;
86 
87  /* setup pins for SSP (SCK, MISO, MOSI) */
89 
90  /* setup SSP */
93  SSPCPSR = SSPCPSR_VAL; /* Prescaler */
94 
95 
96  /* From arm7/max1167_hw.c */
97 
98  /* SS pin is output */
100  /* unselected max3100 */
101  Max3100Unselect();
102 
103  /* connect extint (IRQ) */
104  MAX3100_IRQ_PINSEL |= MAX3100_IRQ_PINSEL_VAL << MAX3100_IRQ_PINSEL_BIT;
105  /* extint is edge trigered */
106  SetBit(EXTMODE, MAX3100_IRQ_EINT);
107  /* extint is trigered on falling edge */
108  ClearBit(EXTPOLAR, MAX3100_IRQ_EINT);
109  /* clear pending extint0 before enabling interrupts */
110  SetBit(EXTINT, MAX3100_IRQ_EINT);
111 
112  /* Configure interrupt vector for external pin interrupt */
113  VICIntSelect &= ~VIC_BIT( MAX3100_VIC_EINT ); // EXTINT selected as IRQ
114  VICIntEnable = VIC_BIT( MAX3100_VIC_EINT ); // EXTINT interrupt enabled
115  VICVectCntl8 = VIC_ENABLE | MAX3100_VIC_EINT;
116  VICVectAddr8 = (uint32_t)EXTINT_ISR; // address of the ISR
117 
118  /* Configure interrupt vector for SPI */
119  VICIntSelect &= ~VIC_BIT(VIC_SPI1); /* SPI1 selected as IRQ */
120  VICIntEnable = VIC_BIT(VIC_SPI1); /* SPI1 interrupt enabled */
122  _VIC_CNTL(SPI1_VIC_SLOT) = (uint32_t)SPI1_ISR; /* address of the ISR */
123 
124  /* Write configuration */
125  //Max3100TransmitConf(MAX3100_BAUD_RATE | MAX3100_BIT_NOT_TM);
127 }
128 
129 
130 /******* External interrupt: Data input available ***********/
131 void EXTINT_ISR(void) {
132  ISR_ENTRY();
133 
134  max3100_data_available = true;
135 
136  SetBit(EXTINT, MAX3100_IRQ_EINT); /* clear extint */
137  VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
138 
139  ISR_EXIT();
140 }
141 
142 void SPI1_ISR(void) {
143  ISR_ENTRY();
144 
145  while (bit_is_set(SSPSR, RNE)) {
146  uint16_t data = SSPDR;
147 
148  if (bit_is_set(data, MAX3100_R_BIT)) { /* Data available */
149  max3100_rx_buf[max3100_rx_insert_idx] = data & 0xff;
150  max3100_rx_insert_idx++; // automatic overflow because len=256
151  read_bytes = true;
152  }
153  if (bit_is_set(data, MAX3100_T_BIT) && (max3100_status == MAX3100_STATUS_READING)) { /* transmit buffer empty */
155  }
156  }
157  SpiClearRti(); /* clear interrupt */
158  SpiDisableRti();
159  SpiDisable ();
160  Max3100Unselect();
162 
163  VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
164  ISR_EXIT();
165 }
166 
167 void max3100_debug(void) {
168  /*** DOWNLINK_SEND_DEBUG(DefaultChannel, DefaultDevice, 16, max3100_rx_buf); ***/
169 }
#define SSPCPSR_VAL
Definition: max3100_hw.c:68
#define VICIntSelect
Definition: LPC21xx.h:430
unsigned short uint16_t
Definition: types.h:16
#define Max3100TransmitConf(_conf)
Definition: max3100_hw.h:114
arch independent UART (Universal Asynchronous Receiver/Transmitter) API
uint8_t volatile max3100_tx_insert_idx
Definition: max3100_hw.c:35
#define SSP_MS
Definition: max3100_hw.c:64
#define SPI1_VIC_SLOT
Definition: max3100_hw.c:74
static void SpiClearRti(struct spi_periph *p)
Definition: spi_arch.c:151
#define SSPCPSR
Definition: LPC21xx.h:226
#define _VIC_CNTL(idx)
Definition: armVIC.h:19
#define Max3100Unselect()
Definition: max3100_hw.h:63
bool volatile max3100_data_available
Definition: max3100_hw.c:32
#define EXTMODE
Definition: LPC21xx.h:419
#define SpiDisable()
#define MAX3100_TX_BUF_LEN
I/O Buffers.
Definition: max3100_hw.h:47
uint8_t volatile max3100_status
Definition: max3100_hw.c:31
uint8_t volatile max3100_rx_extract_idx
Definition: max3100_hw.c:36
uint8_t volatile max3100_tx_buf[MAX3100_TX_BUF_LEN]
Definition: max3100_hw.c:38
#define SSPCR0
Definition: LPC21xx.h:222
static void SPI1_ISR(void)
Definition: max3100_hw.c:142
#define SSP_SOD
Definition: max3100_hw.c:65
#define MAX3100_R_BIT
Definition: max3100_hw.h:88
uint8_t volatile max3100_tx_extract_idx
Definition: max3100_hw.c:35
bool read_bytes
Definition: max3100_hw.c:42
#define VICVectAddr8
Definition: LPC21xx.h:446
#define MAX3100_BIT_NOT_TM
Definition: max3100_hw.h:85
#define EXTPOLAR
Definition: LPC21xx.h:420
#define EXTINT
Definition: LPC21xx.h:417
bool volatile max3100_transmit_buffer_empty
Definition: max3100_hw.c:33
#define SSP_DSS
Definition: max3100_hw.c:54
#define SSPSR
Definition: LPC21xx.h:225
#define MAX3100_T_BIT
Definition: max3100_hw.h:87
#define PINSEL1_MOSI
Definition: max3100_hw.c:50
#define VICVectAddr
Definition: LPC21xx.h:436
#define PINSEL1_SCK
Definition: max3100_hw.c:48
unsigned long uint32_t
Definition: types.h:18
void max3100_debug(void)
Definition: max3100_hw.c:167
#define SSP_FRF
Definition: max3100_hw.c:56
void max3100_init(void)
Definition: max3100_hw.c:78
#define MAX3100_SS_PIN
Definition: max3100_hw.h:28
#define SSP_CPOL
Definition: max3100_hw.c:57
#define VIC_BIT(chan)
Definition: lpcVIC.h:105
#define RNE
Definition: LPC21xx.h:279
#define SSP_CPHA
Definition: max3100_hw.c:58
#define SSP_LBM
Definition: max3100_hw.c:62
uint8_t volatile max3100_rx_buf[MAX3100_RX_BUF_LEN]
Definition: max3100_hw.c:39
#define VICVectCntl8
Definition: LPC21xx.h:462
#define SSP_SCR
Definition: max3100_hw.c:59
unsigned char uint8_t
Definition: types.h:14
#define SSPDR
Definition: LPC21xx.h:224
#define ISR_EXIT()
Definition: armVIC.h:61
#define MAX3100_BIT_NOT_RM
Definition: max3100_hw.h:84
#define MAX3100_STATUS_IDLE
Max3100 protocol status.
Definition: max3100_hw.h:38
#define MAX3100_STATUS_READING
Definition: max3100_hw.h:40
#define VICIntEnable
Definition: LPC21xx.h:431
#define PINSEL1
Definition: LPC21xx.h:348
#define VIC_SPI1
Definition: lpcVIC.h:81
#define MAX3100_SS_IODIR
Definition: max3100_hw.h:34
static void EXTINT_ISR(void)
Definition: max3100_hw.c:131
#define PINSEL1_MISO
Definition: max3100_hw.c:49
static void SpiDisableRti(struct spi_periph *p)
Definition: spi_arch.c:147
#define SSPCR1
Definition: LPC21xx.h:223
#define MAX3100_RX_BUF_LEN
Definition: max3100_hw.h:48
#define ISR_ENTRY()
Definition: armVIC.h:40
uint8_t volatile max3100_rx_insert_idx
Definition: max3100_hw.c:36
#define VIC_ENABLE
Definition: lpcVIC.h:102