Paparazzi UAS  v5.0.5_stable-7-g4b8bbb7
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lpcSCB.h
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1 /******************************************************************************
2  *
3  * $RCSfile$
4  * $Revision$
5  *
6  * Header file for Philips LPC ARM Processors.
7  * Copyright 2004 R O SoftWare
8  *
9  * No guarantees, warrantees, or promises, implied or otherwise.
10  * May be used for hobby or commercial purposes provided copyright
11  * notice remains intact.
12  *
13  *****************************************************************************/
14 #ifndef INC_LPC_SCB_H
15 #define INC_LPC_SCB_H
16 
17 // System Control Block Registers
18 typedef struct
19 {
20  // Memory Accelerator Module Registers (MAM)
21  struct
22  {
23  REG_8 cr; // Control Register
24  REG_8 _pad0[3];
25  REG_8 tim; // Timing Control Register
26  REG32 _pad1[14];
27  } mam;
28 
29  // Memory Mapping Control Register
31  REG32 _pad0[15];
32 
33  // Phase Locked Loop Registers (PLL)
34  struct
35  {
36  REG_8 con; // Control Register
37  REG_8 _pad0[3];
38  REG_8 cfg; // Configuration Register
39  REG_8 _pad1[3];
40  REG16 stat; // Status Register
42  REG_8 feed; // Feed Register
43  REG32 _pad3[12];
44  } pll;
45 
46  // Power Control Registers
47  struct
48  {
49  REG_8 con; // Control Register
50  REG_8 _pad0[3];
51  REG32 conp; // Peripherals Register
52  REG32 _pad1[14];
53  } p;
54 
55  // VPB Divider Register
57  REG32 _pad1[15];
58 
59  // External Interrupt Registers
60  struct
61  {
62  REG_8 flag; // Flag Register
63  REG_8 _pad0[3];
64  REG_8 wake; // Wakeup Register
65  REG_8 _pad1[3];
66  REG_8 mode; // Mode Register
67  REG_8 _pad2[3];
68  REG_8 polar; // Polarity Register
69  REG32 _pad3[12];
70  } ext;
71 } scbRegs_t;
72 
73 
75 // MAM defines
76 #define MAMCR_OFF 0
77 #define MAMCR_PART 1
78 #define MAMCR_FULL 2
79 
80 #define MAMTIM_CYCLES (((CCLK) + 19999999) / 20000000)
81 
83 // MEMMAP defines
84 #define MEMMAP_BBLK 0 // Interrupt Vectors in Boot Block
85 #define MEMMAP_FLASH 1 // Interrupt Vectors in Flash
86 #define MEMMAP_SRAM 2 // Interrupt Vectors in SRAM
87 
89 // PLL defines & computations
90 // Compute the value of PLL_DIV and test range validity
91 // FOSC & PLL_MUL should be defined in project configuration file (config.h)
92 #ifndef CCLK
93 #define CCLK (FOSC * PLL_MUL) // CPU Clock Freq.
94 #endif
95 
96 #define FCCO_MAX (320000000) // Max CC Osc Freq.
97 #define PLL_DIV (FCCO_MAX / (2 * CCLK)) // PLL Divider
98 #define FCCO (FOSC * PLL_MUL * 2 * PLL_DIV) // CC Osc. Freq.
99 
100 // PLLCON Register Bit Definitions
101 #define PLLCON_PLLE (1 << 0) // PLL Enable
102 #define PLLCON_PLLC (1 << 1) // PLL Connect
103 
104 // PLLCFG Register Bit Definitions
105 #define PLLCFG_MSEL ((PLL_MUL - 1) << 0) // PLL Multiplier
106 #define PLLCFG_PSEL ((PLL_DIV - 1) << 5) // PLL Divider
107 
108 // PLLSTAT Register Bit Definitions
109 #define PLLSTAT_LOCK (1 << 10) // PLL Lock Status Bit
110 
112 // VPBDIV defines & computations
113 #define VPBDIV_VALUE (PBSD_BITS & 0x03) // VPBDIV value
114 
115 #endif
REG_8 con
Definition: lpcSCB.h:36
#define REG32
Definition: LPC21xx.h:20
#define REG_8
Definition: LPC21xx.h:18
REG_8 cfg
Definition: lpcSCB.h:38
REG_8 wake
Definition: lpcSCB.h:64
REG16 stat
Definition: lpcSCB.h:40
REG_8 memmap
Definition: lpcSCB.h:30
REG_8 feed
Definition: lpcSCB.h:42
REG_8 cr
Definition: lpcSCB.h:23
REG_8 polar
Definition: lpcSCB.h:68
REG_8 mode
Definition: lpcSCB.h:66
REG32 conp
Definition: lpcSCB.h:51
REG_8 vpbdiv
Definition: lpcSCB.h:56
#define REG16
Definition: LPC21xx.h:19
static float p[2][2]
REG16 _pad2
Definition: lpcSCB.h:41
REG_8 flag
Definition: lpcSCB.h:62
REG_8 tim
Definition: lpcSCB.h:25