Paparazzi UAS  v5.0.5_stable-7-g4b8bbb7
Paparazzi is a free software Unmanned Aircraft System.
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imu_crista_arch.c
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1 /*
2  * Copyright (C) 2008-2009 Antoine Drouin <poinix@gmail.com>
3  *
4  * This file is part of paparazzi.
5  *
6  * paparazzi is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2, or (at your option)
9  * any later version.
10  *
11  * paparazzi is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
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17  * along with paparazzi; see the file COPYING. If not, write to
18  * the Free Software Foundation, 59 Temple Place - Suite 330,
19  * Boston, MA 02111-1307, USA.
20  */
21 
22 #include "subsystems/imu.h"
23 
24 #include "LPC21xx.h"
25 #include "armVIC.h"
26 #include "ssp_hw.h"
27 #include BOARD_CONFIG
28 
29 #define ADS8344_SS_IODIR IO0DIR
30 #define ADS8344_SS_IOSET IO0SET
31 #define ADS8344_SS_IOCLR IO0CLR
32 #define ADS8344_SS_PIN 20
33 
34 #define ADS8344Select() SetBit(ADS8344_SS_IOCLR,ADS8344_SS_PIN)
35 #define ADS8344Unselect() SetBit(ADS8344_SS_IOSET,ADS8344_SS_PIN)
36 
37 #define POWER_MODE (1 << 1 | 1)
38 #define SGL_DIF 1 // Single ended
39 
40 /* SSPCR0 settings */
41 #define SSP_DSS 0x07 << 0 /* data size : 8 bits */
42 #define SSP_FRF 0x00 << 4 /* frame format : SPI */
43 #define SSP_CPOL 0x00 << 6 /* clock polarity : idle low */
44 #define SSP_CPHA 0x00 << 7 /* clock phase : 1 */
45 #define SSP_SCR 0x09 << 8 /* serial clock rate : 1MHz */
46 
47 /* SSPCR1 settings */
48 #define SSP_LBM 0x00 << 0 /* loopback mode : disabled */
49 #define SSP_SSE 0x00 << 1 /* SSP enable : disabled */
50 #define SSP_MS 0x00 << 2 /* master slave mode : master */
51 #define SSP_SOD 0x00 << 3 /* slave output disable : disabled */
52 
53 static void SPI1_ISR(void) __attribute__((naked));
55 
56 #warning "This driver should be updated to use the new SPI peripheral"
57 
59  channel = 0;
60 
61  /* setup pins for SSP (SCK, MISO, MOSI) */
62  PINSEL1 |= 2 << 2 | 2 << 4 | 2 << 6;
63 
64  /* setup SSP */
67  SSPCPSR = 2; /* -> 50kHz */
68 
69  /* initialize interrupt vector */
70  VICIntSelect &= ~VIC_BIT(VIC_SPI1); // SPI1 selected as IRQ
71  VICIntEnable = VIC_BIT(VIC_SPI1); // SPI1 interrupt enabled
73  _VIC_ADDR(SPI1_VIC_SLOT) = (uint32_t)SPI1_ISR; // address of the ISR
74 
75  /* setup slave select */
76  /* configure SS pin */
77  SetBit( ADS8344_SS_IODIR, ADS8344_SS_PIN); /* pin is output */
78  ADS8344Unselect(); /* pin low */
79 }
80 
81 
82 static inline void read_values( void ) {
83  uint8_t foo __attribute__ ((unused)) = SSPDR;
84  uint8_t msb = SSPDR;
85  uint8_t lsb = SSPDR;
86  uint8_t llsb = SSPDR;
87  ADS8344_values[channel] = (msb << 8 | lsb) << 1 | llsb >> 7;
88 }
89 
90 static inline void send_request( void ) {
91  uint8_t control = 1 << 7 | channel << 4 | SGL_DIF << 2 | POWER_MODE;
92  SSP_Send(control);
93  SSP_Send(0);
94  SSP_Send(0);
95  SSP_Send(0);
96 }
97 
98 void ADS8344_start( void ) {
99  ADS8344Select();
100  SSP_ClearRti();
101  SSP_EnableRti();
102  SSP_Enable();
103  send_request();
104 }
105 
106 void SPI1_ISR(void) {
107  ISR_ENTRY();
108  read_values();
109  channel++;
110  if (channel > 7-1) {
111  channel = 0;
113  ADS8344Unselect();
114  }
115  else {
116  send_request();
117  }
118 
119  SSP_ClearRti();
120 
121  VICVectAddr = 0x00000000; /* clear this interrupt from the VIC */
122  ISR_EXIT();
123 }
#define VICIntSelect
Definition: LPC21xx.h:430
#define SSP_LBM
#define ADS8344_SS_PIN
#define SSP_DSS
#define SSP_Send(_a)
Definition: ssp_hw.h:16
#define SSP_CPOL
#define SSP_SCR
#define SSP_MS
#define SSPCPSR
Definition: LPC21xx.h:226
#define _VIC_CNTL(idx)
Definition: armVIC.h:19
#define SSP_FRF
#define ADS8344_SS_IODIR
#define ADS8344Select()
uint16_t ADS8344_values[NB_CHANNELS]
Definition: ADS8344.c:39
#define SSP_Enable()
Definition: max11040_hw.h:44
bool_t ADS8344_available
Definition: ADS8344.c:38
#define SSPCR0
Definition: LPC21xx.h:222
#define _VIC_ADDR(idx)
Definition: armVIC.h:20
#define SGL_DIF
#define SSP_CPHA
static void send_request(void)
#define VICVectAddr
Definition: LPC21xx.h:436
unsigned long uint32_t
Definition: types.h:18
uint16_t foo
Definition: main_demo5.c:54
Inertial Measurement Unit interface.
#define SSP_SOD
#define VIC_BIT(chan)
Definition: lpcVIC.h:105
#define SSP_EnableRti()
Definition: max11040_hw.h:52
#define TRUE
Definition: imu_chimu.h:144
static void SPI1_ISR(void)
#define SPI1_VIC_SLOT
Definition: ADS8344.c:85
void ADS8344_start(void)
unsigned char uint8_t
Definition: types.h:14
#define SSPDR
Definition: LPC21xx.h:224
#define POWER_MODE
#define ISR_EXIT()
Definition: armVIC.h:61
#define SSP_ClearRti()
Definition: max11040_hw.h:54
void imu_crista_arch_init(void)
#define VICIntEnable
Definition: LPC21xx.h:431
#define PINSEL1
Definition: LPC21xx.h:348
#define VIC_SPI1
Definition: lpcVIC.h:81
#define ADS8344Unselect()
#define SSPCR1
Definition: LPC21xx.h:223
static uint8_t channel
#define ISR_ENTRY()
Definition: armVIC.h:40
static void read_values(void)
#define VIC_ENABLE
Definition: lpcVIC.h:102