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armVIC.h
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1 /******************************************************************************
2  *
3  * $RCSfile$
4  * $Revision$
5  *
6  * This module provides the interface definitions for setting up and
7  * controlling the various interrupt modes present on the ARM processor.
8  * Copyright 2004, R O SoftWare
9  * No guarantees, warrantees, or promises, implied or otherwise.
10  * May be used for hobby or commercial purposes provided copyright
11  * notice remains intact.
12  *
13  *****************************************************************************/
14 #ifndef INC_ARM_VIC_H
15 #define INC_ARM_VIC_H
16 
17 #define __VIC_CNTL(idx) VICVectCntl##idx
18 #define __VIC_ADDR(idx) VICVectAddr##idx
19 #define _VIC_CNTL(idx) __VIC_CNTL(idx)
20 #define _VIC_ADDR(idx) __VIC_ADDR(idx)
21 
22 
23 /******************************************************************************
24  *
25  * MACRO Name: ISR_ENTRY()
26  *
27  * Description:
28  * This MACRO is used upon entry to an ISR. The current version of
29  * the gcc compiler for ARM does not produce correct code for
30  * interrupt routines to operate properly with THUMB code. The MACRO
31  * performs the following steps:
32  *
33  * 1 - Adjust address at which execution should resume after servicing
34  * ISR to compensate for IRQ entry
35  * 2 - Save the non-banked registers r0-r12 and lr onto the IRQ stack.
36  * 3 - Get the status of the interrupted program is in SPSR.
37  * 4 - Push it onto the IRQ stack as well.
38  *
39  *****************************************************************************/
40 #define ISR_ENTRY() asm volatile(" sub lr, lr,#4\n" \
41  " stmfd sp!,{r0-r12,lr}\n" \
42  " mrs r1, spsr\n" \
43  " stmfd sp!,{r1}")
44 
45 /******************************************************************************
46  *
47  * MACRO Name: ISR_EXIT()
48  *
49  * Description:
50  * This MACRO is used to exit an ISR. The current version of the gcc
51  * compiler for ARM does not produce correct code for interrupt
52  * routines to operate properly with THUMB code. The MACRO performs
53  * the following steps:
54  *
55  * 1 - Recover SPSR value from stack
56  * 2 - and restore its value
57  * 3 - Pop the return address & the saved general registers from
58  * the IRQ stack & return
59  *
60  *****************************************************************************/
61 #define ISR_EXIT() asm volatile(" ldmfd sp!,{r1}\n" \
62  " msr spsr_c,r1\n" \
63  " ldmfd sp!,{r0-r12,pc}^")
64 
65 /******************************************************************************
66  *
67  * Function Name: disableIRQ()
68  *
69  * Description:
70  * This function sets the IRQ disable bit in the status register
71  *
72  * Calling Sequence:
73  * void
74  *
75  * Returns:
76  * previous value of CPSR
77  *
78  *****************************************************************************/
79 unsigned disableIRQ(void);
80 
81 /******************************************************************************
82  *
83  * Function Name: enableIRQ()
84  *
85  * Description:
86  * This function clears the IRQ disable bit in the status register
87  *
88  * Calling Sequence:
89  * void
90  *
91  * Returns:
92  * previous value of CPSR
93  *
94  *****************************************************************************/
95 unsigned enableIRQ(void);
96 
97 /******************************************************************************
98  *
99  * Function Name: restoreIRQ()
100  *
101  * Description:
102  * This function restores the IRQ disable bit in the status register
103  * to the value contained within passed oldCPSR
104  *
105  * Calling Sequence:
106  * void
107  *
108  * Returns:
109  * previous value of CPSR
110  *
111  *****************************************************************************/
112 unsigned restoreIRQ(unsigned oldCPSR);
113 
114 /******************************************************************************
115  *
116  * Function Name: disableFIQ()
117  *
118  * Description:
119  * This function sets the FIQ disable bit in the status register
120  *
121  * Calling Sequence:
122  * void
123  *
124  * Returns:
125  * previous value of CPSR
126  *
127  *****************************************************************************/
128 unsigned disableFIQ(void);
129 
130 /******************************************************************************
131  *
132  * Function Name: enableFIQ()
133  *
134  * Description:
135  * This function clears the FIQ disable bit in the status register
136  *
137  * Calling Sequence:
138  * void
139  *
140  * Returns:
141  * previous value of CPSR
142  *
143  *****************************************************************************/
144 unsigned enableFIQ(void);
145 
146 /******************************************************************************
147  *
148  * Function Name: restoreIRQ()
149  *
150  * Description:
151  * This function restores the FIQ disable bit in the status register
152  * to the value contained within passed oldCPSR
153  *
154  * Calling Sequence:
155  * void
156  *
157  * Returns:
158  * previous value of CPSR
159  *
160  *****************************************************************************/
161 unsigned restoreFIQ(unsigned oldCPSR);
162 
163 #endif
unsigned enableFIQ(void)
Definition: armVIC.c:78
unsigned disableFIQ(void)
Definition: armVIC.c:60
unsigned restoreIRQ(unsigned oldCPSR)
Definition: armVIC.c:42
unsigned restoreFIQ(unsigned oldCPSR)
Definition: armVIC.c:69
unsigned disableIRQ(void)
Definition: armVIC.c:33
unsigned enableIRQ(void)
Definition: armVIC.c:51