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max1168_arch.c
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1 /*
2  * $Id$
3  *
4  * Copyright (C) 2010 Antoine Drouin <poinix@gmail.com>
5  *
6  * This file is part of paparazzi.
7  *
8  * paparazzi is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2, or (at your option)
11  * any later version.
12  *
13  * paparazzi is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
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20  * the Free Software Foundation, 59 Temple Place - Suite 330,
21  * Boston, MA 02111-1307, USA.
22  */
23 #include "peripherals/max1168.h"
24 
25 #include <stm32/rcc.h>
26 #include <stm32/spi.h>
27 #include <stm32/exti.h>
28 #include <stm32/misc.h>
29 #include <stm32/dma.h>
30 
31 
32 /* I can't use GPIOD as it's already defined in some system header */
33 #define __DRDY_PORT(dev, _x) _x##dev
34 #define _DRDY_PORT(dev, _x) __DRDY_PORT(dev, _x)
35 #define DRDY_PORT(_x) _DRDY_PORT(MAX_1168_DRDY_PORT, _x)
36 
37 #define __DRDY_PORT_SOURCE(dev, _x) _x##dev
38 #define _DRDY_PORT_SOURCE(dev, _x) __DRDY_PORT_SOURCE(dev, _x)
39 #define DRDY_PORT_SOURCE(_x) _DRDY_PORT_SOURCE(MAX_1168_DRDY_PORT_SOURCE, _x)
40 
41 void exti2_irq_handler(void);
42 
43 void max1168_arch_init( void ) {
44 
45  /* set slave select as output and assert it ( on PB12) */
47  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
48  GPIO_InitTypeDef GPIO_InitStructure;
49  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
50  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
51  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
52  GPIO_Init(GPIOB, &GPIO_InitStructure);
53 
54  /* configure external interrupt exti2 on PD2( data ready ) v1.0*/
55  /* PB2( data ready ) v1.1*/
56  // RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_AFIO, ENABLE);
57  RCC_APB2PeriphClockCmd(DRDY_PORT(RCC_APB2Periph) | RCC_APB2Periph_AFIO, ENABLE);
58  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
59  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
60  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
61  GPIO_Init(GPIOD, &GPIO_InitStructure);
62 
63  EXTI_InitTypeDef EXTI_InitStructure;
64  // GPIO_EXTILineConfig(GPIO_PortSourceGPIOD, GPIO_PinSource2);
65  GPIO_EXTILineConfig(DRDY_PORT_SOURCE(GPIO_), GPIO_PinSource2);
66  EXTI_InitStructure.EXTI_Line = EXTI_Line2;
67  EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
68  EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
69  EXTI_InitStructure.EXTI_LineCmd = ENABLE;
70  EXTI_Init(&EXTI_InitStructure);
71 
72  NVIC_InitTypeDef NVIC_InitStructure;
73  NVIC_InitStructure.NVIC_IRQChannel = EXTI2_IRQn;
74  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F;
75  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F;
76  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
77 
78  NVIC_Init(&NVIC_InitStructure);
79 
80 #ifdef MAX1168_HANDLES_DMA_IRQ
81  /* Enable DMA1 channel4 IRQ Channel */
82  NVIC_InitTypeDef NVIC_init_struct = {
83  .NVIC_IRQChannel = DMA1_Channel4_IRQn,
84  .NVIC_IRQChannelPreemptionPriority = 0,
85  .NVIC_IRQChannelSubPriority = 0,
86  .NVIC_IRQChannelCmd = ENABLE
87  };
88  NVIC_Init(&NVIC_init_struct);
89 #endif /* MAX1168_HANDLES_DMA_IRQ */
90 }
91 
92 void max1168_read( void ) {
93  /* ASSERT((max1168_status == STA_MAX1168_IDLE), \
94  * DEBUG_MAX_1168, MAX1168_ERR_READ_OVERUN);
95  */
96  /* select max1168 */
97  Max1168Select();
98 
99  /* write control byte - wait EOC on extint */
100  /* use internal reference and clock, sequentially scan channels 0-7 */
101  const uint16_t ctl_byte = (1 << 0 | 1 << 3 | 7 << 5) << 8;
102  SPI_I2S_SendData(SPI2, ctl_byte);
104 
105 }
106 
107 void exti2_irq_handler(void) {
108 
109  /* ASSERT((max1168_status == STA_MAX1168_SENDING_REQ), \
110  * DEBUG_MAX_1168, MAX1168_ERR_SPURIOUS_EOC);
111  */
112 
113  /* clear EXTI */
114  if(EXTI_GetITStatus(EXTI_Line2) != RESET)
115  EXTI_ClearITPendingBit(EXTI_Line2);
116 
117  /* read control byte FIXME: is this needed ?, yes*/
118  uint16_t foo __attribute__ ((unused)) = SPI_I2S_ReceiveData(SPI2);
119 
120  /* trigger 8 frames read */
121  /* SPI2_Rx_DMA_Channel configuration ------------------------------------*/
122  DMA_DeInit(DMA1_Channel4);
123  DMA_InitTypeDef DMA_initStructure_4 = {
124  .DMA_PeripheralBaseAddr = (uint32_t)(SPI2_BASE+0x0C),
125  .DMA_MemoryBaseAddr = (uint32_t)max1168_values,
126  .DMA_DIR = DMA_DIR_PeripheralSRC,
127  .DMA_BufferSize = MAX1168_NB_CHAN,
128  .DMA_PeripheralInc = DMA_PeripheralInc_Disable,
129  .DMA_MemoryInc = DMA_MemoryInc_Enable,
130  .DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord,
131  .DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord,
132  .DMA_Mode = DMA_Mode_Normal,
133  .DMA_Priority = DMA_Priority_VeryHigh,
134  .DMA_M2M = DMA_M2M_Disable
135  };
136  DMA_Init(DMA1_Channel4, &DMA_initStructure_4);
137 
138  /* SPI2_Tx_DMA_Channel configuration ------------------------------------*/
139  DMA_DeInit(DMA1_Channel5);
140  DMA_InitTypeDef DMA_initStructure_5 = {
141  .DMA_PeripheralBaseAddr = (uint32_t)(SPI2_BASE+0x0C),
142  .DMA_MemoryBaseAddr = (uint32_t)max1168_values,
143  .DMA_DIR = DMA_DIR_PeripheralDST,
144  .DMA_BufferSize = MAX1168_NB_CHAN,
145  .DMA_PeripheralInc = DMA_PeripheralInc_Disable,
146  .DMA_MemoryInc = DMA_MemoryInc_Enable,
147  .DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord,
148  .DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord,
149  .DMA_Mode = DMA_Mode_Normal,
150  .DMA_Priority = DMA_Priority_Medium,
151  .DMA_M2M = DMA_M2M_Disable
152  };
153  DMA_Init(DMA1_Channel5, &DMA_initStructure_5);
154 
155  /* Enable SPI_2 Rx request */
156  SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Rx, ENABLE);
157  /* Enable DMA1 Channel4 */
158  DMA_Cmd(DMA1_Channel4, ENABLE);
159 
160  /* Enable SPI_2 Tx request */
161  SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, ENABLE);
162  /* Enable DMA1 Channel5 */
163  DMA_Cmd(DMA1_Channel5, ENABLE);
164 
165  /* Enable DMA1 Channel4 Transfer Complete interrupt */
166  DMA_ITConfig(DMA1_Channel4, DMA_IT_TC, ENABLE);
167 
169 }
170 
171 #ifdef MAX1168_HANDLES_DMA_IRQ
172 void dma1_c4_irq_handler(void) {
173  Max1168OnDmaIrq();
174 }
175 #endif /*MAX1168_HANDLES_DMA_IRQ */
unsigned short uint16_t
Definition: types.h:16
#define DRDY_PORT_SOURCE(_x)
Definition: max1168_arch.c:39
void max1168_arch_init(void)
Definition: max1168_arch.c:26
uint16_t max1168_values[MAX1168_NB_CHAN]
Definition: max1168.c:29
void dma1_c4_irq_handler(void)
#define Max1168Unselect()
Definition: max1168_arch.h:57
#define DRDY_PORT(_x)
Definition: max1168_arch.c:35
unsigned long uint32_t
Definition: types.h:18
uint16_t foo
Definition: main_demo5.c:54
#define MAX1168_NB_CHAN
Definition: max1168.h:29
volatile uint8_t max1168_status
Definition: max1168.c:28
#define Max1168OnDmaIrq()
Definition: max1168_arch.h:38
void exti2_irq_handler(void)
Definition: max1168_arch.c:107
#define STA_MAX1168_READING_RES
Definition: max1168.h:35
void max1168_read(void)
Definition: max1168_arch.c:52
#define RESET
Definition: humid_sht.h:40
#define STA_MAX1168_SENDING_REQ
Definition: max1168.h:34
__attribute__((always_inline))
Definition: i2c_arch.c:35
#define Max1168Select()
Definition: max1168_arch.h:58